LXR linux/arch/arm/mach-shmobile/setup-sh73a0.c

   1/*
   2 * sh73a0 processor support
   3 *
   4 * Copyright (C) 2010  Takashi Yoshii
   5 * Copyright (C) 2010  Magnus Damm
   6 * Copyright (C) 2008  Yoshihiro Shimoda
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; version 2 of the License.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20 */
  21#include <linux/kernel.h>
  22#include <linux/init.h>
  23#include <linux/interrupt.h>
  24#include <linux/irq.h>
  25#include <linux/irqchip.h>
  26#include <linux/platform_device.h>
  27#include <linux/of_platform.h>
  28#include <linux/delay.h>
  29#include <linux/input.h>
  30#include <linux/io.h>
  31#include <linux/serial_sci.h>
  32#include <linux/sh_dma.h>
  33#include <linux/sh_intc.h>
  34#include <linux/sh_timer.h>
  35#include <linux/platform_data/sh_ipmmu.h>
  36#include <linux/platform_data/irq-renesas-intc-irqpin.h>
  37#include <mach/dma-register.h>
  38#include <mach/hardware.h>
  39#include <mach/irqs.h>
  40#include <mach/sh73a0.h>
  41#include <mach/common.h>
  42#include <asm/mach-types.h>
  43#include <asm/mach/map.h>
  44#include <asm/mach/arch.h>
  45#include <asm/mach/time.h>
  46
  47static struct map_desc sh73a0_io_desc[] __initdata = {
  48        /* create a 1:1 entity map for 0xe6xxxxxx
  49         * used by CPGA, INTC and PFC.
  50         */
  51        {
  52                .virtual        = 0xe6000000,
  53                .pfn            = __phys_to_pfn(0xe6000000),
  54                .length         = 256 << 20,
  55                .type           = MT_DEVICE_NONSHARED
  56        },
  57};
  58
  59void __init sh73a0_map_io(void)
  60{
  61        iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
  62}
  63
  64static struct resource sh73a0_pfc_resources[] = {
  65        [0] = {
  66                .start  = 0xe6050000,
  67                .end    = 0xe6057fff,
  68                .flags  = IORESOURCE_MEM,
  69        },
  70        [1] = {
  71                .start  = 0xe605801c,
  72                .end    = 0xe6058027,
  73                .flags  = IORESOURCE_MEM,
  74        }
  75};
  76
  77static struct platform_device sh73a0_pfc_device = {
  78        .name           = "pfc-sh73a0",
  79        .id             = -1,
  80        .resource       = sh73a0_pfc_resources,
  81        .num_resources  = ARRAY_SIZE(sh73a0_pfc_resources),
  82};
  83
  84void __init sh73a0_pinmux_init(void)
  85{
  86        platform_device_register(&sh73a0_pfc_device);
  87}
  88
  89static struct plat_sci_port scif0_platform_data = {
  90        .mapbase        = 0xe6c40000,
  91        .flags          = UPF_BOOT_AUTOCONF,
  92        .scscr          = SCSCR_RE | SCSCR_TE,
  93        .scbrr_algo_id  = SCBRR_ALGO_4,
  94        .type           = PORT_SCIFA,
  95        .irqs           = { gic_spi(72), gic_spi(72),
  96                            gic_spi(72), gic_spi(72) },
  97};
  98
  99static struct platform_device scif0_device = {
 100        .name           = "sh-sci",
 101        .id             = 0,
 102        .dev            = {
 103                .platform_data  = &scif0_platform_data,
 104        },
 105};
 106
 107static struct plat_sci_port scif1_platform_data = {
 108        .mapbase        = 0xe6c50000,
 109        .flags          = UPF_BOOT_AUTOCONF,
 110        .scscr          = SCSCR_RE | SCSCR_TE,
 111        .scbrr_algo_id  = SCBRR_ALGO_4,
 112        .type           = PORT_SCIFA,
 113        .irqs           = { gic_spi(73), gic_spi(73),
 114                            gic_spi(73), gic_spi(73) },
 115};
 116
 117static struct platform_device scif1_device = {
 118        .name           = "sh-sci",
 119        .id             = 1,
 120        .dev            = {
 121                .platform_data  = &scif1_platform_data,
 122        },
 123};
 124
 125static struct plat_sci_port scif2_platform_data = {
 126        .mapbase        = 0xe6c60000,
 127        .flags          = UPF_BOOT_AUTOCONF,
 128        .scscr          = SCSCR_RE | SCSCR_TE,
 129        .scbrr_algo_id  = SCBRR_ALGO_4,
 130        .type           = PORT_SCIFA,
 131        .irqs           = { gic_spi(74), gic_spi(74),
 132                            gic_spi(74), gic_spi(74) },
 133};
 134
 135static struct platform_device scif2_device = {
 136        .name           = "sh-sci",
 137        .id             = 2,
 138        .dev            = {
 139                .platform_data  = &scif2_platform_data,
 140        },
 141};
 142
 143static struct plat_sci_port scif3_platform_data = {
 144        .mapbase        = 0xe6c70000,
 145        .flags          = UPF_BOOT_AUTOCONF,
 146        .scscr          = SCSCR_RE | SCSCR_TE,
 147        .scbrr_algo_id  = SCBRR_ALGO_4,
 148        .type           = PORT_SCIFA,
 149        .irqs           = { gic_spi(75), gic_spi(75),
 150                            gic_spi(75), gic_spi(75) },
 151};
 152
 153static struct platform_device scif3_device = {
 154        .name           = "sh-sci",
 155        .id             = 3,
 156        .dev            = {
 157                .platform_data  = &scif3_platform_data,
 158        },
 159};
 160
 161static struct plat_sci_port scif4_platform_data = {
 162        .mapbase        = 0xe6c80000,
 163        .flags          = UPF_BOOT_AUTOCONF,
 164        .scscr          = SCSCR_RE | SCSCR_TE,
 165        .scbrr_algo_id  = SCBRR_ALGO_4,
 166        .type           = PORT_SCIFA,
 167        .irqs           = { gic_spi(78), gic_spi(78),
 168                            gic_spi(78), gic_spi(78) },
 169};
 170
 171static struct platform_device scif4_device = {
 172        .name           = "sh-sci",
 173        .id             = 4,
 174        .dev            = {
 175                .platform_data  = &scif4_platform_data,
 176        },
 177};
 178
 179static struct plat_sci_port scif5_platform_data = {
 180        .mapbase        = 0xe6cb0000,
 181        .flags          = UPF_BOOT_AUTOCONF,
 182        .scscr          = SCSCR_RE | SCSCR_TE,
 183        .scbrr_algo_id  = SCBRR_ALGO_4,
 184        .type           = PORT_SCIFA,
 185        .irqs           = { gic_spi(79), gic_spi(79),
 186                            gic_spi(79), gic_spi(79) },
 187};
 188
 189static struct platform_device scif5_device = {
 190        .name           = "sh-sci",
 191        .id             = 5,
 192        .dev            = {
 193                .platform_data  = &scif5_platform_data,
 194        },
 195};
 196
 197static struct plat_sci_port scif6_platform_data = {
 198        .mapbase        = 0xe6cc0000,
 199        .flags          = UPF_BOOT_AUTOCONF,
 200        .scscr          = SCSCR_RE | SCSCR_TE,
 201        .scbrr_algo_id  = SCBRR_ALGO_4,
 202        .type           = PORT_SCIFA,
 203        .irqs           = { gic_spi(156), gic_spi(156),
 204                            gic_spi(156), gic_spi(156) },
 205};
 206
 207static struct platform_device scif6_device = {
 208        .name           = "sh-sci",
 209        .id             = 6,
 210        .dev            = {
 211                .platform_data  = &scif6_platform_data,
 212        },
 213};
 214
 215static struct plat_sci_port scif7_platform_data = {
 216        .mapbase        = 0xe6cd0000,
 217        .flags          = UPF_BOOT_AUTOCONF,
 218        .scscr          = SCSCR_RE | SCSCR_TE,
 219        .scbrr_algo_id  = SCBRR_ALGO_4,
 220        .type           = PORT_SCIFA,
 221        .irqs           = { gic_spi(143), gic_spi(143),
 222                            gic_spi(143), gic_spi(143) },
 223};
 224
 225static struct platform_device scif7_device = {
 226        .name           = "sh-sci",
 227        .id             = 7,
 228        .dev            = {
 229                .platform_data  = &scif7_platform_data,
 230        },
 231};
 232
 233static struct plat_sci_port scif8_platform_data = {
 234        .mapbase        = 0xe6c30000,
 235        .flags          = UPF_BOOT_AUTOCONF,
 236        .scscr          = SCSCR_RE | SCSCR_TE,
 237        .scbrr_algo_id  = SCBRR_ALGO_4,
 238        .type           = PORT_SCIFB,
 239        .irqs           = { gic_spi(80), gic_spi(80),
 240                            gic_spi(80), gic_spi(80) },
 241};
 242
 243static struct platform_device scif8_device = {
 244        .name           = "sh-sci",
 245        .id             = 8,
 246        .dev            = {
 247                .platform_data  = &scif8_platform_data,
 248        },
 249};
 250
 251static struct sh_timer_config cmt10_platform_data = {
 252        .name = "CMT10",
 253        .channel_offset = 0x10,
 254        .timer_bit = 0,
 255        .clockevent_rating = 80,
 256        .clocksource_rating = 125,
 257};
 258
 259static struct resource cmt10_resources[] = {
 260        [0] = {
 261                .name   = "CMT10",
 262                .start  = 0xe6138010,
 263                .end    = 0xe613801b,
 264                .flags  = IORESOURCE_MEM,
 265        },
 266        [1] = {
 267                .start  = gic_spi(65),
 268                .flags  = IORESOURCE_IRQ,
 269        },
 270};
 271
 272static struct platform_device cmt10_device = {
 273        .name           = "sh_cmt",
 274        .id             = 10,
 275        .dev = {
 276                .platform_data  = &cmt10_platform_data,
 277        },
 278        .resource       = cmt10_resources,
 279        .num_resources  = ARRAY_SIZE(cmt10_resources),
 280};
 281
 282/* TMU */
 283static struct sh_timer_config tmu00_platform_data = {
 284        .name = "TMU00",
 285        .channel_offset = 0x4,
 286        .timer_bit = 0,
 287        .clockevent_rating = 200,
 288};
 289
 290static struct resource tmu00_resources[] = {
 291        [0] = {
 292                .name   = "TMU00",
 293                .start  = 0xfff60008,
 294                .end    = 0xfff60013,
 295                .flags  = IORESOURCE_MEM,
 296        },
 297        [1] = {
 298                .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
 299                .flags  = IORESOURCE_IRQ,
 300        },
 301};
 302
 303static struct platform_device tmu00_device = {
 304        .name           = "sh_tmu",
 305        .id             = 0,
 306        .dev = {
 307                .platform_data  = &tmu00_platform_data,
 308        },
 309        .resource       = tmu00_resources,
 310        .num_resources  = ARRAY_SIZE(tmu00_resources),
 311};
 312
 313static struct sh_timer_config tmu01_platform_data = {
 314        .name = "TMU01",
 315        .channel_offset = 0x10,
 316        .timer_bit = 1,
 317        .clocksource_rating = 200,
 318};
 319
 320static struct resource tmu01_resources[] = {
 321        [0] = {
 322                .name   = "TMU01",
 323                .start  = 0xfff60014,
 324                .end    = 0xfff6001f,
 325                .flags  = IORESOURCE_MEM,
 326        },
 327        [1] = {
 328                .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
 329                .flags  = IORESOURCE_IRQ,
 330        },
 331};
 332
 333static struct platform_device tmu01_device = {
 334        .name           = "sh_tmu",
 335        .id             = 1,
 336        .dev = {
 337                .platform_data  = &tmu01_platform_data,
 338        },
 339        .resource       = tmu01_resources,
 340        .num_resources  = ARRAY_SIZE(tmu01_resources),
 341};
 342
 343static struct resource i2c0_resources[] = {
 344        [0] = {
 345                .name   = "IIC0",
 346                .start  = 0xe6820000,
 347                .end    = 0xe6820425 - 1,
 348                .flags  = IORESOURCE_MEM,
 349        },
 350        [1] = {
 351                .start  = gic_spi(167),
 352                .end    = gic_spi(170),
 353                .flags  = IORESOURCE_IRQ,
 354        },
 355};
 356
 357static struct resource i2c1_resources[] = {
 358        [0] = {
 359                .name   = "IIC1",
 360                .start  = 0xe6822000,
 361                .end    = 0xe6822425 - 1,
 362                .flags  = IORESOURCE_MEM,
 363        },
 364        [1] = {
 365                .start  = gic_spi(51),
 366                .end    = gic_spi(54),
 367                .flags  = IORESOURCE_IRQ,
 368        },
 369};
 370
 371static struct resource i2c2_resources[] = {
 372        [0] = {
 373                .name   = "IIC2",
 374                .start  = 0xe6824000,
 375                .end    = 0xe6824425 - 1,
 376                .flags  = IORESOURCE_MEM,
 377        },
 378        [1] = {
 379                .start  = gic_spi(171),
 380                .end    = gic_spi(174),
 381                .flags  = IORESOURCE_IRQ,
 382        },
 383};
 384
 385static struct resource i2c3_resources[] = {
 386        [0] = {
 387                .name   = "IIC3",
 388                .start  = 0xe6826000,
 389                .end    = 0xe6826425 - 1,
 390                .flags  = IORESOURCE_MEM,
 391        },
 392        [1] = {
 393                .start  = gic_spi(183),
 394                .end    = gic_spi(186),
 395                .flags  = IORESOURCE_IRQ,
 396        },
 397};
 398
 399static struct resource i2c4_resources[] = {
 400        [0] = {
 401                .name   = "IIC4",
 402                .start  = 0xe6828000,
 403                .end    = 0xe6828425 - 1,
 404                .flags  = IORESOURCE_MEM,
 405        },
 406        [1] = {
 407                .start  = gic_spi(187),
 408                .end    = gic_spi(190),
 409                .flags  = IORESOURCE_IRQ,
 410        },
 411};
 412
 413static struct platform_device i2c0_device = {
 414        .name           = "i2c-sh_mobile",
 415        .id             = 0,
 416        .resource       = i2c0_resources,
 417        .num_resources  = ARRAY_SIZE(i2c0_resources),
 418};
 419
 420static struct platform_device i2c1_device = {
 421        .name           = "i2c-sh_mobile",
 422        .id             = 1,
 423        .resource       = i2c1_resources,
 424        .num_resources  = ARRAY_SIZE(i2c1_resources),
 425};
 426
 427static struct platform_device i2c2_device = {
 428        .name           = "i2c-sh_mobile",
 429        .id             = 2,
 430        .resource       = i2c2_resources,
 431        .num_resources  = ARRAY_SIZE(i2c2_resources),
 432};
 433
 434static struct platform_device i2c3_device = {
 435        .name           = "i2c-sh_mobile",
 436        .id             = 3,
 437        .resource       = i2c3_resources,
 438        .num_resources  = ARRAY_SIZE(i2c3_resources),
 439};
 440
 441static struct platform_device i2c4_device = {
 442        .name           = "i2c-sh_mobile",
 443        .id             = 4,
 444        .resource       = i2c4_resources,
 445        .num_resources  = ARRAY_SIZE(i2c4_resources),
 446};
 447
 448static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
 449        {
 450                .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 451                .addr           = 0xe6c40020,
 452                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 453                .mid_rid        = 0x21,
 454        }, {
 455                .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 456                .addr           = 0xe6c40024,
 457                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 458                .mid_rid        = 0x22,
 459        }, {
 460                .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 461                .addr           = 0xe6c50020,
 462                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 463                .mid_rid        = 0x25,
 464        }, {
 465                .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 466                .addr           = 0xe6c50024,
 467                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 468                .mid_rid        = 0x26,
 469        }, {
 470                .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 471                .addr           = 0xe6c60020,
 472                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 473                .mid_rid        = 0x29,
 474        }, {
 475                .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 476                .addr           = 0xe6c60024,
 477                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 478                .mid_rid        = 0x2a,
 479        }, {
 480                .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 481                .addr           = 0xe6c70020,
 482                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 483                .mid_rid        = 0x2d,
 484        }, {
 485                .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 486                .addr           = 0xe6c70024,
 487                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 488                .mid_rid        = 0x2e,
 489        }, {
 490                .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 491                .addr           = 0xe6c80020,
 492                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 493                .mid_rid        = 0x39,
 494        }, {
 495                .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 496                .addr           = 0xe6c80024,
 497                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 498                .mid_rid        = 0x3a,
 499        }, {
 500                .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 501                .addr           = 0xe6cb0020,
 502                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 503                .mid_rid        = 0x35,
 504        }, {
 505                .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 506                .addr           = 0xe6cb0024,
 507                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 508                .mid_rid        = 0x36,
 509        }, {
 510                .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 511                .addr           = 0xe6cc0020,
 512                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 513                .mid_rid        = 0x1d,
 514        }, {
 515                .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 516                .addr           = 0xe6cc0024,
 517                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 518                .mid_rid        = 0x1e,
 519        }, {
 520                .slave_id       = SHDMA_SLAVE_SCIF7_TX,
 521                .addr           = 0xe6cd0020,
 522                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 523                .mid_rid        = 0x19,
 524        }, {
 525                .slave_id       = SHDMA_SLAVE_SCIF7_RX,
 526                .addr           = 0xe6cd0024,
 527                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 528                .mid_rid        = 0x1a,
 529        }, {
 530                .slave_id       = SHDMA_SLAVE_SCIF8_TX,
 531                .addr           = 0xe6c30040,
 532                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 533                .mid_rid        = 0x3d,
 534        }, {
 535                .slave_id       = SHDMA_SLAVE_SCIF8_RX,
 536                .addr           = 0xe6c30060,
 537                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 538                .mid_rid        = 0x3e,
 539        }, {
 540                .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 541                .addr           = 0xee100030,
 542                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 543                .mid_rid        = 0xc1,
 544        }, {
 545                .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 546                .addr           = 0xee100030,
 547                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 548                .mid_rid        = 0xc2,
 549        }, {
 550                .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 551                .addr           = 0xee120030,
 552                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 553                .mid_rid        = 0xc9,
 554        }, {
 555                .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 556                .addr           = 0xee120030,
 557                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 558                .mid_rid        = 0xca,
 559        }, {
 560                .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 561                .addr           = 0xee140030,
 562                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 563                .mid_rid        = 0xcd,
 564        }, {
 565                .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 566                .addr           = 0xee140030,
 567                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 568                .mid_rid        = 0xce,
 569        }, {
 570                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 571                .addr           = 0xe6bd0034,
 572                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 573                .mid_rid        = 0xd1,
 574        }, {
 575                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 576                .addr           = 0xe6bd0034,
 577                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 578                .mid_rid        = 0xd2,
 579        },
 580};
 581
 582#define DMAE_CHANNEL(_offset)                                   \
 583        {                                                       \
 584                .offset         = _offset - 0x20,               \
 585                .dmars          = _offset - 0x20 + 0x40,        \
 586        }
 587
 588static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
 589        DMAE_CHANNEL(0x8000),
 590        DMAE_CHANNEL(0x8080),
 591        DMAE_CHANNEL(0x8100),
 592        DMAE_CHANNEL(0x8180),
 593        DMAE_CHANNEL(0x8200),
 594        DMAE_CHANNEL(0x8280),
 595        DMAE_CHANNEL(0x8300),
 596        DMAE_CHANNEL(0x8380),
 597        DMAE_CHANNEL(0x8400),
 598        DMAE_CHANNEL(0x8480),
 599        DMAE_CHANNEL(0x8500),
 600        DMAE_CHANNEL(0x8580),
 601        DMAE_CHANNEL(0x8600),
 602        DMAE_CHANNEL(0x8680),
 603        DMAE_CHANNEL(0x8700),
 604        DMAE_CHANNEL(0x8780),
 605        DMAE_CHANNEL(0x8800),
 606        DMAE_CHANNEL(0x8880),
 607        DMAE_CHANNEL(0x8900),
 608        DMAE_CHANNEL(0x8980),
 609};
 610
 611static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 612        .slave          = sh73a0_dmae_slaves,
 613        .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
 614        .channel        = sh73a0_dmae_channels,
 615        .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
 616        .ts_low_shift   = TS_LOW_SHIFT,
 617        .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 618        .ts_high_shift  = TS_HI_SHIFT,
 619        .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 620        .ts_shift       = dma_ts_shift,
 621        .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 622        .dmaor_init     = DMAOR_DME,
 623};
 624
 625static struct resource sh73a0_dmae_resources[] = {
 626        {
 627                /* Registers including DMAOR and channels including DMARSx */
 628                .start  = 0xfe000020,
 629                .end    = 0xfe008a00 - 1,
 630                .flags  = IORESOURCE_MEM,
 631        },
 632        {
 633                .name   = "error_irq",
 634                .start  = gic_spi(129),
 635                .end    = gic_spi(129),
 636                .flags  = IORESOURCE_IRQ,
 637        },
 638        {
 639                /* IRQ for channels 0-19 */
 640                .start  = gic_spi(109),
 641                .end    = gic_spi(128),
 642                .flags  = IORESOURCE_IRQ,
 643        },
 644};
 645
 646static struct platform_device dma0_device = {
 647        .name           = "sh-dma-engine",
 648        .id             = 0,
 649        .resource       = sh73a0_dmae_resources,
 650        .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
 651        .dev            = {
 652                .platform_data  = &sh73a0_dmae_platform_data,
 653        },
 654};
 655
 656/* MPDMAC */
 657static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
 658        {
 659                .slave_id       = SHDMA_SLAVE_FSI2A_RX,
 660                .addr           = 0xec230020,
 661                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 662                .mid_rid        = 0xd6, /* CHECK ME */
 663        }, {
 664                .slave_id       = SHDMA_SLAVE_FSI2A_TX,
 665                .addr           = 0xec230024,
 666                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 667                .mid_rid        = 0xd5, /* CHECK ME */
 668        }, {
 669                .slave_id       = SHDMA_SLAVE_FSI2C_RX,
 670                .addr           = 0xec230060,
 671                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 672                .mid_rid        = 0xda, /* CHECK ME */
 673        }, {
 674                .slave_id       = SHDMA_SLAVE_FSI2C_TX,
 675                .addr           = 0xec230064,
 676                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 677                .mid_rid        = 0xd9, /* CHECK ME */
 678        }, {
 679                .slave_id       = SHDMA_SLAVE_FSI2B_RX,
 680                .addr           = 0xec240020,
 681                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 682                .mid_rid        = 0x8e, /* CHECK ME */
 683        }, {
 684                .slave_id       = SHDMA_SLAVE_FSI2B_TX,
 685                .addr           = 0xec240024,
 686                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 687                .mid_rid        = 0x8d, /* CHECK ME */
 688        }, {
 689                .slave_id       = SHDMA_SLAVE_FSI2D_RX,
 690                .addr           =  0xec240060,
 691                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 692                .mid_rid        = 0x9a, /* CHECK ME */
 693        },
 694};
 695
 696#define MPDMA_CHANNEL(a, b, c)                  \
 697{                                               \
 698        .offset         = a,                    \
 699        .dmars          = b,                    \
 700        .dmars_bit      = c,                    \
 701        .chclr_offset   = (0x220 - 0x20) + a    \
 702}
 703
 704static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
 705        MPDMA_CHANNEL(0x00, 0, 0),
 706        MPDMA_CHANNEL(0x10, 0, 8),
 707        MPDMA_CHANNEL(0x20, 4, 0),
 708        MPDMA_CHANNEL(0x30, 4, 8),
 709        MPDMA_CHANNEL(0x50, 8, 0),
 710        MPDMA_CHANNEL(0x70, 8, 8),
 711};
 712
 713static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 714        .slave          = sh73a0_mpdma_slaves,
 715        .slave_num      = ARRAY_SIZE(sh73a0_mpdma_slaves),
 716        .channel        = sh73a0_mpdma_channels,
 717        .channel_num    = ARRAY_SIZE(sh73a0_mpdma_channels),
 718        .ts_low_shift   = TS_LOW_SHIFT,
 719        .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 720        .ts_high_shift  = TS_HI_SHIFT,
 721        .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 722        .ts_shift       = dma_ts_shift,
 723        .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 724        .dmaor_init     = DMAOR_DME,
 725        .chclr_present  = 1,
 726};
 727
 728/* Resource order important! */
 729static struct resource sh73a0_mpdma_resources[] = {
 730        {
 731                /* Channel registers and DMAOR */
 732                .start  = 0xec618020,
 733                .end    = 0xec61828f,
 734                .flags  = IORESOURCE_MEM,
 735        },
 736        {
 737                /* DMARSx */
 738                .start  = 0xec619000,
 739                .end    = 0xec61900b,
 740                .flags  = IORESOURCE_MEM,
 741        },
 742        {
 743                .name   = "error_irq",
 744                .start  = gic_spi(181),
 745                .end    = gic_spi(181),
 746                .flags  = IORESOURCE_IRQ,
 747        },
 748        {
 749                /* IRQ for channels 0-5 */
 750                .start  = gic_spi(175),
 751                .end    = gic_spi(180),
 752                .flags  = IORESOURCE_IRQ,
 753        },
 754};
 755
 756static struct platform_device mpdma0_device = {
 757        .name           = "sh-dma-engine",
 758        .id             = 1,
 759        .resource       = sh73a0_mpdma_resources,
 760        .num_resources  = ARRAY_SIZE(sh73a0_mpdma_resources),
 761        .dev            = {
 762                .platform_data  = &sh73a0_mpdma_platform_data,
 763        },
 764};
 765
 766static struct resource pmu_resources[] = {
 767        [0] = {
 768                .start  = gic_spi(55),
 769                .end    = gic_spi(55),
 770                .flags  = IORESOURCE_IRQ,
 771        },
 772        [1] = {
 773                .start  = gic_spi(56),
 774                .end    = gic_spi(56),
 775                .flags  = IORESOURCE_IRQ,
 776        },
 777};
 778
 779static struct platform_device pmu_device = {
 780        .name           = "arm-pmu",
 781        .id             = -1,
 782        .num_resources  = ARRAY_SIZE(pmu_resources),
 783        .resource       = pmu_resources,
 784};
 785
 786/* an IPMMU module for ICB */
 787static struct resource ipmmu_resources[] = {
 788        [0] = {
 789                .name   = "IPMMU",
 790                .start  = 0xfe951000,
 791                .end    = 0xfe9510ff,
 792                .flags  = IORESOURCE_MEM,
 793        },
 794};
 795
 796static const char * const ipmmu_dev_names[] = {
 797        "sh_mobile_lcdc_fb.0",
 798};
 799
 800static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 801        .dev_names = ipmmu_dev_names,
 802        .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 803};
 804
 805static struct platform_device ipmmu_device = {
 806        .name           = "ipmmu",
 807        .id             = -1,
 808        .dev = {
 809                .platform_data = &ipmmu_platform_data,
 810        },
 811        .resource       = ipmmu_resources,
 812        .num_resources  = ARRAY_SIZE(ipmmu_resources),
 813};
 814
 815static struct renesas_intc_irqpin_config irqpin0_platform_data = {
 816        .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
 817};
 818
 819static struct resource irqpin0_resources[] = {
 820        DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
 821        DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
 822        DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
 823        DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
 824        DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
 825        DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
 826        DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
 827        DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
 828        DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
 829        DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
 830        DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
 831        DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
 832        DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
 833};
 834
 835static struct platform_device irqpin0_device = {
 836        .name           = "renesas_intc_irqpin",
 837        .id             = 0,
 838        .resource       = irqpin0_resources,
 839        .num_resources  = ARRAY_SIZE(irqpin0_resources),
 840        .dev            = {
 841                .platform_data  = &irqpin0_platform_data,
 842        },
 843};
 844
 845static struct renesas_intc_irqpin_config irqpin1_platform_data = {
 846        .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
 847        .control_parent = true, /* Disable spurious IRQ10 */
 848};
 849
 850static struct resource irqpin1_resources[] = {
 851        DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
 852        DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
 853        DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
 854        DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
 855        DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
 856        DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
 857        DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
 858        DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
 859        DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
 860        DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
 861        DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
 862        DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
 863        DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
 864};
 865
 866static struct platform_device irqpin1_device = {
 867        .name           = "renesas_intc_irqpin",
 868        .id             = 1,
 869        .resource       = irqpin1_resources,
 870        .num_resources  = ARRAY_SIZE(irqpin1_resources),
 871        .dev            = {
 872                .platform_data  = &irqpin1_platform_data,
 873        },
 874};
 875
 876static struct renesas_intc_irqpin_config irqpin2_platform_data = {
 877        .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
 878};
 879
 880static struct resource irqpin2_resources[] = {
 881        DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
 882        DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
 883        DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
 884        DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
 885        DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
 886        DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
 887        DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
 888        DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
 889        DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
 890        DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
 891        DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
 892        DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
 893        DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
 894};
 895
 896static struct platform_device irqpin2_device = {
 897        .name           = "renesas_intc_irqpin",
 898        .id             = 2,
 899        .resource       = irqpin2_resources,
 900        .num_resources  = ARRAY_SIZE(irqpin2_resources),
 901        .dev            = {
 902                .platform_data  = &irqpin2_platform_data,
 903        },
 904};
 905
 906static struct renesas_intc_irqpin_config irqpin3_platform_data = {
 907        .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
 908};
 909
 910static struct resource irqpin3_resources[] = {
 911        DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
 912        DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
 913        DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
 914        DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
 915        DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
 916        DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
 917        DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
 918        DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
 919        DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
 920        DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
 921        DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
 922        DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
 923        DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
 924};
 925
 926static struct platform_device irqpin3_device = {
 927        .name           = "renesas_intc_irqpin",
 928        .id             = 3,
 929        .resource       = irqpin3_resources,
 930        .num_resources  = ARRAY_SIZE(irqpin3_resources),
 931        .dev            = {
 932                .platform_data  = &irqpin3_platform_data,
 933        },
 934};
 935
 936static struct platform_device *sh73a0_devices_dt[] __initdata = {
 937        &scif0_device,
 938        &scif1_device,
 939        &scif2_device,
 940        &scif3_device,
 941        &scif4_device,
 942        &scif5_device,
 943        &scif6_device,
 944        &scif7_device,
 945        &scif8_device,
 946        &cmt10_device,
 947};
 948
 949static struct platform_device *sh73a0_early_devices[] __initdata = {
 950        &tmu00_device,
 951        &tmu01_device,
 952        &ipmmu_device,
 953};
 954
 955static struct platform_device *sh73a0_late_devices[] __initdata = {
 956        &i2c0_device,
 957        &i2c1_device,
 958        &i2c2_device,
 959        &i2c3_device,
 960        &i2c4_device,
 961        &dma0_device,
 962        &mpdma0_device,
 963        &pmu_device,
 964        &irqpin0_device,
 965        &irqpin1_device,
 966        &irqpin2_device,
 967        &irqpin3_device,
 968};
 969
 970#define SRCR2          IOMEM(0xe61580b0)
 971
 972void __init sh73a0_add_standard_devices(void)
 973{
 974        /* Clear software reset bit on SY-DMAC module */
 975        __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 976
 977        platform_add_devices(sh73a0_devices_dt,
 978                            ARRAY_SIZE(sh73a0_devices_dt));
 979        platform_add_devices(sh73a0_early_devices,
 980                            ARRAY_SIZE(sh73a0_early_devices));
 981        platform_add_devices(sh73a0_late_devices,
 982                            ARRAY_SIZE(sh73a0_late_devices));
 983}
 984
 985/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 986void __init __weak sh73a0_register_twd(void) { }
 987
 988void __init sh73a0_earlytimer_init(void)
 989{
 990        sh73a0_clock_init();
 991        shmobile_earlytimer_init();
 992        sh73a0_register_twd();
 993}
 994
 995void __init sh73a0_add_early_devices(void)
 996{
 997        early_platform_add_devices(sh73a0_devices_dt,
 998                                   ARRAY_SIZE(sh73a0_devices_dt));
 999        early_platform_add_devices(sh73a0_early_devices,
1000                                   ARRAY_SIZE(sh73a0_early_devices));

1001
1002        /* setup early console here as well */
1003        shmobile_setup_console();
1004}
1005
1006#ifdef CONFIG_USE_OF
1007
1008void __init sh73a0_init_delay(void)
1009{
1010        shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
1011}
1012
1013static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
1014        {},
1015};
1016
1017void __init sh73a0_add_standard_devices_dt(void)
1018{
1019        /* clocks are setup late during boot in the case of DT */
1020        sh73a0_clock_init();
1021
1022        platform_add_devices(sh73a0_devices_dt,
1023                             ARRAY_SIZE(sh73a0_devices_dt));
1024        of_platform_populate(NULL, of_default_bus_match_table,
1025                             sh73a0_auxdata_lookup, NULL);
1026}
1027
1028static const char *sh73a0_boards_compat_dt[] __initdata = {
1029        "renesas,sh73a0",
1030        NULL,
1031};
1032
1033DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
1034        .smp            = smp_ops(sh73a0_smp_ops),
1035        .map_io         = sh73a0_map_io,
1036        .init_early     = sh73a0_init_delay,
1037        .nr_irqs        = NR_IRQS_LEGACY,
1038        .init_irq       = irqchip_init,
1039        .init_machine   = sh73a0_add_standard_devices_dt,
1040        .dt_compat      = sh73a0_boards_compat_dt,
1041MACHINE_END
1042#endif /* CONFIG_USE_OF */
1043