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28#include <linux/linkage.h>
29#include <linux/init.h>
30#include <asm/assembler.h>
31#include <asm/asm-offsets.h>
32#include <asm/hwcap.h>
33#include <asm/pgtable-hwdef.h>
34#include <asm/pgtable.h>
35#include <asm/ptrace.h>
36
37#include "proc-macros.S"
38
39
40
41
42
43
44
45
46
47#define MAX_AREA_SIZE 32768
48
49
50
51
52#define CACHE_DLINESIZE 32
53
54
55
56
57#define CACHE_DSEGMENTS 16
58
59
60
61
62#define CACHE_DENTRIES 64
63
64
65
66
67
68
69#define CACHE_DLIMIT 32768
70
71 .text
72
73
74
75ENTRY(cpu_arm1020e_proc_init)
76 mov pc, lr
77
78
79
80
81ENTRY(cpu_arm1020e_proc_fin)
82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0,
84 bic r0, r0,
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 mov pc, lr
87
88
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91
92
93
94
95
96
97 .align 5
98 .pushsection .idmap.text, "ax"
99ENTRY(cpu_arm1020e_reset)
100 mov ip,
101 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
102 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103#ifdef CONFIG_MMU
104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105#endif
106 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
107 bic ip, ip,
108 bic ip, ip,
109 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
110 mov pc, r0
111ENDPROC(cpu_arm1020e_reset)
112 .popsection
113
114
115
116
117 .align 5
118ENTRY(cpu_arm1020e_do_idle)
119 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
120 mov pc, lr
121
122
123
124 .align 5
125
126
127
128
129
130
131ENTRY(arm1020e_flush_icache_all)
132#ifndef CONFIG_CPU_ICACHE_DISABLE
133 mov r0,
134 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
135#endif
136 mov pc, lr
137ENDPROC(arm1020e_flush_icache_all)
138
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142
143
144
145ENTRY(arm1020e_flush_user_cache_all)
146
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150
151
152ENTRY(arm1020e_flush_kern_cache_all)
153 mov r2,
154 mov ip,
155__flush_whole_cache:
156#ifndef CONFIG_CPU_DCACHE_DISABLE
157 mcr p15, 0, ip, c7, c10, 4 @ drain WB
158 mov r1,
1591: orr r3, r1,
1602: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
161 subs r3, r3,
162 bcs 2b @ entries 63 to 0
163 subs r1, r1,
164 bcs 1b @ segments 15 to 0
165#endif
166 tst r2,
167#ifndef CONFIG_CPU_ICACHE_DISABLE
168 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
169#endif
170 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
171 mov pc, lr
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181
182
183ENTRY(arm1020e_flush_user_cache_range)
184 mov ip,
185 sub r3, r1, r0 @ calculate total size
186 cmp r3,
187 bhs __flush_whole_cache
188
189#ifndef CONFIG_CPU_DCACHE_DISABLE
1901: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
191 add r0, r0,
192 cmp r0, r1
193 blo 1b
194#endif
195 tst r2,
196#ifndef CONFIG_CPU_ICACHE_DISABLE
197 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
198#endif
199 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
200 mov pc, lr
201
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211
212ENTRY(arm1020e_coherent_kern_range)
213
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224ENTRY(arm1020e_coherent_user_range)
225 mov ip,
226 bic r0, r0,
2271:
228#ifndef CONFIG_CPU_DCACHE_DISABLE
229 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
230#endif
231#ifndef CONFIG_CPU_ICACHE_DISABLE
232 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
233#endif
234 add r0, r0,
235 cmp r0, r1
236 blo 1b
237 mcr p15, 0, ip, c7, c10, 4 @ drain WB
238 mov r0,
239 mov pc, lr
240
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248
249
250ENTRY(arm1020e_flush_kern_dcache_area)
251 mov ip,
252#ifndef CONFIG_CPU_DCACHE_DISABLE
253 add r1, r0, r1
2541: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
255 add r0, r0,
256 cmp r0, r1
257 blo 1b
258#endif
259 mcr p15, 0, ip, c7, c10, 4 @ drain WB
260 mov pc, lr
261
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274
275arm1020e_dma_inv_range:
276 mov ip,
277#ifndef CONFIG_CPU_DCACHE_DISABLE
278 tst r0,
279 bic r0, r0,
280 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
281 tst r1,
282 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
2831: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
284 add r0, r0,
285 cmp r0, r1
286 blo 1b
287#endif
288 mcr p15, 0, ip, c7, c10, 4 @ drain WB
289 mov pc, lr
290
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299
300
301arm1020e_dma_clean_range:
302 mov ip,
303#ifndef CONFIG_CPU_DCACHE_DISABLE
304 bic r0, r0,
3051: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
306 add r0, r0,
307 cmp r0, r1
308 blo 1b
309#endif
310 mcr p15, 0, ip, c7, c10, 4 @ drain WB
311 mov pc, lr
312
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320
321ENTRY(arm1020e_dma_flush_range)
322 mov ip,
323#ifndef CONFIG_CPU_DCACHE_DISABLE
324 bic r0, r0,
3251: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
326 add r0, r0,
327 cmp r0, r1
328 blo 1b
329#endif
330 mcr p15, 0, ip, c7, c10, 4 @ drain WB
331 mov pc, lr
332
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337
338
339ENTRY(arm1020e_dma_map_area)
340 add r1, r1, r0
341 cmp r2,
342 beq arm1020e_dma_clean_range
343 bcs arm1020e_dma_inv_range
344 b arm1020e_dma_flush_range
345ENDPROC(arm1020e_dma_map_area)
346
347
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350
351
352
353ENTRY(arm1020e_dma_unmap_area)
354 mov pc, lr
355ENDPROC(arm1020e_dma_unmap_area)
356
357 .globl arm1020e_flush_kern_cache_louis
358 .equ arm1020e_flush_kern_cache_louis, arm1020e_flush_kern_cache_all
359
360 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
361 define_cache_functions arm1020e
362
363 .align 5
364ENTRY(cpu_arm1020e_dcache_clean_area)
365#ifndef CONFIG_CPU_DCACHE_DISABLE
366 mov ip,
3671: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
368 add r0, r0,
369 subs r1, r1,
370 bhi 1b
371#endif
372 mov pc, lr
373
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381
382
383 .align 5
384ENTRY(cpu_arm1020e_switch_mm)
385#ifdef CONFIG_MMU
386#ifndef CONFIG_CPU_DCACHE_DISABLE
387 mcr p15, 0, r3, c7, c10, 4
388 mov r1,
3891: mov r3,
3902: mov ip, r3, LSL
391 orr ip, ip, r1, LSL
392 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
393 mov ip,
394 subs r3, r3,
395 cmp r3,
396 bge 2b @ entries 3F to 0
397 subs r1, r1,
398 cmp r1,
399 bge 1b @ segments 15 to 0
400
401#endif
402 mov r1,
403#ifndef CONFIG_CPU_ICACHE_DISABLE
404 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
405#endif
406 mcr p15, 0, r1, c7, c10, 4 @ drain WB
407 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
408 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
409#endif
410 mov pc, lr
411
412
413
414
415
416
417 .align 5
418ENTRY(cpu_arm1020e_set_pte_ext)
419#ifdef CONFIG_MMU
420 armv3_set_pte_ext
421 mov r0, r0
422#ifndef CONFIG_CPU_DCACHE_DISABLE
423 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
424#endif
425#endif
426 mov pc, lr
427
428 __CPUINIT
429
430 .type __arm1020e_setup,
431__arm1020e_setup:
432 mov r0,
433 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
434 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
435#ifdef CONFIG_MMU
436 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
437#endif
438 adr r5, arm1020e_crval
439 ldmia r5, {r5, r6}
440 mrc p15, 0, r0, c1, c0 @ get control register v4
441 bic r0, r0, r5
442 orr r0, r0, r6
443#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
444 orr r0, r0,
445#endif
446 mov pc, lr
447 .size __arm1020e_setup, . - __arm1020e_setup
448
449
450
451
452
453
454 .type arm1020e_crval,
455arm1020e_crval:
456 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
457
458 __INITDATA
459 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
460 define_processor_functions arm1020e, dabort=v4t_early_abort, pabort=legacy_pabort
461
462 .section ".rodata"
463
464 string cpu_arch_name, "armv5te"
465 string cpu_elf_name, "v5"
466 string cpu_arm1020e_name, "ARM1020E"
467
468 .align
469
470 .section ".proc.info.init",
471
472 .type __arm1020e_proc_info,
473__arm1020e_proc_info:
474 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
475 .long 0xff0ffff0
476 .long PMD_TYPE_SECT | \
477 PMD_BIT4 | \
478 PMD_SECT_AP_WRITE | \
479 PMD_SECT_AP_READ
480 .long PMD_TYPE_SECT | \
481 PMD_BIT4 | \
482 PMD_SECT_AP_WRITE | \
483 PMD_SECT_AP_READ
484 b __arm1020e_setup
485 .long cpu_arch_name
486 .long cpu_elf_name
487 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
488 .long cpu_arm1020e_name
489 .long arm1020e_processor_functions
490 .long v4wbi_tlb_fns
491 .long v4wb_user_fns
492 .long arm1020e_cache_fns
493 .size __arm1020e_proc_info, . - __arm1020e_proc_info
494