LXR linux/arch/blackfin/include/asm/bfin

   1/*
   2 * bfin_serial.h - Blackfin UART/Serial definitions
   3 *
   4 * Copyright 2006-2010 Analog Devices Inc.
   5 *
   6 * Licensed under the GPL-2 or later.
   7 */
   8
   9#ifndef __BFIN_ASM_SERIAL_H__
  10#define __BFIN_ASM_SERIAL_H__
  11
  12#include <linux/serial_core.h>
  13#include <linux/spinlock.h>
  14#include <mach/anomaly.h>
  15#include <mach/bfin_serial.h>
  16
  17#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
  18    defined(CONFIG_BFIN_UART1_CTSRTS) || \
  19    defined(CONFIG_BFIN_UART2_CTSRTS) || \
  20    defined(CONFIG_BFIN_UART3_CTSRTS)
  21# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
  22#  define CONFIG_SERIAL_BFIN_HARD_CTSRTS
  23# else
  24#  define CONFIG_SERIAL_BFIN_CTSRTS
  25# endif
  26#endif
  27
  28struct circ_buf;
  29struct timer_list;
  30struct work_struct;
  31
  32struct bfin_serial_port {
  33        struct uart_port port;
  34        unsigned int old_status;
  35        int tx_irq;
  36        int rx_irq;
  37        int status_irq;
  38#ifndef BFIN_UART_BF54X_STYLE
  39        unsigned int lsr;
  40#endif
  41#ifdef CONFIG_SERIAL_BFIN_DMA
  42        int tx_done;
  43        int tx_count;
  44        struct circ_buf rx_dma_buf;
  45        struct timer_list rx_dma_timer;
  46        int rx_dma_nrows;
  47        spinlock_t rx_lock;
  48        unsigned int tx_dma_channel;
  49        unsigned int rx_dma_channel;
  50        struct work_struct tx_dma_workqueue;
  51#elif ANOMALY_05000363
  52        unsigned int anomaly_threshold;
  53#endif
  54#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
  55        defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
  56        int cts_pin;
  57        int rts_pin;
  58#endif
  59};
  60
  61#ifdef BFIN_UART_BF60X_STYLE
  62
  63/* UART_CTL Masks */
  64#define UCEN                     0x1  /* Enable UARTx Clocks */
  65#define LOOP_ENA                 0x2  /* Loopback Mode Enable */
  66#define UMOD_MDB                 0x10  /* Enable MDB Mode */
  67#define UMOD_IRDA                0x20  /* Enable IrDA Mode */
  68#define UMOD_MASK                0x30  /* Uart Mode Mask */
  69#define WLS(x)                   (((x-5) & 0x03) << 8)  /* Word Length Select */
  70#define WLS_MASK                 0x300  /* Word length Select Mask */
  71#define WLS_OFFSET               8      /* Word length Select Offset */
  72#define STB                      0x1000  /* Stop Bits */
  73#define STBH                     0x2000  /* Half Stop Bits */
  74#define PEN                      0x4000  /* Parity Enable */
  75#define EPS                      0x8000  /* Even Parity Select */
  76#define STP                      0x10000  /* Stick Parity */
  77#define FPE                      0x20000  /* Force Parity Error On Transmit */
  78#define FFE                      0x40000  /* Force Framing Error On Transmit */
  79#define SB                       0x80000  /* Set Break */
  80#define LCR_MASK                 (SB | STP | EPS | PEN | STB | WLS_MASK)
  81#define FCPOL                    0x400000  /* Flow Control Pin Polarity */
  82#define RPOLC                    0x800000  /* IrDA RX Polarity Change */
  83#define TPOLC                    0x1000000  /* IrDA TX Polarity Change */
  84#define MRTS                     0x2000000  /* Manual Request To Send */
  85#define XOFF                     0x4000000  /* Transmitter Off */
  86#define ARTS                     0x8000000  /* Automatic Request To Send */
  87#define ACTS                     0x10000000  /* Automatic Clear To Send */
  88#define RFIT                     0x20000000  /* Receive FIFO IRQ Threshold */
  89#define RFRT                     0x40000000  /* Receive FIFO RTS Threshold */
  90
  91/* UART_STAT Masks */
  92#define DR                       0x01  /* Data Ready */
  93#define OE                       0x02  /* Overrun Error */
  94#define PE                       0x04  /* Parity Error */
  95#define FE                       0x08  /* Framing Error */
  96#define BI                       0x10  /* Break Interrupt */
  97#define THRE                     0x20  /* THR Empty */
  98#define TEMT                     0x80  /* TSR and UART_THR Empty */
  99#define TFI                      0x100  /* Transmission Finished Indicator */
 100
 101#define ASTKY                    0x200  /* Address Sticky */
 102#define ADDR                     0x400  /* Address bit status */
 103#define RO                       0x800  /* Reception Ongoing */
 104#define SCTS                     0x1000  /* Sticky CTS */
 105#define CTS                      0x10000  /* Clear To Send */
 106#define RFCS                     0x20000  /* Receive FIFO Count Status */
 107
 108/* UART_CLOCK Masks */
 109#define EDBO                     0x80000000 /* Enable Devide by One */
 110
 111#else /* BFIN_UART_BF60X_STYLE */
 112
 113/* UART_LCR Masks */
 114#define WLS(x)                   (((x)-5) & 0x03)  /* Word Length Select */
 115#define WLS_MASK                 0x03  /* Word length Select Mask */
 116#define WLS_OFFSET               0     /* Word length Select Offset */
 117#define STB                      0x04  /* Stop Bits */
 118#define PEN                      0x08  /* Parity Enable */
 119#define EPS                      0x10  /* Even Parity Select */
 120#define STP                      0x20  /* Stick Parity */
 121#define SB                       0x40  /* Set Break */
 122#define DLAB                     0x80  /* Divisor Latch Access */
 123#define LCR_MASK                 (SB | STP | EPS | PEN | STB | WLS_MASK)
 124
 125/* UART_LSR Masks */
 126#define DR                       0x01  /* Data Ready */
 127#define OE                       0x02  /* Overrun Error */
 128#define PE                       0x04  /* Parity Error */
 129#define FE                       0x08  /* Framing Error */
 130#define BI                       0x10  /* Break Interrupt */
 131#define THRE                     0x20  /* THR Empty */
 132#define TEMT                     0x40  /* TSR and UART_THR Empty */
 133#define TFI                      0x80  /* Transmission Finished Indicator */
 134
 135/* UART_MCR Masks */
 136#define XOFF                     0x01  /* Transmitter Off */
 137#define MRTS                     0x02  /* Manual Request To Send */
 138#define RFIT                     0x04  /* Receive FIFO IRQ Threshold */
 139#define RFRT                     0x08  /* Receive FIFO RTS Threshold */
 140#define LOOP_ENA                 0x10  /* Loopback Mode Enable */
 141#define FCPOL                    0x20  /* Flow Control Pin Polarity */
 142#define ARTS                     0x40  /* Automatic Request To Send */
 143#define ACTS                     0x80  /* Automatic Clear To Send */
 144
 145/* UART_MSR Masks */
 146#define SCTS                     0x01  /* Sticky CTS */
 147#define CTS                      0x10  /* Clear To Send */
 148#define RFCS                     0x20  /* Receive FIFO Count Status */
 149
 150/* UART_GCTL Masks */
 151#define UCEN                     0x01  /* Enable UARTx Clocks */
 152#define UMOD_IRDA                0x02  /* Enable IrDA Mode */
 153#define UMOD_MASK                0x02  /* Uart Mode Mask */
 154#define TPOLC                    0x04  /* IrDA TX Polarity Change */
 155#define RPOLC                    0x08  /* IrDA RX Polarity Change */
 156#define FPE                      0x10  /* Force Parity Error On Transmit */
 157#define FFE                      0x20  /* Force Framing Error On Transmit */
 158
 159#endif /* BFIN_UART_BF60X_STYLE */
 160
 161/* UART_IER Masks */
 162#define ERBFI                    0x01  /* Enable Receive Buffer Full Interrupt */
 163#define ETBEI                    0x02  /* Enable Transmit Buffer Empty Interrupt */
 164#define ELSI                     0x04  /* Enable RX Status Interrupt */
 165#define EDSSI                    0x08  /* Enable Modem Status Interrupt */
 166#define EDTPTI                   0x10  /* Enable DMA Transmit PIRQ Interrupt */
 167#define ETFI                     0x20  /* Enable Transmission Finished Interrupt */
 168#define ERFCI                    0x40  /* Enable Receive FIFO Count Interrupt */
 169
 170#if defined(BFIN_UART_BF60X_STYLE)
 171# define OFFSET_REDIV            0x00  /* Version ID Register             */
 172# define OFFSET_CTL              0x04  /* Control Register                */
 173# define OFFSET_STAT             0x08  /* Status Register                 */
 174# define OFFSET_SCR              0x0C  /* SCR Scratch Register            */
 175# define OFFSET_CLK              0x10  /* Clock Rate Register             */
 176# define OFFSET_IER              0x14  /* Interrupt Enable Register       */
 177# define OFFSET_IER_SET          0x18  /* Set Interrupt Enable Register   */
 178# define OFFSET_IER_CLEAR        0x1C  /* Clear Interrupt Enable Register */
 179# define OFFSET_RBR              0x20  /* Receive Buffer register         */
 180# define OFFSET_THR              0x24  /* Transmit Holding register       */
 181#elif defined(BFIN_UART_BF54X_STYLE)
 182# define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)        */
 183# define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)       */
 184# define OFFSET_GCTL             0x08  /* Global Control Register         */
 185# define OFFSET_LCR              0x0C  /* Line Control Register           */
 186# define OFFSET_MCR              0x10  /* Modem Control Register          */
 187# define OFFSET_LSR              0x14  /* Line Status Register            */
 188# define OFFSET_MSR              0x18  /* Modem Status Register           */
 189# define OFFSET_SCR              0x1C  /* SCR Scratch Register            */
 190# define OFFSET_IER_SET          0x20  /* Set Interrupt Enable Register   */
 191# define OFFSET_IER_CLEAR        0x24  /* Clear Interrupt Enable Register */
 192# define OFFSET_THR              0x28  /* Transmit Holding register       */
 193# define OFFSET_RBR              0x2C  /* Receive Buffer register         */
 194#else /* BF533 style */
 195# define OFFSET_THR              0x00  /* Transmit Holding register         */
 196# define OFFSET_RBR              0x00  /* Receive Buffer register           */
 197# define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)          */
 198# define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)         */
 199# define OFFSET_IER              0x04  /* Interrupt Enable Register         */
 200# define OFFSET_IIR              0x08  /* Interrupt Identification Register */
 201# define OFFSET_LCR              0x0C  /* Line Control Register             */
 202# define OFFSET_MCR              0x10  /* Modem Control Register            */
 203# define OFFSET_LSR              0x14  /* Line Status Register              */
 204# define OFFSET_MSR              0x18  /* Modem Status Register             */
 205# define OFFSET_SCR              0x1C  /* SCR Scratch Register              */
 206# define OFFSET_GCTL             0x24  /* Global Control Register           */
 207/* code should not need IIR, so force build error if they use it */
 208# undef OFFSET_IIR
 209#endif
 210
 211/*
 212 * All Blackfin system MMRs are padded to 32bits even if the register
 213 * itself is only 16bits.  So use a helper macro to streamline this.
 214 */
 215#define __BFP(m) u16 m; u16 __pad_##m
 216struct bfin_uart_regs {
 217#if defined(BFIN_UART_BF60X_STYLE)
 218        u32 revid;
 219        u32 ctl;
 220        u32 stat;
 221        u32 scr;
 222        u32 clk;
 223        u32 ier;
 224        u32 ier_set;
 225        u32 ier_clear;
 226        u32 rbr;
 227        u32 thr;
 228        u32 taip;
 229        u32 tsr;
 230        u32 rsr;
 231        u32 txdiv;
 232        u32 rxdiv;
 233#elif defined(BFIN_UART_BF54X_STYLE)
 234        __BFP(dll);
 235        __BFP(dlh);
 236        __BFP(gctl);
 237        __BFP(lcr);
 238        __BFP(mcr);
 239        __BFP(lsr);
 240        __BFP(msr);
 241        __BFP(scr);
 242        __BFP(ier_set);
 243        __BFP(ier_clear);
 244        __BFP(thr);
 245        __BFP(rbr);
 246#else
 247        union {
 248                u16 dll;
 249                u16 thr;
 250                const u16 rbr;
 251        };
 252        const u16 __pad0;
 253        union {
 254                u16 dlh;
 255                u16 ier;
 256        };
 257        const u16 __pad1;
 258        const __BFP(iir);
 259        __BFP(lcr);
 260        __BFP(mcr);
 261        __BFP(lsr);
 262        __BFP(msr);
 263        __BFP(scr);
 264        const u32 __pad2;
 265        __BFP(gctl);
 266#endif
 267};
 268#undef __BFP
 269
 270#define port_membase(uart)     (((struct bfin_serial_port *)(uart))->port.membase)
 271
 272/*
 273#ifndef port_membase
 274# define port_membase(p) 0
 275#endif
 276*/
 277#ifdef BFIN_UART_BF60X_STYLE
 278
 279#define UART_GET_CHAR(p)      bfin_read32(port_membase(p) + OFFSET_RBR)
 280#define UART_GET_CLK(p)       bfin_read32(port_membase(p) + OFFSET_CLK)
 281#define UART_GET_CTL(p)       bfin_read32(port_membase(p) + OFFSET_CTL)
 282#define UART_GET_GCTL(p)      UART_GET_CTL(p)
 283#define UART_GET_LCR(p)       UART_GET_CTL(p)
 284#define UART_GET_MCR(p)       UART_GET_CTL(p)
 285#if ANOMALY_16000030
 286#define UART_GET_STAT(p) \
 287({ \
 288        u32 __ret; \
 289        unsigned long flags; \
 290        flags = hard_local_irq_save(); \
 291        __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \
 292        hard_local_irq_restore(flags); \
 293        __ret; \
 294})
 295#else
 296#define UART_GET_STAT(p)      bfin_read32(port_membase(p) + OFFSET_STAT)
 297#endif
 298#define UART_GET_MSR(p)       UART_GET_STAT(p)
 299
 300#define UART_PUT_CHAR(p, v)   bfin_write32(port_membase(p) + OFFSET_THR, v)
 301#define UART_PUT_CLK(p, v)    bfin_write32(port_membase(p) + OFFSET_CLK, v)
 302#define UART_PUT_CTL(p, v)    bfin_write32(port_membase(p) + OFFSET_CTL, v)
 303#define UART_PUT_GCTL(p, v)   UART_PUT_CTL(p, v)
 304#define UART_PUT_LCR(p, v)    UART_PUT_CTL(p, v)
 305#define UART_PUT_MCR(p, v)    UART_PUT_CTL(p, v)
 306#define UART_PUT_STAT(p, v)   bfin_write32(port_membase(p) + OFFSET_STAT, v)
 307
 308#define UART_CLEAR_IER(p, v)  bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v)
 309#define UART_GET_IER(p)       bfin_read32(port_membase(p) + OFFSET_IER)
 310#define UART_SET_IER(p, v)    bfin_write32(port_membase(p) + OFFSET_IER_SET, v)
 311
 312#define UART_CLEAR_DLAB(p)    /* MMRs not muxed on BF60x */
 313#define UART_SET_DLAB(p)      /* MMRs not muxed on BF60x */
 314
 315#define UART_CLEAR_LSR(p)     UART_PUT_STAT(p, -1)
 316#define UART_GET_LSR(p)       UART_GET_STAT(p)
 317#define UART_PUT_LSR(p, v)    UART_PUT_STAT(p, v)
 318
 319/* This handles hard CTS/RTS */
 320#define BFIN_UART_CTSRTS_HARD
 321#define UART_CLEAR_SCTS(p)      UART_PUT_STAT(p, SCTS)
 322#define UART_GET_CTS(x)         (UART_GET_MSR(x) & CTS)
 323#define UART_DISABLE_RTS(x)     UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
 324#define UART_ENABLE_RTS(x)      UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
 325#define UART_ENABLE_INTS(x, v)  UART_SET_IER(x, v)
 326#define UART_DISABLE_INTS(x)    UART_CLEAR_IER(x, 0xF)
 327
 328#else /* BFIN_UART_BF60X_STYLE */
 329
 330#define UART_GET_CHAR(p)      bfin_read16(port_membase(p) + OFFSET_RBR)
 331#define UART_GET_DLL(p)       bfin_read16(port_membase(p) + OFFSET_DLL)
 332#define UART_GET_DLH(p)       bfin_read16(port_membase(p) + OFFSET_DLH)
 333#define UART_GET_CLK(p)       ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
 334#define UART_GET_GCTL(p)      bfin_read16(port_membase(p) + OFFSET_GCTL)
 335#define UART_GET_LCR(p)       bfin_read16(port_membase(p) + OFFSET_LCR)
 336#define UART_GET_MCR(p)       bfin_read16(port_membase(p) + OFFSET_MCR)
 337#define UART_GET_MSR(p)       bfin_read16(port_membase(p) + OFFSET_MSR)
 338
 339#define UART_PUT_CHAR(p, v)   bfin_write16(port_membase(p) + OFFSET_THR, v)
 340#define UART_PUT_DLL(p, v)    bfin_write16(port_membase(p) + OFFSET_DLL, v)
 341#define UART_PUT_DLH(p, v)    bfin_write16(port_membase(p) + OFFSET_DLH, v)
 342#define UART_PUT_CLK(p, v) do \
 343{\
 344UART_PUT_DLL(p, v & 0xFF); \
 345UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
 346
 347#define UART_PUT_GCTL(p, v)   bfin_write16(port_membase(p) + OFFSET_GCTL, v)
 348#define UART_PUT_LCR(p, v)    bfin_write16(port_membase(p) + OFFSET_LCR, v)
 349#define UART_PUT_MCR(p, v)    bfin_write16(port_membase(p) + OFFSET_MCR, v)
 350
 351#ifdef BFIN_UART_BF54X_STYLE
 352
 353#define UART_CLEAR_IER(p, v)  bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
 354#define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER_SET)
 355#define UART_SET_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
 356
 357#define UART_CLEAR_DLAB(p)    /* MMRs not muxed on BF54x */
 358#define UART_SET_DLAB(p)      /* MMRs not muxed on BF54x */
 359
 360#define UART_CLEAR_LSR(p)     bfin_write16(port_membase(p) + OFFSET_LSR, -1)
 361#define UART_GET_LSR(p)       bfin_read16(port_membase(p) + OFFSET_LSR)
 362#define UART_PUT_LSR(p, v)    bfin_write16(port_membase(p) + OFFSET_LSR, v)
 363
 364/* This handles hard CTS/RTS */
 365#define BFIN_UART_CTSRTS_HARD
 366#define UART_CLEAR_SCTS(p)      bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
 367#define UART_GET_CTS(x)         (UART_GET_MSR(x) & CTS)
 368#define UART_DISABLE_RTS(x)     UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
 369#define UART_ENABLE_RTS(x)      UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
 370#define UART_ENABLE_INTS(x, v)  UART_SET_IER(x, v)
 371#define UART_DISABLE_INTS(x)    UART_CLEAR_IER(x, 0xF)
 372
 373#else /* BF533 style */
 374
 375#define UART_CLEAR_IER(p, v)  UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
 376#define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER)
 377#define UART_PUT_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER, v)
 378#define UART_SET_IER(p, v)    UART_PUT_IER(p, UART_GET_IER(p) | (v))
 379
 380#define UART_CLEAR_DLAB(p)    do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
 381#define UART_SET_DLAB(p)      do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
 382
 383#define get_lsr_cache(uart)    (((struct bfin_serial_port *)(uart))->lsr)
 384#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
 385
 386/*
 387#ifndef put_lsr_cache
 388# define put_lsr_cache(p, v)
 389#endif
 390#ifndef get_lsr_cache
 391# define get_lsr_cache(p) 0
 392#endif
 393*/
 394
 395/* The hardware clears the LSR bits upon read, so we need to cache
 396 * some of the more fun bits in software so they don't get lost
 397 * when checking the LSR in other code paths (TX).
 398 */
 399static inline void UART_CLEAR_LSR(void *p)
 400{
 401        put_lsr_cache(p, 0);
 402        bfin_write16(port_membase(p) + OFFSET_LSR, -1);
 403}
 404static inline unsigned int UART_GET_LSR(void *p)
 405{
 406        unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
 407        put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
 408        return lsr | get_lsr_cache(p);
 409}
 410static inline void UART_PUT_LSR(void *p, uint16_t val)
 411{
 412        put_lsr_cache(p, get_lsr_cache(p) & ~val);
 413}
 414
 415/* This handles soft CTS/RTS */
 416#define UART_GET_CTS(x)        gpio_get_value((x)->cts_pin)
 417#define UART_DISABLE_RTS(x)    gpio_set_value((x)->rts_pin, 1)
 418#define UART_ENABLE_RTS(x)     gpio_set_value((x)->rts_pin, 0)
 419#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
 420#define UART_DISABLE_INTS(x)   UART_PUT_IER(x, 0)
 421
 422#endif /* BFIN_UART_BF54X_STYLE */
 423
 424#endif /* BFIN_UART_BF60X_STYLE */
 425
 426#ifndef BFIN_UART_TX_FIFO_SIZE
 427# define BFIN_UART_TX_FIFO_SIZE 2
 428#endif
 429
 430#endif /* __BFIN_ASM_SERIAL_H__ */
 431