LXR linux/arch/cris/include/arch-v32/arch/irq.h

   1#ifndef _ASM_ARCH_IRQ_H
   2#define _ASM_ARCH_IRQ_H
   3
   4#include <hwregs/intr_vect.h>
   5
   6/* Number of non-cpu interrupts. */
   7#define NR_IRQS NBR_INTR_VECT /* Exceptions + IRQs */
   8#define FIRST_IRQ 0x31 /* Exception number for first IRQ */
   9#define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */
  10#if NR_REAL_IRQS > 32
  11#define MACH_IRQS 64
  12#else
  13#define MACH_IRQS 32
  14#endif
  15
  16#ifndef __ASSEMBLY__
  17/* Global IRQ vector. */
  18typedef void (*irqvectptr)(void);
  19
  20struct etrax_interrupt_vector {
  21        irqvectptr v[256];
  22};
  23
  24extern struct etrax_interrupt_vector *etrax_irv;        /* head.S */
  25
  26void crisv32_mask_irq(int irq);
  27void crisv32_unmask_irq(int irq);
  28
  29void set_exception_vector(int n, irqvectptr addr);
  30
  31/* Save registers so that they match pt_regs. */
  32#define SAVE_ALL \
  33        "subq 12,$sp\n\t"       \
  34        "move $erp,[$sp]\n\t"   \
  35        "subq 4,$sp\n\t"        \
  36        "move $srp,[$sp]\n\t"   \
  37        "subq 4,$sp\n\t"        \
  38        "move $ccs,[$sp]\n\t"   \
  39        "subq 4,$sp\n\t"        \
  40        "move $spc,[$sp]\n\t"   \
  41        "subq 4,$sp\n\t"        \
  42        "move $mof,[$sp]\n\t"   \
  43        "subq 4,$sp\n\t"        \
  44        "move $srs,[$sp]\n\t"   \
  45        "subq 4,$sp\n\t"        \
  46        "move.d $acr,[$sp]\n\t" \
  47        "subq 14*4,$sp\n\t"     \
  48        "movem $r13,[$sp]\n\t"  \
  49        "subq 4,$sp\n\t"        \
  50        "move.d $r10,[$sp]\n"
  51
  52#define STR2(x) #x
  53#define STR(x) STR2(x)
  54
  55#define IRQ_NAME2(nr) nr##_interrupt(void)
  56#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
  57
  58/*
  59 * The reason for setting the S-bit when debugging the kernel is that we want
  60 * hardware breakpoints to remain active while we are in an exception handler.
  61 * Note that we cannot simply copy S1, since we may come here from user-space,
  62 * or any context where the S-bit wasn't set.
  63 */
  64#ifdef CONFIG_ETRAX_KGDB
  65#define KGDB_FIXUP \
  66        "move $ccs, $r10\n\t"           \
  67        "or.d (1<<9), $r10\n\t"         \
  68        "move $r10, $ccs\n\t"
  69#else
  70#define KGDB_FIXUP ""
  71#endif
  72
  73/*
  74 * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock
  75 * and jump to ret_from_intr which is found in entry.S.
  76 *
  77 * The reason for blocking the IRQ is to allow an sti() before the handler,
  78 * which will acknowledge the interrupt, is run. The actual blocking is made
  79 * by crisv32_do_IRQ.
  80 */
  81#define BUILD_IRQ(nr)                   \
  82void IRQ_NAME(nr);                      \
  83__asm__ (                               \
  84        ".text\n\t"                     \
  85        "IRQ" #nr "_interrupt:\n\t"     \
  86        SAVE_ALL                        \
  87        KGDB_FIXUP                      \
  88        "move.d "#nr",$r10\n\t"         \
  89        "move.d $sp, $r12\n\t"          \
  90        "jsr crisv32_do_IRQ\n\t"        \
  91        "moveq 1, $r11\n\t"             \
  92        "jump ret_from_intr\n\t"        \
  93        "nop\n\t");
  94/*
  95 * This is subtle. The timer interrupt is crucial and it should not be disabled
  96 * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it
  97 * would have been BLOCK'ed, and then softirq's are run before we return here to
  98 * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run
  99 * and the watchdog will kill us.
 100 *
 101 * Furthermore, if a lot of other irq's occur before we return here, the
 102 * multiple_irq handler is run and it prioritizes the timer interrupt. However
 103 * if we had BLOCK'edit here, we would not get the multiple_irq at all.
 104 *
 105 * The non-blocking here is based on the knowledge that the timer interrupt is
 106 * registered as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not
 107 * be an sti() before the timer irq handler is run to acknowledge the interrupt.
 108 */
 109#define BUILD_TIMER_IRQ(nr, mask)       \
 110void IRQ_NAME(nr);                      \
 111__asm__ (                               \
 112        ".text\n\t"                     \
 113        "IRQ" #nr "_interrupt:\n\t"     \
 114        SAVE_ALL                        \
 115        KGDB_FIXUP                      \
 116        "move.d "#nr",$r10\n\t"         \
 117        "move.d $sp,$r12\n\t"           \
 118        "jsr crisv32_do_IRQ\n\t"        \
 119        "moveq 0,$r11\n\t"              \
 120        "jump ret_from_intr\n\t"        \
 121        "nop\n\t");
 122
 123#endif /* __ASSEMBLY__ */
 124#endif /* _ASM_ARCH_IRQ_H */
 125