1/****************************************************************************/ 2 3/* 4 * m53xxacr.h -- ColdFire version 3 core cache support 5 * 6 * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com> 7 */ 8 9/****************************************************************************/ 10#ifndef m53xxacr_h 11#define m53xxacr_h 12/****************************************************************************/ 13 14/* 15 * All varients of the ColdFire using version 3 cores have a similar 16 * cache setup. They have a unified instruction and data cache, with 17 * configurable write-through or copy-back operation. 18 */ 19 20/* 21 * Define the Cache Control register flags. 22 */ 23#define CACR_EC 0x80000000 /* Enable cache */ 24#define CACR_ESB 0x20000000 /* Enable store buffer */ 25#define CACR_DPI 0x10000000 /* Disable invalidation by CPUSHL */ 26#define CACR_HLCK 0x08000000 /* Half cache lock mode */ 27#define CACR_CINVA 0x01000000 /* Invalidate cache */ 28#define CACR_DNFB 0x00000400 /* Inhibited fill buffer */ 29#define CACR_DCM_WT 0x00000000 /* Cacheable write-through */ 30#define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */ 31#define CACR_DCM_PRE 0x00000200 /* Cache inhibited, precise */ 32#define CACR_DCM_IMPRE 0x00000300 /* Cache inhibited, imprecise */ 33#define CACR_WPROTECT 0x00000020 /* Write protect*/ 34#define CACR_EUSP 0x00000010 /* Eanble separate user a7 */ 35 36/* 37 * Define the Access Control register flags. 38 */ 39#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */ 40#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */ 41#define ACR_ENABLE 0x00008000 /* Enable this ACR */ 42#define ACR_USER 0x00000000 /* Allow only user accesses */ 43#define ACR_SUPER 0x00002000 /* Allow supervisor access only */ 44#define ACR_ANY 0x00004000 /* Allow any access type */ 45#define ACR_CM_WT 0x00000000 /* Cacheable, write-through */ 46#define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */ 47#define ACR_CM_PRE 0x00000040 /* Cache inhibited, precise */ 48#define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */ 49#define ACR_WPROTECT 0x00000004 /* Write protect region */ 50 51/* 52 * Define the cache type and arrangement (needed for pushes). 53 */ 54#if defined(CONFIG_M5307) 55#define CACHE_SIZE 0x2000 /* 8k of unified cache */ 56#define ICACHE_SIZE CACHE_SIZE 57#define DCACHE_SIZE CACHE_SIZE 58#elif defined(CONFIG_M53xx) 59#define CACHE_SIZE 0x4000 /* 16k of unified cache */ 60#define ICACHE_SIZE CACHE_SIZE 61#define DCACHE_SIZE CACHE_SIZE 62#endif 63 64#define CACHE_LINE_SIZE 16 /* 16 byte line size */ 65#define CACHE_WAYS 4 /* 4 ways - set associative */ 66 67/* 68 * Set the cache controller settings we will use. This default in the 69 * CACR is cache inhibited, we use the ACR register to set cacheing 70 * enabled on the regions we want (eg RAM). 71 */ 72#if defined(CONFIG_CACHE_COPYBACK) 73#define CACHE_TYPE ACR_CM_CB 74#define CACHE_PUSH 75#else 76#define CACHE_TYPE ACR_CM_WT 77#endif 78 79#ifdef CONFIG_COLDFIRE_SW_A7 80#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE) 81#else 82#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP) 83#endif 84 85/* 86 * Unified cache means we will never need to flush for coherency of 87 * instruction fetch. We will need to flush to maintain memory/DMA 88 * coherency though in all cases. And for copyback caches we will need 89 * to push cached data as well. 90 */ 91#define CACHE_INIT CACR_CINVA 92#define CACHE_INVALIDATE CACR_CINVA 93#define CACHE_INVALIDATED CACR_CINVA 94 95#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ 96 (0x000f0000) + \ 97 (ACR_ENABLE + ACR_ANY + CACHE_TYPE)) 98#define ACR1_MODE 0 99 100/****************************************************************************/ 101#endif /* m53xxsim_h */ 102