LXR linux/arch/m68k/include/asm/m54xxpci.h

   1/****************************************************************************/
   2
   3/*
   4 *      m54xxpci.h -- ColdFire 547x and 548x PCI bus support
   5 *
   6 *      (C) Copyright 2011,  Greg Ungerer <gerg@uclinux.org>
   7 *
   8 * This file is subject to the terms and conditions of the GNU General Public
   9 * License.  See the file COPYING in the main directory of this archive
  10 * for more details.
  11 */
  12
  13/****************************************************************************/
  14#ifndef M54XXPCI_H
  15#define M54XXPCI_H
  16/****************************************************************************/
  17
  18/*
  19 *      The core set of PCI support registers are mapped into the MBAR region.
  20 */
  21#define PCIIDR          (CONFIG_MBAR + 0xb00)   /* PCI device/vendor ID */
  22#define PCISCR          (CONFIG_MBAR + 0xb04)   /* PCI status/command */
  23#define PCICCRIR        (CONFIG_MBAR + 0xb08)   /* PCI class/revision */
  24#define PCICR1          (CONFIG_MBAR + 0xb0c)   /* PCI configuration 1 */
  25#define PCIBAR0         (CONFIG_MBAR + 0xb10)   /* PCI base address 0 */
  26#define PCIBAR1         (CONFIG_MBAR + 0xb14)   /* PCI base address 1 */
  27#define PCICCPR         (CONFIG_MBAR + 0xb28)   /* PCI cardbus CIS pointer */
  28#define PCISID          (CONFIG_MBAR + 0xb2c)   /* PCI subsystem IDs */
  29#define PCIERBAR        (CONFIG_MBAR + 0xb30)   /* PCI expansion ROM */
  30#define PCICPR          (CONFIG_MBAR + 0xb34)   /* PCI capabilities pointer */
  31#define PCICR2          (CONFIG_MBAR + 0xb3c)   /* PCI configuration 2 */
  32
  33#define PCIGSCR         (CONFIG_MBAR + 0xb60)   /* Global status/control */
  34#define PCITBATR0       (CONFIG_MBAR + 0xb64)   /* Target base translation 0 */
  35#define PCITBATR1       (CONFIG_MBAR + 0xb68)   /* Target base translation 1 */
  36#define PCITCR          (CONFIG_MBAR + 0xb6c)   /* Target control */
  37#define PCIIW0BTAR      (CONFIG_MBAR + 0xb70)   /* Initiator window 0 */
  38#define PCIIW1BTAR      (CONFIG_MBAR + 0xb74)   /* Initiator window 1 */
  39#define PCIIW2BTAR      (CONFIG_MBAR + 0xb78)   /* Initiator window 2 */
  40#define PCIIWCR         (CONFIG_MBAR + 0xb80)   /* Initiator window config */
  41#define PCIICR          (CONFIG_MBAR + 0xb84)   /* Initiator control */
  42#define PCIISR          (CONFIG_MBAR + 0xb88)   /* Initiator status */
  43#define PCICAR          (CONFIG_MBAR + 0xbf8)   /* Configuration address */
  44
  45#define PCITPSR         (CONFIG_MBAR + 0x8400)  /* TX packet size */
  46#define PCITSAR         (CONFIG_MBAR + 0x8404)  /* TX start address */
  47#define PCITTCR         (CONFIG_MBAR + 0x8408)  /* TX transaction control */
  48#define PCITER          (CONFIG_MBAR + 0x840c)  /* TX enables */
  49#define PCITNAR         (CONFIG_MBAR + 0x8410)  /* TX next address */
  50#define PCITLWR         (CONFIG_MBAR + 0x8414)  /* TX last word */
  51#define PCITDCR         (CONFIG_MBAR + 0x8418)  /* TX done counts */
  52#define PCITSR          (CONFIG_MBAR + 0x841c)  /* TX status */
  53#define PCITFDR         (CONFIG_MBAR + 0x8440)  /* TX FIFO data */
  54#define PCITFSR         (CONFIG_MBAR + 0x8444)  /* TX FIFO status */
  55#define PCITFCR         (CONFIG_MBAR + 0x8448)  /* TX FIFO control */
  56#define PCITFAR         (CONFIG_MBAR + 0x844c)  /* TX FIFO alarm */
  57#define PCITFRPR        (CONFIG_MBAR + 0x8450)  /* TX FIFO read pointer */
  58#define PCITFWPR        (CONFIG_MBAR + 0x8454)  /* TX FIFO write pointer */
  59
  60#define PCIRPSR         (CONFIG_MBAR + 0x8480)  /* RX packet size */
  61#define PCIRSAR         (CONFIG_MBAR + 0x8484)  /* RX start address */
  62#define PCIRTCR         (CONFIG_MBAR + 0x8488)  /* RX transaction control */
  63#define PCIRER          (CONFIG_MBAR + 0x848c)  /* RX enables */
  64#define PCIRNAR         (CONFIG_MBAR + 0x8490)  /* RX next address */
  65#define PCIRDCR         (CONFIG_MBAR + 0x8498)  /* RX done counts */
  66#define PCIRSR          (CONFIG_MBAR + 0x849c)  /* RX status */
  67#define PCIRFDR         (CONFIG_MBAR + 0x84c0)  /* RX FIFO data */
  68#define PCIRFSR         (CONFIG_MBAR + 0x84c4)  /* RX FIFO status */
  69#define PCIRFCR         (CONFIG_MBAR + 0x84c8)  /* RX FIFO control */
  70#define PCIRFAR         (CONFIG_MBAR + 0x84cc)  /* RX FIFO alarm */
  71#define PCIRFRPR        (CONFIG_MBAR + 0x84d0)  /* RX FIFO read pointer */
  72#define PCIRFWPR        (CONFIG_MBAR + 0x84d4)  /* RX FIFO write pointer */
  73
  74#define PACR            (CONFIG_MBAR + 0xc00)   /* PCI arbiter control */
  75#define PASR            (COFNIG_MBAR + 0xc04)   /* PCI arbiter status */
  76
  77/*
  78 *      Definitions for the Global status and control register.
  79 */
  80#define PCIGSCR_PE      0x20000000              /* Parity error detected */
  81#define PCIGSCR_SE      0x10000000              /* System error detected */
  82#define PCIGSCR_XCLKBIN 0x07000000              /* XLB2CLKIN mask */
  83#define PCIGSCR_PEE     0x00002000              /* Parity error intr enable */
  84#define PCIGSCR_SEE     0x00001000              /* System error intr enable */
  85#define PCIGSCR_RESET   0x00000001              /* Reset bit */
  86
  87/*
  88 *      Bit definitions for the PCICAR configuration address register.
  89 */
  90#define PCICAR_E        0x80000000              /* Enable config space */
  91#define PCICAR_BUSN     16                      /* Move bus bits */
  92#define PCICAR_DEVFNN   8                       /* Move devfn bits */
  93#define PCICAR_DWORDN   0                       /* Move dword bits */
  94
  95/*
  96 *      The initiator windows hold the memory and IO mapping information.
  97 *      This macro creates the register values from the desired addresses.
  98 */
  99#define WXBTAR(hostaddr, pciaddr, size) \
 100                        (((hostaddr) & 0xff000000) | \
 101                        ((((size) - 1) & 0xff000000) >> 8) | \
 102                        (((pciaddr) & 0xff000000) >> 16))
 103
 104#define PCIIWCR_W0_MEM  0x00000000              /* Window 0 is memory */
 105#define PCIIWCR_W0_IO   0x08000000              /* Window 0 is IO */
 106#define PCIIWCR_W0_MRD  0x00000000              /* Window 0 memory read */
 107#define PCIIWCR_W0_MRDL 0x02000000              /* Window 0 memory read line */
 108#define PCIIWCR_W0_MRDM 0x04000000              /* Window 0 memory read mult */
 109#define PCIIWCR_W0_E    0x01000000              /* Window 0 enable */
 110
 111#define PCIIWCR_W1_MEM  0x00000000              /* Window 0 is memory */
 112#define PCIIWCR_W1_IO   0x00080000              /* Window 0 is IO */
 113#define PCIIWCR_W1_MRD  0x00000000              /* Window 0 memory read */
 114#define PCIIWCR_W1_MRDL 0x00020000              /* Window 0 memory read line */
 115#define PCIIWCR_W1_MRDM 0x00040000              /* Window 0 memory read mult */
 116#define PCIIWCR_W1_E    0x00010000              /* Window 0 enable */
 117
 118/*
 119 *      Bit definitions for the PCIBATR registers.
 120 */
 121#define PCITBATR0_E     0x00000001              /* Enable window 0 */
 122#define PCITBATR1_E     0x00000001              /* Enable window 1 */
 123
 124/*
 125 *      PCI arbiter support definitions and macros.
 126 */
 127#define PACR_INTMPRI    0x00000001
 128#define PACR_EXTMPRI(x) (((x) & 0x1f) << 1)
 129#define PACR_INTMINTE   0x00010000
 130#define PACR_EXTMINTE(x) (((x) & 0x1f) << 17)
 131#define PACR_PKMD       0x40000000
 132#define PACR_DS         0x80000000
 133
 134#define PCICR1_CL(x)    ((x) & 0xf)             /* Cacheline size field */
 135#define PCICR1_LT(x)    (((x) & 0xff) << 8)     /* Latency timer field */
 136
 137/****************************************************************************/
 138#endif  /* M54XXPCI_H */
 139