LXR linux/arch/m68k/include/asm/m68360

   1/***********************************
   2 * $Id: m68360_regs.h,v 1.2 2002/10/26 15:03:55 gerg Exp $
   3 ***********************************
   4 *
   5 ***************************************
   6 * Definitions of the QUICC registers
   7 ***************************************
   8 */
   9
  10#ifndef __REGISTERS_H
  11#define __REGISTERS_H
  12
  13#define CLEAR_BIT(x, bit)  x =bit 
  14
  15/*****************************************************************
  16        Command Register
  17*****************************************************************/
  18
  19/* bit fields within command register */
  20#define SOFTWARE_RESET  0x8000
  21#define CMD_OPCODE      0x0f00
  22#define CMD_CHANNEL     0x00f0
  23#define CMD_FLAG        0x0001
  24
  25/* general command opcodes */
  26#define INIT_RXTX_PARAMS        0x0000
  27#define INIT_RX_PARAMS          0x0100
  28#define INIT_TX_PARAMS          0x0200
  29#define ENTER_HUNT_MODE         0x0300
  30#define STOP_TX                 0x0400
  31#define GR_STOP_TX              0x0500
  32#define RESTART_TX              0x0600
  33#define CLOSE_RX_BD             0x0700
  34#define SET_ENET_GROUP          0x0800
  35#define RESET_ENET_GROUP        0x0900
  36
  37/* quicc32 CP commands */
  38#define STOP_TX_32              0x0e00  /*add chan# bits 2-6 */
  39#define ENTER_HUNT_MODE_32      0x1e00
  40
  41/* quicc32 mask/event SCC register */
  42#define GOV     0x01
  43#define GUN     0x02
  44#define GINT    0x04
  45#define IQOV    0x08
  46
  47
  48/* Timer commands */
  49#define SET_TIMER               0x0800
  50
  51/* Multi channel Interrupt structure */
  52#define INTR_VALID      0x8000  /* Valid interrupt entry */
  53#define INTR_WRAP       0x4000  /* Wrap bit in the interrupt entry table */
  54#define INTR_CH_NU      0x07c0  /* Channel Num in interrupt table */
  55#define INTR_MASK_BITS  0x383f
  56
  57/*
  58 * General SCC mode register (GSMR)
  59 */
  60
  61#define MODE_HDLC               0x0
  62#define MODE_APPLE_TALK         0x2
  63#define MODE_SS7                0x3
  64#define MODE_UART               0x4
  65#define MODE_PROFIBUS           0x5
  66#define MODE_ASYNC_HDLC         0x6
  67#define MODE_V14                0x7
  68#define MODE_BISYNC             0x8
  69#define MODE_DDCMP              0x9
  70#define MODE_MULTI_CHANNEL      0xa
  71#define MODE_ETHERNET           0xc
  72
  73#define DIAG_NORMAL             0x0
  74#define DIAG_LOCAL_LPB          0x1
  75#define DIAG_AUTO_ECHO          0x2
  76#define DIAG_LBP_ECHO           0x3
  77
  78/* For RENC and TENC fields in GSMR */
  79#define ENC_NRZ                 0x0
  80#define ENC_NRZI                0x1
  81#define ENC_FM0                 0x2
  82#define ENC_MANCH               0x4
  83#define ENC_DIFF_MANC           0x6
  84
  85/* For TDCR and RDCR fields in GSMR */
  86#define CLOCK_RATE_1            0x0
  87#define CLOCK_RATE_8            0x1
  88#define CLOCK_RATE_16           0x2
  89#define CLOCK_RATE_32           0x3
  90
  91#define TPP_00                  0x0
  92#define TPP_10                  0x1
  93#define TPP_01                  0x2
  94#define TPP_11                  0x3
  95
  96#define TPL_NO                  0x0
  97#define TPL_8                   0x1
  98#define TPL_16                  0x2
  99#define TPL_32                  0x3
 100#define TPL_48                  0x4
 101#define TPL_64                  0x5
 102#define TPL_128                 0x6
 103
 104#define TSNC_INFINITE           0x0
 105#define TSNC_14_65              0x1
 106#define TSNC_4_15               0x2
 107#define TSNC_3_1                0x3
 108
 109#define EDGE_BOTH               0x0
 110#define EDGE_POS                0x1
 111#define EDGE_NEG                0x2
 112#define EDGE_NO                 0x3
 113
 114#define SYNL_NO                 0x0
 115#define SYNL_4                  0x1
 116#define SYNL_8                  0x2
 117#define SYNL_16                 0x3
 118
 119#define TCRC_CCITT16            0x0
 120#define TCRC_CRC16              0x1
 121#define TCRC_CCITT32            0x2
 122
 123
 124/*****************************************************************
 125        TODR (Transmit on demand) Register
 126*****************************************************************/
 127#define TODR_TOD        0x8000  /* Transmit on demand */
 128
 129
 130/*****************************************************************
 131        CICR register settings
 132*****************************************************************/
 133
 134/* note that relative irq priorities of the SCCs can be reordered
 135 * if desired - see p. 7-377 of the MC68360UM */
 136#define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
 137#define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
 138#define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
 139#define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
 140
 141#define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrupt */
 142#define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
 143#define CICR_VBA_MASK           ((uint)0x000000e0)      /* Vector Base Address */
 144#define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
 145
 146
 147/*****************************************************************
 148       Interrupt bits for CIPR and CIMR (MC68360UM p. 7-379)
 149*****************************************************************/
 150
 151#define INTR_PIO_PC0    0x80000000      /* parallel I/O C bit 0 */
 152#define INTR_SCC1       0x40000000      /* SCC port 1 */
 153#define INTR_SCC2       0x20000000      /* SCC port 2 */
 154#define INTR_SCC3       0x10000000      /* SCC port 3 */
 155#define INTR_SCC4       0x08000000      /* SCC port 4 */
 156#define INTR_PIO_PC1    0x04000000      /* parallel i/o C bit 1 */
 157#define INTR_TIMER1     0x02000000      /* timer 1 */
 158#define INTR_PIO_PC2    0x01000000      /* parallel i/o C bit 2 */
 159#define INTR_PIO_PC3    0x00800000      /* parallel i/o C bit 3 */
 160#define INTR_SDMA_BERR  0x00400000      /* SDMA channel bus error */
 161#define INTR_DMA1       0x00200000      /* idma 1 */
 162#define INTR_DMA2       0x00100000      /* idma 2 */
 163#define INTR_TIMER2     0x00040000      /* timer 2 */
 164#define INTR_CP_TIMER   0x00020000      /* CP timer */
 165#define INTR_PIP_STATUS 0x00010000      /* PIP status */
 166#define INTR_PIO_PC4    0x00008000      /* parallel i/o C bit 4 */
 167#define INTR_PIO_PC5    0x00004000      /* parallel i/o C bit 5 */
 168#define INTR_TIMER3     0x00001000      /* timer 3 */
 169#define INTR_PIO_PC6    0x00000800      /* parallel i/o C bit 6 */
 170#define INTR_PIO_PC7    0x00000400      /* parallel i/o C bit 7 */
 171#define INTR_PIO_PC8    0x00000200      /* parallel i/o C bit 8 */
 172#define INTR_TIMER4     0x00000080      /* timer 4 */
 173#define INTR_PIO_PC9    0x00000040      /* parallel i/o C bit 9 */
 174#define INTR_SCP        0x00000020      /* SCP */
 175#define INTR_SMC1       0x00000010      /* SMC 1 */
 176#define INTR_SMC2       0x00000008      /* SMC 2 */
 177#define INTR_PIO_PC10   0x00000004      /* parallel i/o C bit 10 */
 178#define INTR_PIO_PC11   0x00000002      /* parallel i/o C bit 11 */
 179#define INTR_ERR        0x00000001      /* error */
 180
 181
 182/*****************************************************************
 183        CPM Interrupt vector encodings (MC68360UM p. 7-376)
 184*****************************************************************/
 185
 186#define CPMVEC_NR               32
 187#define CPMVEC_PIO_PC0          0x1f
 188#define CPMVEC_SCC1             0x1e
 189#define CPMVEC_SCC2             0x1d
 190#define CPMVEC_SCC3             0x1c
 191#define CPMVEC_SCC4             0x1b
 192#define CPMVEC_PIO_PC1          0x1a
 193#define CPMVEC_TIMER1           0x19
 194#define CPMVEC_PIO_PC2          0x18
 195#define CPMVEC_PIO_PC3          0x17
 196#define CPMVEC_SDMA_CB_ERR      0x16
 197#define CPMVEC_IDMA1            0x15
 198#define CPMVEC_IDMA2            0x14
 199#define CPMVEC_RESERVED3        0x13
 200#define CPMVEC_TIMER2           0x12
 201#define CPMVEC_RISCTIMER        0x11
 202#define CPMVEC_RESERVED2        0x10
 203#define CPMVEC_PIO_PC4          0x0f
 204#define CPMVEC_PIO_PC5          0x0e
 205#define CPMVEC_TIMER3           0x0c
 206#define CPMVEC_PIO_PC6          0x0b
 207#define CPMVEC_PIO_PC7          0x0a
 208#define CPMVEC_PIO_PC8          0x09
 209#define CPMVEC_RESERVED1        0x08
 210#define CPMVEC_TIMER4           0x07
 211#define CPMVEC_PIO_PC9          0x06
 212#define CPMVEC_SPI              0x05
 213#define CPMVEC_SMC1             0x04
 214#define CPMVEC_SMC2             0x03
 215#define CPMVEC_PIO_PC10         0x02
 216#define CPMVEC_PIO_PC11         0x01
 217#define CPMVEC_ERROR            0x00
 218
 219/* #define CPMVEC_PIO_PC0               ((ushort)0x1f) */
 220/* #define CPMVEC_SCC1          ((ushort)0x1e) */
 221/* #define CPMVEC_SCC2          ((ushort)0x1d) */
 222/* #define CPMVEC_SCC3          ((ushort)0x1c) */
 223/* #define CPMVEC_SCC4          ((ushort)0x1b) */
 224/* #define CPMVEC_PIO_PC1               ((ushort)0x1a) */
 225/* #define CPMVEC_TIMER1                ((ushort)0x19) */
 226/* #define CPMVEC_PIO_PC2               ((ushort)0x18) */
 227/* #define CPMVEC_PIO_PC3               ((ushort)0x17) */
 228/* #define CPMVEC_SDMA_CB_ERR   ((ushort)0x16) */
 229/* #define CPMVEC_IDMA1         ((ushort)0x15) */
 230/* #define CPMVEC_IDMA2         ((ushort)0x14) */
 231/* #define CPMVEC_RESERVED3     ((ushort)0x13) */
 232/* #define CPMVEC_TIMER2                ((ushort)0x12) */
 233/* #define CPMVEC_RISCTIMER     ((ushort)0x11) */
 234/* #define CPMVEC_RESERVED2     ((ushort)0x10) */
 235/* #define CPMVEC_PIO_PC4               ((ushort)0x0f) */
 236/* #define CPMVEC_PIO_PC5               ((ushort)0x0e) */
 237/* #define CPMVEC_TIMER3                ((ushort)0x0c) */
 238/* #define CPMVEC_PIO_PC6               ((ushort)0x0b) */
 239/* #define CPMVEC_PIO_PC7               ((ushort)0x0a) */
 240/* #define CPMVEC_PIO_PC8               ((ushort)0x09) */
 241/* #define CPMVEC_RESERVED1     ((ushort)0x08) */
 242/* #define CPMVEC_TIMER4                ((ushort)0x07) */
 243/* #define CPMVEC_PIO_PC9               ((ushort)0x06) */
 244/* #define CPMVEC_SPI           ((ushort)0x05) */
 245/* #define CPMVEC_SMC1          ((ushort)0x04) */
 246/* #define CPMVEC_SMC2          ((ushort)0x03) */
 247/* #define CPMVEC_PIO_PC10              ((ushort)0x02) */
 248/* #define CPMVEC_PIO_PC11              ((ushort)0x01) */
 249/* #define CPMVEC_ERROR         ((ushort)0x00) */
 250
 251
 252/*****************************************************************
 253 *        PIO control registers
 254 *****************************************************************/
 255
 256/* Port A - See 360UM p. 7-358
 257 * 
 258 *  Note that most of these pins have alternate functions
 259 */
 260
 261
 262/* The macros are nice, but there are all sorts of references to 1-indexed
 263 * facilities on the 68360... */
 264/* #define PA_RXD(n)    ((ushort)(0x01<<(2*n))) */
 265/* #define PA_TXD(n)    ((ushort)(0x02<<(2*n))) */
 266
 267#define PA_RXD1         ((ushort)0x0001)
 268#define PA_TXD1         ((ushort)0x0002)
 269#define PA_RXD2         ((ushort)0x0004)
 270#define PA_TXD2         ((ushort)0x0008)
 271#define PA_RXD3         ((ushort)0x0010)
 272#define PA_TXD3         ((ushort)0x0020)
 273#define PA_RXD4         ((ushort)0x0040)
 274#define PA_TXD4         ((ushort)0x0080)
 275
 276#define PA_CLK1         ((ushort)0x0100)
 277#define PA_CLK2         ((ushort)0x0200)
 278#define PA_CLK3         ((ushort)0x0400)
 279#define PA_CLK4         ((ushort)0x0800)
 280#define PA_CLK5         ((ushort)0x1000)
 281#define PA_CLK6         ((ushort)0x2000)
 282#define PA_CLK7         ((ushort)0x4000)
 283#define PA_CLK8         ((ushort)0x8000)
 284
 285
 286/* Port B - See 360UM p. 7-362
 287 */
 288
 289
 290/* Port C - See 360UM p. 7-365
 291 */
 292
 293#define PC_RTS1         ((ushort)0x0001)
 294#define PC_RTS2         ((ushort)0x0002)
 295#define PC__RTS3        ((ushort)0x0004) /* !RTS3 */
 296#define PC__RTS4        ((ushort)0x0008) /* !RTS4 */
 297
 298#define PC_CTS1         ((ushort)0x0010)
 299#define PC_CD1          ((ushort)0x0020)
 300#define PC_CTS2         ((ushort)0x0040)
 301#define PC_CD2          ((ushort)0x0080)
 302#define PC_CTS3         ((ushort)0x0100)
 303#define PC_CD3          ((ushort)0x0200)
 304#define PC_CTS4         ((ushort)0x0400)
 305#define PC_CD4          ((ushort)0x0800)
 306
 307
 308
 309/*****************************************************************
 310        chip select option register
 311*****************************************************************/
 312#define DTACK           0xe000
 313#define ADR_MASK        0x1ffc
 314#define RDWR_MASK       0x0002
 315#define FC_MASK         0x0001
 316
 317/*****************************************************************
 318        tbase and rbase registers
 319*****************************************************************/
 320#define TBD_ADDR(quicc,pram) ((struct quicc_bd *) \
 321    (quicc->ch_or_u.u.udata_bd_ucode + pram->tbase))
 322#define RBD_ADDR(quicc,pram) ((struct quicc_bd *) \
 323    (quicc->ch_or_u.u.udata_bd_ucode + pram->rbase))
 324#define TBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \
 325    (quicc->ch_or_u.u.udata_bd_ucode + pram->tbptr))
 326#define RBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \
 327    (quicc->ch_or_u.u.udata_bd_ucode + pram->rbptr))
 328#define TBD_SET_CUR_ADDR(bd,quicc,pram) pram->tbptr = \
 329    ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))
 330#define RBD_SET_CUR_ADDR(bd,quicc,pram) pram->rbptr = \
 331    ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))
 332#define INCREASE_TBD(bd,quicc,pram) {  \
 333    if((bd)->status & T_W)             \
 334        (bd) = TBD_ADDR(quicc,pram);   \
 335    else                               \
 336        (bd)++;                        \
 337}
 338#define DECREASE_TBD(bd,quicc,pram) {  \
 339    if ((bd) == TBD_ADDR(quicc, pram)) \
 340        while (!((bd)->status & T_W))  \
 341            (bd)++;                    \
 342    else                               \
 343        (bd)--;                        \
 344}
 345#define INCREASE_RBD(bd,quicc,pram) {  \
 346    if((bd)->status & R_W)             \
 347        (bd) = RBD_ADDR(quicc,pram);   \
 348    else                               \
 349        (bd)++;                        \
 350}
 351#define DECREASE_RBD(bd,quicc,pram) {  \
 352    if ((bd) == RBD_ADDR(quicc, pram)) \
 353        while (!((bd)->status & T_W))  \
 354            (bd)++;                    \
 355    else                               \
 356        (bd)--;                        \
 357}
 358
 359/*****************************************************************
 360        Macros for Multi channel
 361*****************************************************************/
 362#define QMC_BASE(quicc,page) (struct global_multi_pram *)(&quicc->pram[page])
 363#define MCBASE(quicc,page) (unsigned long)(quicc->pram[page].m.mcbase)
 364#define CHANNEL_PRAM_BASE(quicc,channel) ((struct quicc32_pram *) \
 365                (&(quicc->ch_or_u.ch_pram_tbl[channel])))
 366#define TBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \
 367    (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbase)))
 368#define RBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \
 369    (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbase)))
 370#define TBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \
 371    (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbptr)))
 372#define RBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \
 373    (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbptr)))
 374#define TBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \
 375     CHANNEL_PRAM_BASE(quicc,channel)->tbptr = \
 376    ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))
 377#define RBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \
 378     CHANNEL_PRAM_BASE(quicc,channel)->rbptr = \
 379    ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))
 380
 381#define INCREASE_TBD_32(bd,quicc,page,channel) {  \
 382    if((bd)->status & T_W)                        \
 383        (bd) = TBD_32_ADDR(quicc,page,channel);   \
 384    else                                          \
 385        (bd)++;                                   \
 386}
 387#define DECREASE_TBD_32(bd,quicc,page,channel) {  \
 388    if ((bd) == TBD_32_ADDR(quicc, page,channel)) \
 389        while (!((bd)->status & T_W))             \
 390            (bd)++;                               \
 391    else                                          \
 392        (bd)--;                                   \
 393}
 394#define INCREASE_RBD_32(bd,quicc,page,channel) {  \
 395    if((bd)->status & R_W)                        \
 396        (bd) = RBD_32_ADDR(quicc,page,channel);   \
 397    else                                          \
 398        (bd)++;                                   \
 399}
 400#define DECREASE_RBD_32(bd,quicc,page,channel) {  \
 401    if ((bd) == RBD_32_ADDR(quicc, page,channel)) \
 402        while (!((bd)->status & T_W))             \
 403            (bd)++;                               \
 404    else                                          \
 405        (bd)--;                                   \
 406}
 407
 408#endif
 409