1/****************************************************************************/ 2 3/* 4 * mcfdma.h -- Coldfire internal DMA support defines. 5 * 6 * (C) Copyright 1999, Rob Scott (rscott@mtrob.ml.org) 7 */ 8 9/****************************************************************************/ 10#ifndef mcfdma_h 11#define mcfdma_h 12/****************************************************************************/ 13 14#if !defined(CONFIG_M5272) 15 16/* 17 * Define the DMA register set addresses. 18 * Note: these are longword registers, use unsigned long as data type 19 */ 20#define MCFDMA_SAR 0x00 /* DMA source address (r/w) */ 21#define MCFDMA_DAR 0x01 /* DMA destination adr (r/w) */ 22/* these are word registers, use unsigned short data type */ 23#define MCFDMA_DCR 0x04 /* DMA control reg (r/w) */ 24#define MCFDMA_BCR 0x06 /* DMA byte count reg (r/w) */ 25/* these are byte registers, use unsiged char data type */ 26#define MCFDMA_DSR 0x10 /* DMA status reg (r/w) */ 27#define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */ 28 29/* 30 * Bit definitions for the DMA Control Register (DCR). 31 */ 32#define MCFDMA_DCR_INT 0x8000 /* Enable completion irq */ 33#define MCFDMA_DCR_EEXT 0x4000 /* Enable external DMA req */ 34#define MCFDMA_DCR_CS 0x2000 /* Enable cycle steal */ 35#define MCFDMA_DCR_AA 0x1000 /* Enable auto alignment */ 36#define MCFDMA_DCR_BWC_MASK 0x0E00 /* Bandwidth ctl mask */ 37#define MCFDMA_DCR_BWC_512 0x0200 /* Bandwidth: 512 Bytes */ 38#define MCFDMA_DCR_BWC_1024 0x0400 /* Bandwidth: 1024 Bytes */ 39#define MCFDMA_DCR_BWC_2048 0x0600 /* Bandwidth: 2048 Bytes */ 40#define MCFDMA_DCR_BWC_4096 0x0800 /* Bandwidth: 4096 Bytes */ 41#define MCFDMA_DCR_BWC_8192 0x0a00 /* Bandwidth: 8192 Bytes */ 42#define MCFDMA_DCR_BWC_16384 0x0c00 /* Bandwidth: 16384 Bytes */ 43#define MCFDMA_DCR_BWC_32768 0x0e00 /* Bandwidth: 32768 Bytes */ 44#define MCFDMA_DCR_SAA 0x0100 /* Single Address Access */ 45#define MCFDMA_DCR_S_RW 0x0080 /* SAA read/write value */ 46#define MCFDMA_DCR_SINC 0x0040 /* Source addr inc enable */ 47#define MCFDMA_DCR_SSIZE_MASK 0x0030 /* Src xfer size */ 48#define MCFDMA_DCR_SSIZE_LONG 0x0000 /* Src xfer size, 00 = longw */ 49#define MCFDMA_DCR_SSIZE_BYTE 0x0010 /* Src xfer size, 01 = byte */ 50#define MCFDMA_DCR_SSIZE_WORD 0x0020 /* Src xfer size, 10 = word */ 51#define MCFDMA_DCR_SSIZE_LINE 0x0030 /* Src xfer size, 11 = line */ 52#define MCFDMA_DCR_DINC 0x0008 /* Dest addr inc enable */ 53#define MCFDMA_DCR_DSIZE_MASK 0x0006 /* Dest xfer size */ 54#define MCFDMA_DCR_DSIZE_LONG 0x0000 /* Dest xfer size, 00 = long */ 55#define MCFDMA_DCR_DSIZE_BYTE 0x0002 /* Dest xfer size, 01 = byte */ 56#define MCFDMA_DCR_DSIZE_WORD 0x0004 /* Dest xfer size, 10 = word */ 57#define MCFDMA_DCR_DSIZE_LINE 0x0006 /* Dest xfer size, 11 = line */ 58#define MCFDMA_DCR_START 0x0001 /* Start transfer */ 59 60/* 61 * Bit definitions for the DMA Status Register (DSR). 62 */ 63#define MCFDMA_DSR_CE 0x40 /* Config error */ 64#define MCFDMA_DSR_BES 0x20 /* Bus Error on source */ 65#define MCFDMA_DSR_BED 0x10 /* Bus Error on dest */ 66#define MCFDMA_DSR_REQ 0x04 /* Requests remaining */ 67#define MCFDMA_DSR_BSY 0x02 /* Busy */ 68#define MCFDMA_DSR_DONE 0x01 /* DMA transfer complete */ 69 70#else /* This is an MCF5272 */ 71 72#define MCFDMA_DMR 0x00 /* Mode Register (r/w) */ 73#define MCFDMA_DIR 0x03 /* Interrupt trigger register (r/w) */ 74#define MCFDMA_DSAR 0x03 /* Source Address register (r/w) */ 75#define MCFDMA_DDAR 0x04 /* Destination Address register (r/w) */ 76#define MCFDMA_DBCR 0x02 /* Byte Count Register (r/w) */ 77 78/* Bit definitions for the DMA Mode Register (DMR) */ 79#define MCFDMA_DMR_RESET 0x80000000L /* Reset bit */ 80#define MCFDMA_DMR_EN 0x40000000L /* DMA enable */ 81#define MCFDMA_DMR_RQM 0x000C0000L /* Request Mode Mask */ 82#define MCFDMA_DMR_RQM_DUAL 0x000C0000L /* Dual address mode, the only valid mode */ 83#define MCFDMA_DMR_DSTM 0x00002000L /* Destination addressing mask */ 84#define MCFDMA_DMR_DSTM_SA 0x00000000L /* Destination uses static addressing */ 85#define MCFDMA_DMR_DSTM_IA 0x00002000L /* Destination uses incremental addressing */ 86#define MCFDMA_DMR_DSTT_UD 0x00000400L /* Destination is user data */ 87#define MCFDMA_DMR_DSTT_UC 0x00000800L /* Destination is user code */ 88#define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */ 89#define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */ 90#define MCFDMA_DMR_DSTS_OFF 0x8 /* offset to the destination size bits */ 91#define MCFDMA_DMR_DSTS_LONG 0x00000000L /* Long destination size */ 92#define MCFDMA_DMR_DSTS_BYTE 0x00000100L /* Byte destination size */ 93#define MCFDMA_DMR_DSTS_WORD 0x00000200L /* Word destination size */ 94#define MCFDMA_DMR_DSTS_LINE 0x00000300L /* Line destination size */ 95#define MCFDMA_DMR_SRCM 0x00000020L /* Source addressing mask */ 96#define MCFDMA_DMR_SRCM_SA 0x00000000L /* Source uses static addressing */ 97#define MCFDMA_DMR_SRCM_IA 0x00000020L /* Source uses incremental addressing */ 98#define MCFDMA_DMR_SRCT_UD 0x00000004L /* Source is user data */ 99#define MCFDMA_DMR_SRCT_UC 0x00000008L /* Source is user code */ 100#define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */ 101#define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */ 102#define MCFDMA_DMR_SRCS_OFF 0x0 /* Offset to the source size bits */ 103#define MCFDMA_DMR_SRCS_LONG 0x00000000L /* Long source size */ 104#define MCFDMA_DMR_SRCS_BYTE 0x00000001L /* Byte source size */ 105#define MCFDMA_DMR_SRCS_WORD 0x00000002L /* Word source size */ 106#define MCFDMA_DMR_SRCS_LINE 0x00000003L /* Line source size */ 107 108/* Bit definitions for the DMA interrupt register (DIR) */ 109#define MCFDMA_DIR_INVEN 0x1000 /* Invalid Combination interrupt enable */ 110#define MCFDMA_DIR_ASCEN 0x0800 /* Address Sequence Complete (Completion) interrupt enable */ 111#define MCFDMA_DIR_TEEN 0x0200 /* Transfer Error interrupt enable */ 112#define MCFDMA_DIR_TCEN 0x0100 /* Transfer Complete (a bus transfer, that is) interrupt enable */ 113#define MCFDMA_DIR_INV 0x0010 /* Invalid Combination */ 114#define MCFDMA_DIR_ASC 0x0008 /* Address Sequence Complete (DMA Completion) */ 115#define MCFDMA_DIR_TE 0x0002 /* Transfer Error */ 116#define MCFDMA_DIR_TC 0x0001 /* Transfer Complete */ 117 118#endif /* !defined(CONFIG_M5272) */ 119 120/****************************************************************************/ 121#endif /* mcfdma_h */ 122