LXR linux/arch/mips/include/asm/bcache.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (c) 1997, 1999 by Ralf Baechle
   7 * Copyright (c) 1999 Silicon Graphics, Inc.
   8 */
   9#ifndef _ASM_BCACHE_H
  10#define _ASM_BCACHE_H
  11
  12
  13/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
  14   chipset implemented caches.  On machines with other CPUs the CPU does the
  15   cache thing itself. */
  16struct bcache_ops {
  17        void (*bc_enable)(void);
  18        void (*bc_disable)(void);
  19        void (*bc_wback_inv)(unsigned long page, unsigned long size);
  20        void (*bc_inv)(unsigned long page, unsigned long size);
  21};
  22
  23extern void indy_sc_init(void);
  24
  25#ifdef CONFIG_BOARD_SCACHE
  26
  27extern struct bcache_ops *bcops;
  28
  29static inline void bc_enable(void)
  30{
  31        bcops->bc_enable();
  32}
  33
  34static inline void bc_disable(void)
  35{
  36        bcops->bc_disable();
  37}
  38
  39static inline void bc_wback_inv(unsigned long page, unsigned long size)
  40{
  41        bcops->bc_wback_inv(page, size);
  42}
  43
  44static inline void bc_inv(unsigned long page, unsigned long size)
  45{
  46        bcops->bc_inv(page, size);
  47}
  48
  49#else /* !defined(CONFIG_BOARD_SCACHE) */
  50
  51/* Not R4000 / R4400 / R4600 / R5000.  */
  52
  53#define bc_enable() do { } while (0)
  54#define bc_disable() do { } while (0)
  55#define bc_wback_inv(page, size) do { } while (0)
  56#define bc_inv(page, size) do { } while (0)
  57
  58#endif /* !defined(CONFIG_BOARD_SCACHE) */
  59
  60#endif /* _ASM_BCACHE_H */
  61