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9#include <linux/bitmap.h>
10#include <linux/init.h>
11#include <linux/smp.h>
12#include <linux/irq.h>
13#include <linux/clocksource.h>
14
15#include <asm/io.h>
16#include <asm/gic.h>
17#include <asm/setup.h>
18#include <asm/traps.h>
19#include <asm/gcmpregs.h>
20#include <linux/hardirq.h>
21#include <asm-generic/bitops/find.h>
22
23unsigned int gic_frequency;
24unsigned int gic_present;
25unsigned long _gic_base;
26unsigned int gic_irq_base;
27unsigned int gic_irq_flags[GIC_NUM_INTRS];
28
29
30struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
31
32static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
33static struct gic_pending_regs pending_regs[NR_CPUS];
34static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
35
36#if defined(CONFIG_CSRC_GIC) || defined(CONFIG_CEVT_GIC)
37cycle_t gic_read_count(void)
38{
39 unsigned int hi, hi2, lo;
40
41 do {
42 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
43 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
44 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
45 } while (hi2 != hi);
46
47 return (((cycle_t) hi) << 32) + lo;
48}
49
50void gic_write_compare(cycle_t cnt)
51{
52 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
53 (int)(cnt >> 32));
54 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
55 (int)(cnt & 0xffffffff));
56}
57
58cycle_t gic_read_compare(void)
59{
60 unsigned int hi, lo;
61
62 GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), hi);
63 GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), lo);
64
65 return (((cycle_t) hi) << 32) + lo;
66}
67#endif
68
69unsigned int gic_get_timer_pending(void)
70{
71 unsigned int vpe_pending;
72
73 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
74 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
75 return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
76}
77
78void gic_bind_eic_interrupt(int irq, int set)
79{
80
81 irq -= GIC_PIN_TO_VEC_OFFSET;
82
83
84 GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
85}
86
87void gic_send_ipi(unsigned int intr)
88{
89 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
90}
91
92static void gic_eic_irq_dispatch(void)
93{
94 unsigned int cause = read_c0_cause();
95 int irq;
96
97 irq = (cause & ST0_IM) >> STATUSB_IP2;
98 if (irq == 0)
99 irq = -1;
100
101 if (irq >= 0)
102 do_IRQ(gic_irq_base + irq);
103 else
104 spurious_interrupt();
105}
106
107static void __init vpe_local_setup(unsigned int numvpes)
108{
109 unsigned long timer_intr = GIC_INT_TMR;
110 unsigned long perf_intr = GIC_INT_PERFCTR;
111 unsigned int vpe_ctl;
112 int i;
113
114 if (cpu_has_veic) {
115
116
117
118
119 timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
120
121
122
123
124 perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
125 }
126
127
128
129
130
131 for (i = 0; i < numvpes; i++) {
132 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
133
134
135 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
136 if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
137 GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
138 GIC_MAP_TO_PIN_MSK | timer_intr);
139 if (cpu_has_veic) {
140 set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
141 gic_eic_irq_dispatch);
142 gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
143 }
144
145 if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
146 GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
147 GIC_MAP_TO_PIN_MSK | perf_intr);
148 if (cpu_has_veic) {
149 set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
150 gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
151 }
152 }
153}
154
155unsigned int gic_compare_int(void)
156{
157 unsigned int pending;
158
159 GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_PEND), pending);
160 if (pending & GIC_VPE_PEND_CMP_MSK)
161 return 1;
162 else
163 return 0;
164}
165
166unsigned int gic_get_int(void)
167{
168 unsigned int i;
169 unsigned long *pending, *intrmask, *pcpu_mask;
170 unsigned long *pending_abs, *intrmask_abs;
171
172
173 pending = pending_regs[smp_processor_id()].pending;
174 intrmask = intrmask_regs[smp_processor_id()].intrmask;
175 pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
176
177 pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
178 GIC_SH_PEND_31_0_OFS);
179 intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
180 GIC_SH_MASK_31_0_OFS);
181
182 for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
183 GICREAD(*pending_abs, pending[i]);
184 GICREAD(*intrmask_abs, intrmask[i]);
185 pending_abs++;
186 intrmask_abs++;
187 }
188
189 bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
190 bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
191
192 return find_first_bit(pending, GIC_NUM_INTRS);
193}
194
195static void gic_mask_irq(struct irq_data *d)
196{
197 GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
198}
199
200static void gic_unmask_irq(struct irq_data *d)
201{
202 GIC_SET_INTR_MASK(d->irq - gic_irq_base);
203}
204
205#ifdef CONFIG_SMP
206static DEFINE_SPINLOCK(gic_lock);
207
208static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
209 bool force)
210{
211 unsigned int irq = (d->irq - gic_irq_base);
212 cpumask_t tmp = CPU_MASK_NONE;
213 unsigned long flags;
214 int i;
215
216 cpumask_and(&tmp, cpumask, cpu_online_mask);
217 if (cpus_empty(tmp))
218 return -1;
219
220
221 spin_lock_irqsave(&gic_lock, flags);
222 for (;;) {
223
224 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
225
226
227 for (i = 0; i < NR_CPUS; i++)
228 clear_bit(irq, pcpu_masks[i].pcpu_mask);
229 set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
230
231 }
232 cpumask_copy(d->affinity, cpumask);
233 spin_unlock_irqrestore(&gic_lock, flags);
234
235 return IRQ_SET_MASK_OK_NOCOPY;
236}
237#endif
238
239static struct irq_chip gic_irq_controller = {
240 .name = "MIPS GIC",
241 .irq_ack = gic_irq_ack,
242 .irq_mask = gic_mask_irq,
243 .irq_mask_ack = gic_mask_irq,
244 .irq_unmask = gic_unmask_irq,
245 .irq_eoi = gic_finish_irq,
246#ifdef CONFIG_SMP
247 .irq_set_affinity = gic_set_affinity,
248#endif
249};
250
251static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
252 unsigned int pin, unsigned int polarity, unsigned int trigtype,
253 unsigned int flags)
254{
255 struct gic_shared_intr_map *map_ptr;
256
257
258 if (pin & GIC_MAP_TO_NMI_MSK) {
259 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
260
261 for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
262 GICWRITE(GIC_REG_ADDR(SHARED,
263 GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
264 0xffffffff);
265 }
266 } else {
267 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
268 GIC_MAP_TO_PIN_MSK | pin);
269
270 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
271 if (cpu_has_veic) {
272 set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
273 gic_eic_irq_dispatch);
274 map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
275 if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
276 BUG();
277 map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
278 }
279 }
280
281
282 GIC_SET_POLARITY(intr, polarity);
283
284
285 GIC_SET_TRIGGER(intr, trigtype);
286
287
288 GIC_CLR_INTR_MASK(intr);
289
290 if (flags & GIC_FLAG_IPI)
291 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
292 if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
293 GIC_SET_INTR_MASK(intr);
294 if (trigtype == GIC_TRIG_EDGE)
295 gic_irq_flags[intr] |= GIC_TRIG_EDGE;
296}
297
298static void __init gic_basic_init(int numintrs, int numvpes,
299 struct gic_intr_map *intrmap, int mapsize)
300{
301 unsigned int i, cpu;
302 unsigned int pin_offset = 0;
303
304 board_bind_eic_interrupt = &gic_bind_eic_interrupt;
305
306
307 for (i = 0; i < numintrs; i++) {
308 GIC_SET_POLARITY(i, GIC_POL_POS);
309 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
310 GIC_CLR_INTR_MASK(i);
311 if (i < GIC_NUM_INTRS) {
312 gic_irq_flags[i] = 0;
313 gic_shared_intr_map[i].num_shared_intr = 0;
314 gic_shared_intr_map[i].local_intr_mask = 0;
315 }
316 }
317
318
319
320
321
322 if (cpu_has_veic)
323 pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
324
325
326 for (i = 0; i < mapsize; i++) {
327 cpu = intrmap[i].cpunum;
328 if (cpu == GIC_UNUSED)
329 continue;
330 if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
331 continue;
332 gic_setup_intr(i,
333 intrmap[i].cpunum,
334 intrmap[i].pin + pin_offset,
335 intrmap[i].polarity,
336 intrmap[i].trigtype,
337 intrmap[i].flags);
338 }
339
340 vpe_local_setup(numvpes);
341}
342
343void __init gic_init(unsigned long gic_base_addr,
344 unsigned long gic_addrspace_size,
345 struct gic_intr_map *intr_map, unsigned int intr_map_size,
346 unsigned int irqbase)
347{
348 unsigned int gicconfig;
349 int numvpes, numintrs;
350
351 _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
352 gic_addrspace_size);
353 gic_irq_base = irqbase;
354
355 GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
356 numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
357 GIC_SH_CONFIG_NUMINTRS_SHF;
358 numintrs = ((numintrs + 1) * 8);
359
360 numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
361 GIC_SH_CONFIG_NUMVPES_SHF;
362 numvpes = numvpes + 1;
363
364 gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
365
366 gic_platform_init(numintrs, &gic_irq_controller);
367}
368
