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35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/mm.h>
40#include <linux/slab.h>
41#include <linux/irq.h>
42
43#include <asm/errno.h>
44#include <asm/signal.h>
45#include <asm/ptrace.h>
46#include <asm/mipsregs.h>
47#include <asm/thread_info.h>
48
49#include <asm/netlogic/mips-extns.h>
50#include <asm/netlogic/interrupt.h>
51#include <asm/netlogic/haldefs.h>
52#include <asm/netlogic/common.h>
53
54#if defined(CONFIG_CPU_XLP)
55#include <asm/netlogic/xlp-hal/iomap.h>
56#include <asm/netlogic/xlp-hal/xlp.h>
57#include <asm/netlogic/xlp-hal/pic.h>
58#elif defined(CONFIG_CPU_XLR)
59#include <asm/netlogic/xlr/iomap.h>
60#include <asm/netlogic/xlr/pic.h>
61#include <asm/netlogic/xlr/fmn.h>
62#else
63#error "Unknown CPU"
64#endif
65
66#ifdef CONFIG_SMP
67#define SMP_IRQ_MASK ((1ULL << IRQ_IPI_SMP_FUNCTION) | \
68 (1ULL << IRQ_IPI_SMP_RESCHEDULE))
69#else
70#define SMP_IRQ_MASK 0
71#endif
72#define PERCPU_IRQ_MASK (SMP_IRQ_MASK | (1ull << IRQ_TIMER) | \
73 (1ull << IRQ_FMN))
74
75struct nlm_pic_irq {
76 void (*extra_ack)(struct irq_data *);
77 struct nlm_soc_info *node;
78 int picirq;
79 int irt;
80 int flags;
81};
82
83static void xlp_pic_enable(struct irq_data *d)
84{
85 unsigned long flags;
86 struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
87
88 BUG_ON(!pd);
89 spin_lock_irqsave(&pd->node->piclock, flags);
90 nlm_pic_enable_irt(pd->node->picbase, pd->irt);
91 spin_unlock_irqrestore(&pd->node->piclock, flags);
92}
93
94static void xlp_pic_disable(struct irq_data *d)
95{
96 struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
97 unsigned long flags;
98
99 BUG_ON(!pd);
100 spin_lock_irqsave(&pd->node->piclock, flags);
101 nlm_pic_disable_irt(pd->node->picbase, pd->irt);
102 spin_unlock_irqrestore(&pd->node->piclock, flags);
103}
104
105static void xlp_pic_mask_ack(struct irq_data *d)
106{
107 struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
108
109 clear_c0_eimr(pd->picirq);
110 ack_c0_eirr(pd->picirq);
111}
112
113static void xlp_pic_unmask(struct irq_data *d)
114{
115 struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
116
117 BUG_ON(!pd);
118
119 if (pd->extra_ack)
120 pd->extra_ack(d);
121
122
123 set_c0_eimr(pd->picirq);
124
125
126 nlm_pic_ack(pd->node->picbase, pd->irt);
127}
128
129static struct irq_chip xlp_pic = {
130 .name = "XLP-PIC",
131 .irq_enable = xlp_pic_enable,
132 .irq_disable = xlp_pic_disable,
133 .irq_mask_ack = xlp_pic_mask_ack,
134 .irq_unmask = xlp_pic_unmask,
135};
136
137static void cpuintr_disable(struct irq_data *d)
138{
139 clear_c0_eimr(d->irq);
140}
141
142static void cpuintr_enable(struct irq_data *d)
143{
144 set_c0_eimr(d->irq);
145}
146
147static void cpuintr_ack(struct irq_data *d)
148{
149 ack_c0_eirr(d->irq);
150}
151
152
153
154
155
156struct irq_chip nlm_cpu_intr = {
157 .name = "XLP-CPU-INTR",
158 .irq_enable = cpuintr_enable,
159 .irq_disable = cpuintr_disable,
160 .irq_mask = cpuintr_disable,
161 .irq_ack = cpuintr_ack,
162 .irq_eoi = cpuintr_enable,
163};
164
165static void __init nlm_init_percpu_irqs(void)
166{
167 int i;
168
169 for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
170 irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
171#ifdef CONFIG_SMP
172 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
173 nlm_smp_function_ipi_handler);
174 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
175 nlm_smp_resched_ipi_handler);
176#endif
177}
178
179void nlm_setup_pic_irq(int node, int picirq, int irq, int irt)
180{
181 struct nlm_pic_irq *pic_data;
182 int xirq;
183
184 xirq = nlm_irq_to_xirq(node, irq);
185 pic_data = kzalloc(sizeof(*pic_data), GFP_KERNEL);
186 BUG_ON(pic_data == NULL);
187 pic_data->irt = irt;
188 pic_data->picirq = picirq;
189 pic_data->node = nlm_get_node(node);
190 irq_set_chip_and_handler(xirq, &xlp_pic, handle_level_irq);
191 irq_set_handler_data(xirq, pic_data);
192}
193
194void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *))
195{
196 struct nlm_pic_irq *pic_data;
197 int xirq;
198
199 xirq = nlm_irq_to_xirq(node, irq);
200 pic_data = irq_get_handler_data(xirq);
201 pic_data->extra_ack = xack;
202}
203
204static void nlm_init_node_irqs(int node)
205{
206 int i, irt;
207 uint64_t irqmask;
208 struct nlm_soc_info *nodep;
209
210 pr_info("Init IRQ for node %d\n", node);
211 nodep = nlm_get_node(node);
212 irqmask = PERCPU_IRQ_MASK;
213 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) {
214 irt = nlm_irq_to_irt(i);
215 if (irt == -1)
216 continue;
217 nlm_setup_pic_irq(node, i, i, irt);
218
219 nlm_pic_init_irt(nodep->picbase, irt, i,
220 node * NLM_CPUS_PER_NODE, 0);
221 irqmask |= (1ull << i);
222 }
223 nodep->irqmask = irqmask;
224}
225
226void __init arch_init_irq(void)
227{
228
229 nlm_init_percpu_irqs();
230 nlm_init_node_irqs(0);
231 write_c0_eimr(nlm_current_node()->irqmask);
232#if defined(CONFIG_CPU_XLR)
233 nlm_setup_fmn_irq();
234#endif
235}
236
237void nlm_smp_irq_init(int hwcpuid)
238{
239 int node, cpu;
240
241 node = hwcpuid / NLM_CPUS_PER_NODE;
242 cpu = hwcpuid % NLM_CPUS_PER_NODE;
243
244 if (cpu == 0 && node != 0)
245 nlm_init_node_irqs(node);
246 write_c0_eimr(nlm_current_node()->irqmask);
247}
248
249asmlinkage void plat_irq_dispatch(void)
250{
251 uint64_t eirr;
252 int i, node;
253
254 node = nlm_nodeid();
255 eirr = read_c0_eirr_and_eimr();
256
257 i = __ilog2_u64(eirr);
258 if (i == -1)
259 return;
260
261
262 if (eirr & PERCPU_IRQ_MASK) {
263 do_IRQ(i);
264 return;
265 }
266
267
268 do_IRQ(nlm_irq_to_xirq(node, i));
269}
270