1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/smp.h>
23#include <linux/kernel_stat.h>
24#include <linux/sched.h>
25
26#include <asm/mmu_context.h>
27#include <asm/io.h>
28#include <asm/fw/cfe/cfe_api.h>
29#include <asm/sibyte/sb1250.h>
30#include <asm/sibyte/sb1250_regs.h>
31#include <asm/sibyte/sb1250_int.h>
32
33static void *mailbox_set_regs[] = {
34 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),
35 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
36};
37
38static void *mailbox_clear_regs[] = {
39 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
40 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
41};
42
43static void *mailbox_regs[] = {
44 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
45 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
46};
47
48
49
50
51void __cpuinit sb1250_smp_init(void)
52{
53 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
54 STATUSF_IP1 | STATUSF_IP0;
55
56
57 change_c0_status(ST0_IM, imask);
58}
59
60
61
62
63
64
65
66
67
68
69static void sb1250_send_ipi_single(int cpu, unsigned int action)
70{
71 __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
72}
73
74static inline void sb1250_send_ipi_mask(const struct cpumask *mask,
75 unsigned int action)
76{
77 unsigned int i;
78
79 for_each_cpu(i, mask)
80 sb1250_send_ipi_single(i, action);
81}
82
83
84
85
86static void __cpuinit sb1250_init_secondary(void)
87{
88 extern void sb1250_smp_init(void);
89
90 sb1250_smp_init();
91}
92
93
94
95
96
97static void __cpuinit sb1250_smp_finish(void)
98{
99 extern void sb1250_clockevent_init(void);
100
101 sb1250_clockevent_init();
102 local_irq_enable();
103}
104
105
106
107
108static void sb1250_cpus_done(void)
109{
110}
111
112
113
114
115
116static void __cpuinit sb1250_boot_secondary(int cpu, struct task_struct *idle)
117{
118 int retval;
119
120 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
121 __KSTK_TOS(idle),
122 (unsigned long)task_thread_info(idle), 0);
123 if (retval != 0)
124 printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
125}
126
127
128
129
130
131
132
133
134static void __init sb1250_smp_setup(void)
135{
136 int i, num;
137
138 init_cpu_possible(cpumask_of(0));
139 __cpu_number_map[0] = 0;
140 __cpu_logical_map[0] = 0;
141
142 for (i = 1, num = 0; i < NR_CPUS; i++) {
143 if (cfe_cpu_stop(i) == 0) {
144 set_cpu_possible(i, true);
145 __cpu_number_map[i] = ++num;
146 __cpu_logical_map[num] = i;
147 }
148 }
149 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
150}
151
152static void __init sb1250_prepare_cpus(unsigned int max_cpus)
153{
154}
155
156struct plat_smp_ops sb_smp_ops = {
157 .send_ipi_single = sb1250_send_ipi_single,
158 .send_ipi_mask = sb1250_send_ipi_mask,
159 .init_secondary = sb1250_init_secondary,
160 .smp_finish = sb1250_smp_finish,
161 .cpus_done = sb1250_cpus_done,
162 .boot_secondary = sb1250_boot_secondary,
163 .smp_setup = sb1250_smp_setup,
164 .prepare_cpus = sb1250_prepare_cpus,
165};
166
167void sb1250_mailbox_interrupt(void)
168{
169 int cpu = smp_processor_id();
170 int irq = K_INT_MBOX_0;
171 unsigned int action;
172
173 kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
174
175 action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff;
176
177
178 ____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]);
179
180 if (action & SMP_RESCHEDULE_YOURSELF)
181 scheduler_ipi();
182
183 if (action & SMP_CALL_FUNCTION)
184 smp_call_function_interrupt();
185}
186