LXR linux/arch/mips/wrppmc/irq.c

   1/*
   2 * irq.c: GT64120 Interrupt Controller
   3 *
   4 * Copyright (C) 2006, Wind River System Inc.
   5 * Author: Rongkai.Zhan, <rongkai.zhan@windriver.com>
   6 *
   7 * This program is free software; you can redistribute  it and/or modify it
   8 * under  the terms of  the GNU General  Public License as published by the
   9 * Free Software Foundation;  either version 2 of the  License, or (at your
  10 * option) any later version.
  11 */
  12#include <linux/hardirq.h>
  13#include <linux/init.h>
  14#include <linux/irq.h>
  15
  16#include <asm/gt64120.h>
  17#include <asm/irq_cpu.h>
  18#include <asm/mipsregs.h>
  19
  20asmlinkage void plat_irq_dispatch(void)
  21{
  22        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
  23
  24        if (pending & STATUSF_IP7)
  25                do_IRQ(WRPPMC_MIPS_TIMER_IRQ);  /* CPU Compare/Count internal timer */
  26        else if (pending & STATUSF_IP6)
  27                do_IRQ(WRPPMC_UART16550_IRQ);   /* UART 16550 port */
  28        else if (pending & STATUSF_IP3)
  29                do_IRQ(WRPPMC_PCI_INTA_IRQ);    /* PCI INT_A */
  30        else
  31                spurious_interrupt();
  32}
  33
  34/**
  35 * Initialize GT64120 Interrupt Controller
  36 */
  37void gt64120_init_pic(void)
  38{
  39        /* clear CPU Interrupt Cause Registers */
  40        GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21));
  41        GT_WRITE(GT_HINTRCAUSE_OFS, 0x00);
  42
  43        /* Disable all interrupts from GT64120 bridge chip */
  44        GT_WRITE(GT_INTRMASK_OFS, 0x00);
  45        GT_WRITE(GT_HINTRMASK_OFS, 0x00);
  46        GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00);
  47        GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00);
  48}
  49
  50void __init arch_init_irq(void)
  51{
  52        /* IRQ 0 - 7 are for MIPS common irq_cpu controller */
  53        mips_cpu_irq_init();
  54
  55        gt64120_init_pic();
  56}
  57