1/* 2 * base MPC5121 Device Tree Source 3 * 4 * Copyright 2007-2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "mpc5121"; 16 compatible = "fsl,mpc5121"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 interrupt-parent = <&ipic>; 20 21 aliases { 22 ethernet0 = ð0; 23 pci = &pci; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 PowerPC,5121@0 { 31 device_type = "cpu"; 32 reg = <0>; 33 d-cache-line-size = <0x20>; /* 32 bytes */ 34 i-cache-line-size = <0x20>; /* 32 bytes */ 35 d-cache-size = <0x8000>; /* L1, 32K */ 36 i-cache-size = <0x8000>; /* L1, 32K */ 37 timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */ 38 bus-frequency = <198000000>; /* 198 MHz csb bus */ 39 clock-frequency = <396000000>; /* 396 MHz ppc core */ 40 }; 41 }; 42 43 memory { 44 device_type = "memory"; 45 reg = <0x00000000 0x10000000>; /* 256MB at 0 */ 46 }; 47 48 mbx@20000000 { 49 compatible = "fsl,mpc5121-mbx"; 50 reg = <0x20000000 0x4000>; 51 interrupts = <66 0x8>; 52 }; 53 54 sram@30000000 { 55 compatible = "fsl,mpc5121-sram"; 56 reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */ 57 }; 58 59 nfc@40000000 { 60 compatible = "fsl,mpc5121-nfc"; 61 reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */ 62 interrupts = <6 8>; 63 #address-cells = <1>; 64 #size-cells = <1>; 65 }; 66 67 localbus@80000020 { 68 compatible = "fsl,mpc5121-localbus"; 69 #address-cells = <2>; 70 #size-cells = <1>; 71 reg = <0x80000020 0x40>; 72 interrupts = <7 0x8>; 73 ranges = <0x0 0x0 0xfc000000 0x04000000>; 74 }; 75 76 soc@80000000 { 77 compatible = "fsl,mpc5121-immr"; 78 #address-cells = <1>; 79 #size-cells = <1>; 80 #interrupt-cells = <2>; 81 ranges = <0x0 0x80000000 0x400000>; 82 reg = <0x80000000 0x400000>; 83 bus-frequency = <66000000>; /* 66 MHz ips bus */ 84 85 86 /* 87 * IPIC 88 * interrupts cell = <intr #, sense> 89 * sense values match linux IORESOURCE_IRQ_* defines: 90 * sense == 8: Level, low assertion 91 * sense == 2: Edge, high-to-low change 92 */ 93 ipic: interrupt-controller@c00 { 94 compatible = "fsl,mpc5121-ipic", "fsl,ipic"; 95 interrupt-controller; 96 #address-cells = <0>; 97 #interrupt-cells = <2>; 98 reg = <0xc00 0x100>; 99 }; 100 101 /* Watchdog timer */ 102 wdt@900 { 103 compatible = "fsl,mpc5121-wdt"; 104 reg = <0x900 0x100>; 105 }; 106 107 /* Real time clock */ 108 rtc@a00 { 109 compatible = "fsl,mpc5121-rtc"; 110 reg = <0xa00 0x100>; 111 interrupts = <79 0x8 80 0x8>; 112 }; 113 114 /* Reset module */ 115 reset@e00 { 116 compatible = "fsl,mpc5121-reset"; 117 reg = <0xe00 0x100>; 118 }; 119 120 /* Clock control */ 121 clock@f00 { 122 compatible = "fsl,mpc5121-clock"; 123 reg = <0xf00 0x100>; 124 }; 125 126 /* Power Management Controller */ 127 pmc@1000{ 128 compatible = "fsl,mpc5121-pmc"; 129 reg = <0x1000 0x100>; 130 interrupts = <83 0x8>; 131 }; 132 133 gpio@1100 { 134 compatible = "fsl,mpc5121-gpio"; 135 reg = <0x1100 0x100>; 136 interrupts = <78 0x8>; 137 }; 138 139 can@1300 { 140 compatible = "fsl,mpc5121-mscan"; 141 reg = <0x1300 0x80>; 142 interrupts = <12 0x8>; 143 }; 144 145 can@1380 { 146 compatible = "fsl,mpc5121-mscan"; 147 reg = <0x1380 0x80>; 148 interrupts = <13 0x8>; 149 }; 150 151 sdhc@1500 { 152 compatible = "fsl,mpc5121-sdhc"; 153 reg = <0x1500 0x100>; 154 interrupts = <8 0x8>; 155 dmas = <&dma0 30>; 156 dma-names = "rx-tx"; 157 }; 158 159 i2c@1700 { 160 #address-cells = <1>; 161 #size-cells = <0>; 162 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 163 reg = <0x1700 0x20>; 164 interrupts = <9 0x8>; 165 }; 166 167 i2c@1720 { 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 171 reg = <0x1720 0x20>; 172 interrupts = <10 0x8>; 173 }; 174 175 i2c@1740 { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 179 reg = <0x1740 0x20>; 180 interrupts = <11 0x8>; 181 }; 182 183 i2ccontrol@1760 { 184 compatible = "fsl,mpc5121-i2c-ctrl"; 185 reg = <0x1760 0x8>; 186 }; 187 188 axe@2000 { 189 compatible = "fsl,mpc5121-axe"; 190 reg = <0x2000 0x100>; 191 interrupts = <42 0x8>; 192 }; 193 194 display@2100 { 195 compatible = "fsl,mpc5121-diu"; 196 reg = <0x2100 0x100>; 197 interrupts = <64 0x8>; 198 }; 199 200 can@2300 { 201 compatible = "fsl,mpc5121-mscan"; 202 reg = <0x2300 0x80>; 203 interrupts = <90 0x8>; 204 }; 205 206 can@2380 { 207 compatible = "fsl,mpc5121-mscan"; 208 reg = <0x2380 0x80>; 209 interrupts = <91 0x8>; 210 }; 211 212 viu@2400 { 213 compatible = "fsl,mpc5121-viu"; 214 reg = <0x2400 0x400>; 215 interrupts = <67 0x8>; 216 }; 217 218 mdio@2800 { 219 compatible = "fsl,mpc5121-fec-mdio"; 220 reg = <0x2800 0x800>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 }; 224 225 eth0: ethernet@2800 { 226 device_type = "network"; 227 compatible = "fsl,mpc5121-fec"; 228 reg = <0x2800 0x800>; 229 local-mac-address = [ 00 00 00 00 00 00 ]; 230 interrupts = <4 0x8>; 231 }; 232 233 /* USB1 using external ULPI PHY */ 234 usb@3000 { 235 compatible = "fsl,mpc5121-usb2-dr"; 236 reg = <0x3000 0x600>; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 interrupts = <43 0x8>; 240 dr_mode = "otg"; 241 phy_type = "ulpi"; 242 }; 243 244 /* USB0 using internal UTMI PHY */ 245 usb@4000 { 246 compatible = "fsl,mpc5121-usb2-dr"; 247 reg = <0x4000 0x600>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 interrupts = <44 0x8>; 251 dr_mode = "otg"; 252 phy_type = "utmi_wide"; 253 }; 254 255 /* IO control */ 256 ioctl@a000 { 257 compatible = "fsl,mpc5121-ioctl"; 258 reg = <0xA000 0x1000>; 259 }; 260 261 /* LocalPlus controller */ 262 lpc@10000 { 263 compatible = "fsl,mpc5121-lpc"; 264 reg = <0x10000 0x200>; 265 }; 266 267 pata@10200 { 268 compatible = "fsl,mpc5121-pata"; 269 reg = <0x10200 0x100>; 270 interrupts = <5 0x8>; 271 }; 272 273 /* 512x PSCs are not 52xx PSC compatible */ 274 275 /* PSC0 */ 276 psc@11000 { 277 compatible = "fsl,mpc5121-psc"; 278 reg = <0x11000 0x100>; 279 interrupts = <40 0x8>; 280 fsl,rx-fifo-size = <16>; 281 fsl,tx-fifo-size = <16>; 282 }; 283 284 /* PSC1 */ 285 psc@11100 { 286 compatible = "fsl,mpc5121-psc"; 287 reg = <0x11100 0x100>; 288 interrupts = <40 0x8>; 289 fsl,rx-fifo-size = <16>; 290 fsl,tx-fifo-size = <16>; 291 }; 292 293 /* PSC2 */ 294 psc@11200 { 295 compatible = "fsl,mpc5121-psc"; 296 reg = <0x11200 0x100>; 297 interrupts = <40 0x8>; 298 fsl,rx-fifo-size = <16>; 299 fsl,tx-fifo-size = <16>; 300 }; 301 302 /* PSC3 */ 303 psc@11300 { 304 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 305 reg = <0x11300 0x100>; 306 interrupts = <40 0x8>; 307 fsl,rx-fifo-size = <16>; 308 fsl,tx-fifo-size = <16>; 309 }; 310 311 /* PSC4 */ 312 psc@11400 { 313 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 314 reg = <0x11400 0x100>; 315 interrupts = <40 0x8>; 316 fsl,rx-fifo-size = <16>; 317 fsl,tx-fifo-size = <16>; 318 }; 319 320 /* PSC5 */ 321 psc@11500 { 322 compatible = "fsl,mpc5121-psc"; 323 reg = <0x11500 0x100>; 324 interrupts = <40 0x8>; 325 fsl,rx-fifo-size = <16>; 326 fsl,tx-fifo-size = <16>; 327 }; 328 329 /* PSC6 */ 330 psc@11600 { 331 compatible = "fsl,mpc5121-psc"; 332 reg = <0x11600 0x100>; 333 interrupts = <40 0x8>; 334 fsl,rx-fifo-size = <16>; 335 fsl,tx-fifo-size = <16>; 336 }; 337 338 /* PSC7 */ 339 psc@11700 { 340 compatible = "fsl,mpc5121-psc"; 341 reg = <0x11700 0x100>; 342 interrupts = <40 0x8>; 343 fsl,rx-fifo-size = <16>; 344 fsl,tx-fifo-size = <16>; 345 }; 346 347 /* PSC8 */ 348 psc@11800 { 349 compatible = "fsl,mpc5121-psc"; 350 reg = <0x11800 0x100>; 351 interrupts = <40 0x8>; 352 fsl,rx-fifo-size = <16>; 353 fsl,tx-fifo-size = <16>; 354 }; 355 356 /* PSC9 */ 357 psc@11900 { 358 compatible = "fsl,mpc5121-psc"; 359 reg = <0x11900 0x100>; 360 interrupts = <40 0x8>; 361 fsl,rx-fifo-size = <16>; 362 fsl,tx-fifo-size = <16>; 363 }; 364 365 /* PSC10 */ 366 psc@11a00 { 367 compatible = "fsl,mpc5121-psc"; 368 reg = <0x11a00 0x100>; 369 interrupts = <40 0x8>; 370 fsl,rx-fifo-size = <16>; 371 fsl,tx-fifo-size = <16>; 372 }; 373 374 /* PSC11 */ 375 psc@11b00 { 376 compatible = "fsl,mpc5121-psc"; 377 reg = <0x11b00 0x100>; 378 interrupts = <40 0x8>; 379 fsl,rx-fifo-size = <16>; 380 fsl,tx-fifo-size = <16>; 381 }; 382 383 pscfifo@11f00 { 384 compatible = "fsl,mpc5121-psc-fifo"; 385 reg = <0x11f00 0x100>; 386 interrupts = <40 0x8>; 387 }; 388 389 dma0: dma@14000 { 390 compatible = "fsl,mpc5121-dma"; 391 reg = <0x14000 0x1800>; 392 interrupts = <65 0x8>; 393 }; 394 }; 395 396 pci: pci@80008500 { 397 compatible = "fsl,mpc5121-pci"; 398 device_type = "pci"; 399 interrupts = <1 0x8>; 400 clock-frequency = <0>; 401 #address-cells = <3>; 402 #size-cells = <2>; 403 #interrupt-cells = <1>; 404 405 reg = <0x80008500 0x100 /* internal registers */ 406 0x80008300 0x8>; /* config space access registers */ 407 bus-range = <0x0 0x0>; 408 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 409 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 410 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>; 411 }; 412}; 413