1/* 2 * MPC85xx/86xx PCI Express structure define 3 * 4 * Copyright 2007,2011 Freescale Semiconductor, Inc 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 */ 12 13#ifdef __KERNEL__ 14#ifndef __POWERPC_FSL_PCI_H 15#define __POWERPC_FSL_PCI_H 16 17struct platform_device; 18 19#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ 20#define PCIE_LTSSM_L0 0x16 /* L0 state */ 21#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */ 22#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */ 23#define PIWAR_EN 0x80000000 /* Enable */ 24#define PIWAR_PF 0x20000000 /* prefetch */ 25#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ 26#define PIWAR_READ_SNOOP 0x00050000 27#define PIWAR_WRITE_SNOOP 0x00005000 28#define PIWAR_SZ_MASK 0x0000003f 29 30/* PCI/PCI Express outbound window reg */ 31struct pci_outbound_window_regs { 32 __be32 potar; /* 0x.0 - Outbound translation address register */ 33 __be32 potear; /* 0x.4 - Outbound translation extended address register */ 34 __be32 powbar; /* 0x.8 - Outbound window base address register */ 35 u8 res1[4]; 36 __be32 powar; /* 0x.10 - Outbound window attributes register */ 37 u8 res2[12]; 38}; 39 40/* PCI/PCI Express inbound window reg */ 41struct pci_inbound_window_regs { 42 __be32 pitar; /* 0x.0 - Inbound translation address register */ 43 u8 res1[4]; 44 __be32 piwbar; /* 0x.8 - Inbound window base address register */ 45 __be32 piwbear; /* 0x.c - Inbound window base extended address register */ 46 __be32 piwar; /* 0x.10 - Inbound window attributes register */ 47 u8 res2[12]; 48}; 49 50/* PCI/PCI Express IO block registers for 85xx/86xx */ 51struct ccsr_pci { 52 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */ 53 __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */ 54 __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ 55 __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */ 56 __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */ 57 __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */ 58 __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */ 59 u8 res2[4]; 60 __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */ 61 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */ 62 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */ 63 __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */ 64 u8 res3[3016]; 65 __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */ 66 __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */ 67 68/* PCI/PCI Express outbound window 0-4 69 * Window 0 is the default window and is the only window enabled upon reset. 70 * The default outbound register set is used when a transaction misses 71 * in all of the other outbound windows. 72 */ 73 struct pci_outbound_window_regs pow[5]; 74 u8 res14[96]; 75 struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */ 76 u8 res6[96]; 77/* PCI/PCI Express inbound window 3-0 78 * inbound window 1 supports only a 32-bit base address and does not 79 * define an inbound window base extended address register. 80 */ 81 struct pci_inbound_window_regs piw[4]; 82 83 __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ 84 u8 res21[4]; 85 __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */ 86 u8 res22[4]; 87 __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */ 88 u8 res23[12]; 89 __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */ 90 u8 res24[4]; 91 __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */ 92 __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ 93 __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ 94 __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ 95 u8 res_e38[200]; 96 __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */ 97 u8 res_f04[16]; 98 __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/ 99#define PEX_CSR0_LTSSM_MASK 0xFC 100#define PEX_CSR0_LTSSM_SHIFT 2 101#define PEX_CSR0_LTSSM_L0 0x11 102 __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/ 103 u8 res_f1c[228]; 104 105}; 106 107extern int fsl_add_bridge(struct platform_device *pdev, int is_primary); 108extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); 109extern int mpc83xx_add_bridge(struct device_node *dev); 110u64 fsl_pci_immrbar_base(struct pci_controller *hose); 111 112extern struct device_node *fsl_pci_primary; 113 114#ifdef CONFIG_PCI 115void fsl_pci_assign_primary(void); 116#else 117static inline void fsl_pci_assign_primary(void) {} 118#endif 119 120#ifdef CONFIG_EDAC_MPC85XX 121int mpc85xx_pci_err_probe(struct platform_device *op); 122#else 123static inline int mpc85xx_pci_err_probe(struct platform_device *op) 124{ 125 return -ENOTSUPP; 126} 127#endif 128 129#endif /* __POWERPC_FSL_PCI_H */ 130#endif /* __KERNEL__ */ 131