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17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/reboot.h>
21#include <linux/slab.h>
22#include <linux/stddef.h>
23#include <linux/sched.h>
24#include <linux/signal.h>
25#include <linux/device.h>
26#include <linux/bootmem.h>
27#include <linux/spinlock.h>
28#include <asm/irq.h>
29#include <asm/io.h>
30#include <asm/prom.h>
31#include <asm/qe_ic.h>
32
33#include "qe_ic.h"
34
35static DEFINE_RAW_SPINLOCK(qe_ic_lock);
36
37static struct qe_ic_info qe_ic_info[] = {
38 [1] = {
39 .mask = 0x00008000,
40 .mask_reg = QEIC_CIMR,
41 .pri_code = 0,
42 .pri_reg = QEIC_CIPWCC,
43 },
44 [2] = {
45 .mask = 0x00004000,
46 .mask_reg = QEIC_CIMR,
47 .pri_code = 1,
48 .pri_reg = QEIC_CIPWCC,
49 },
50 [3] = {
51 .mask = 0x00002000,
52 .mask_reg = QEIC_CIMR,
53 .pri_code = 2,
54 .pri_reg = QEIC_CIPWCC,
55 },
56 [10] = {
57 .mask = 0x00000040,
58 .mask_reg = QEIC_CIMR,
59 .pri_code = 1,
60 .pri_reg = QEIC_CIPZCC,
61 },
62 [11] = {
63 .mask = 0x00000020,
64 .mask_reg = QEIC_CIMR,
65 .pri_code = 2,
66 .pri_reg = QEIC_CIPZCC,
67 },
68 [12] = {
69 .mask = 0x00000010,
70 .mask_reg = QEIC_CIMR,
71 .pri_code = 3,
72 .pri_reg = QEIC_CIPZCC,
73 },
74 [13] = {
75 .mask = 0x00000008,
76 .mask_reg = QEIC_CIMR,
77 .pri_code = 4,
78 .pri_reg = QEIC_CIPZCC,
79 },
80 [14] = {
81 .mask = 0x00000004,
82 .mask_reg = QEIC_CIMR,
83 .pri_code = 5,
84 .pri_reg = QEIC_CIPZCC,
85 },
86 [15] = {
87 .mask = 0x00000002,
88 .mask_reg = QEIC_CIMR,
89 .pri_code = 6,
90 .pri_reg = QEIC_CIPZCC,
91 },
92 [20] = {
93 .mask = 0x10000000,
94 .mask_reg = QEIC_CRIMR,
95 .pri_code = 3,
96 .pri_reg = QEIC_CIPRTA,
97 },
98 [25] = {
99 .mask = 0x00800000,
100 .mask_reg = QEIC_CRIMR,
101 .pri_code = 0,
102 .pri_reg = QEIC_CIPRTB,
103 },
104 [26] = {
105 .mask = 0x00400000,
106 .mask_reg = QEIC_CRIMR,
107 .pri_code = 1,
108 .pri_reg = QEIC_CIPRTB,
109 },
110 [27] = {
111 .mask = 0x00200000,
112 .mask_reg = QEIC_CRIMR,
113 .pri_code = 2,
114 .pri_reg = QEIC_CIPRTB,
115 },
116 [28] = {
117 .mask = 0x00100000,
118 .mask_reg = QEIC_CRIMR,
119 .pri_code = 3,
120 .pri_reg = QEIC_CIPRTB,
121 },
122 [32] = {
123 .mask = 0x80000000,
124 .mask_reg = QEIC_CIMR,
125 .pri_code = 0,
126 .pri_reg = QEIC_CIPXCC,
127 },
128 [33] = {
129 .mask = 0x40000000,
130 .mask_reg = QEIC_CIMR,
131 .pri_code = 1,
132 .pri_reg = QEIC_CIPXCC,
133 },
134 [34] = {
135 .mask = 0x20000000,
136 .mask_reg = QEIC_CIMR,
137 .pri_code = 2,
138 .pri_reg = QEIC_CIPXCC,
139 },
140 [35] = {
141 .mask = 0x10000000,
142 .mask_reg = QEIC_CIMR,
143 .pri_code = 3,
144 .pri_reg = QEIC_CIPXCC,
145 },
146 [36] = {
147 .mask = 0x08000000,
148 .mask_reg = QEIC_CIMR,
149 .pri_code = 4,
150 .pri_reg = QEIC_CIPXCC,
151 },
152 [40] = {
153 .mask = 0x00800000,
154 .mask_reg = QEIC_CIMR,
155 .pri_code = 0,
156 .pri_reg = QEIC_CIPYCC,
157 },
158 [41] = {
159 .mask = 0x00400000,
160 .mask_reg = QEIC_CIMR,
161 .pri_code = 1,
162 .pri_reg = QEIC_CIPYCC,
163 },
164 [42] = {
165 .mask = 0x00200000,
166 .mask_reg = QEIC_CIMR,
167 .pri_code = 2,
168 .pri_reg = QEIC_CIPYCC,
169 },
170 [43] = {
171 .mask = 0x00100000,
172 .mask_reg = QEIC_CIMR,
173 .pri_code = 3,
174 .pri_reg = QEIC_CIPYCC,
175 },
176};
177
178static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
179{
180 return in_be32(base + (reg >> 2));
181}
182
183static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
184 u32 value)
185{
186 out_be32(base + (reg >> 2), value);
187}
188
189static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
190{
191 return irq_get_chip_data(virq);
192}
193
194static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
195{
196 return irq_data_get_irq_chip_data(d);
197}
198
199static void qe_ic_unmask_irq(struct irq_data *d)
200{
201 struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
202 unsigned int src = irqd_to_hwirq(d);
203 unsigned long flags;
204 u32 temp;
205
206 raw_spin_lock_irqsave(&qe_ic_lock, flags);
207
208 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
209 qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
210 temp | qe_ic_info[src].mask);
211
212 raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
213}
214
215static void qe_ic_mask_irq(struct irq_data *d)
216{
217 struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
218 unsigned int src = irqd_to_hwirq(d);
219 unsigned long flags;
220 u32 temp;
221
222 raw_spin_lock_irqsave(&qe_ic_lock, flags);
223
224 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
225 qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
226 temp & ~qe_ic_info[src].mask);
227
228
229
230
231
232
233
234
235
236 mb();
237
238 raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
239}
240
241static struct irq_chip qe_ic_irq_chip = {
242 .name = "QEIC",
243 .irq_unmask = qe_ic_unmask_irq,
244 .irq_mask = qe_ic_mask_irq,
245 .irq_mask_ack = qe_ic_mask_irq,
246};
247
248static int qe_ic_host_match(struct irq_domain *h, struct device_node *node)
249{
250
251 return h->of_node == NULL || h->of_node == node;
252}
253
254static int qe_ic_host_map(struct irq_domain *h, unsigned int virq,
255 irq_hw_number_t hw)
256{
257 struct qe_ic *qe_ic = h->host_data;
258 struct irq_chip *chip;
259
260 if (qe_ic_info[hw].mask == 0) {
261 printk(KERN_ERR "Can't map reserved IRQ\n");
262 return -EINVAL;
263 }
264
265 chip = &qe_ic->hc_irq;
266
267 irq_set_chip_data(virq, qe_ic);
268 irq_set_status_flags(virq, IRQ_LEVEL);
269
270 irq_set_chip_and_handler(virq, chip, handle_level_irq);
271
272 return 0;
273}
274
275static struct irq_domain_ops qe_ic_host_ops = {
276 .match = qe_ic_host_match,
277 .map = qe_ic_host_map,
278 .xlate = irq_domain_xlate_onetwocell,
279};
280
281
282unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
283{
284 int irq;
285
286 BUG_ON(qe_ic == NULL);
287
288
289 irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
290
291 if (irq == 0)
292 return NO_IRQ;
293
294 return irq_linear_revmap(qe_ic->irqhost, irq);
295}
296
297
298unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
299{
300 int irq;
301
302 BUG_ON(qe_ic == NULL);
303
304
305 irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
306
307 if (irq == 0)
308 return NO_IRQ;
309
310 return irq_linear_revmap(qe_ic->irqhost, irq);
311}
312
313void __init qe_ic_init(struct device_node *node, unsigned int flags,
314 void (*low_handler)(unsigned int irq, struct irq_desc *desc),
315 void (*high_handler)(unsigned int irq, struct irq_desc *desc))
316{
317 struct qe_ic *qe_ic;
318 struct resource res;
319 u32 temp = 0, ret, high_active = 0;
320
321 ret = of_address_to_resource(node, 0, &res);
322 if (ret)
323 return;
324
325 qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
326 if (qe_ic == NULL)
327 return;
328
329 qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
330 &qe_ic_host_ops, qe_ic);
331 if (qe_ic->irqhost == NULL) {
332 kfree(qe_ic);
333 return;
334 }
335
336 qe_ic->regs = ioremap(res.start, resource_size(&res));
337
338 qe_ic->hc_irq = qe_ic_irq_chip;
339
340 qe_ic->virq_high = irq_of_parse_and_map(node, 0);
341 qe_ic->virq_low = irq_of_parse_and_map(node, 1);
342
343 if (qe_ic->virq_low == NO_IRQ) {
344 printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
345 kfree(qe_ic);
346 return;
347 }
348
349
350
351 if (flags & QE_IC_SPREADMODE_GRP_W)
352 temp |= CICR_GWCC;
353 if (flags & QE_IC_SPREADMODE_GRP_X)
354 temp |= CICR_GXCC;
355 if (flags & QE_IC_SPREADMODE_GRP_Y)
356 temp |= CICR_GYCC;
357 if (flags & QE_IC_SPREADMODE_GRP_Z)
358 temp |= CICR_GZCC;
359 if (flags & QE_IC_SPREADMODE_GRP_RISCA)
360 temp |= CICR_GRTA;
361 if (flags & QE_IC_SPREADMODE_GRP_RISCB)
362 temp |= CICR_GRTB;
363
364
365 if (flags & QE_IC_HIGH_SIGNAL) {
366 temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
367 high_active = 1;
368 }
369
370 qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
371
372 irq_set_handler_data(qe_ic->virq_low, qe_ic);
373 irq_set_chained_handler(qe_ic->virq_low, low_handler);
374
375 if (qe_ic->virq_high != NO_IRQ &&
376 qe_ic->virq_high != qe_ic->virq_low) {
377 irq_set_handler_data(qe_ic->virq_high, qe_ic);
378 irq_set_chained_handler(qe_ic->virq_high, high_handler);
379 }
380}
381
382void qe_ic_set_highest_priority(unsigned int virq, int high)
383{
384 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
385 unsigned int src = virq_to_hw(virq);
386 u32 temp = 0;
387
388 temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
389
390 temp &= ~CICR_HP_MASK;
391 temp |= src << CICR_HP_SHIFT;
392
393 temp &= ~CICR_HPIT_MASK;
394 temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
395
396 qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
397}
398
399
400int qe_ic_set_priority(unsigned int virq, unsigned int priority)
401{
402 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
403 unsigned int src = virq_to_hw(virq);
404 u32 temp;
405
406 if (priority > 8 || priority == 0)
407 return -EINVAL;
408 if (src > 127)
409 return -EINVAL;
410 if (qe_ic_info[src].pri_reg == 0)
411 return -EINVAL;
412
413 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
414
415 if (priority < 4) {
416 temp &= ~(0x7 << (32 - priority * 3));
417 temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
418 } else {
419 temp &= ~(0x7 << (24 - priority * 3));
420 temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
421 }
422
423 qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
424
425 return 0;
426}
427
428
429int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
430{
431 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
432 unsigned int src = virq_to_hw(virq);
433 u32 temp, control_reg = QEIC_CICNR, shift = 0;
434
435 if (priority > 2 || priority == 0)
436 return -EINVAL;
437
438 switch (qe_ic_info[src].pri_reg) {
439 case QEIC_CIPZCC:
440 shift = CICNR_ZCC1T_SHIFT;
441 break;
442 case QEIC_CIPWCC:
443 shift = CICNR_WCC1T_SHIFT;
444 break;
445 case QEIC_CIPYCC:
446 shift = CICNR_YCC1T_SHIFT;
447 break;
448 case QEIC_CIPXCC:
449 shift = CICNR_XCC1T_SHIFT;
450 break;
451 case QEIC_CIPRTA:
452 shift = CRICR_RTA1T_SHIFT;
453 control_reg = QEIC_CRICR;
454 break;
455 case QEIC_CIPRTB:
456 shift = CRICR_RTB1T_SHIFT;
457 control_reg = QEIC_CRICR;
458 break;
459 default:
460 return -EINVAL;
461 }
462
463 shift += (2 - priority) * 2;
464 temp = qe_ic_read(qe_ic->regs, control_reg);
465 temp &= ~(SIGNAL_MASK << shift);
466 temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
467 qe_ic_write(qe_ic->regs, control_reg, temp);
468
469 return 0;
470}
471
472static struct bus_type qe_ic_subsys = {
473 .name = "qe_ic",
474 .dev_name = "qe_ic",
475};
476
477static struct device device_qe_ic = {
478 .id = 0,
479 .bus = &qe_ic_subsys,
480};
481
482static int __init init_qe_ic_sysfs(void)
483{
484 int rc;
485
486 printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
487
488 rc = subsys_system_register(&qe_ic_subsys, NULL);
489 if (rc) {
490 printk(KERN_ERR "Failed registering qe_ic sys class\n");
491 return -ENODEV;
492 }
493 rc = device_register(&device_qe_ic);
494 if (rc) {
495 printk(KERN_ERR "Failed registering qe_ic sys device\n");
496 return -ENODEV;
497 }
498 return 0;
499}
500
501subsys_initcall(init_qe_ic_sysfs);
502
