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25#ifndef _SFP_MACHINE_H
26#define _SFP_MACHINE_H
27
28
29#define _FP_W_TYPE_SIZE 32
30#define _FP_W_TYPE unsigned int
31#define _FP_WS_TYPE signed int
32#define _FP_I_TYPE int
33
34#define _FP_MUL_MEAT_S(R,X,Y) \
35 _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
36#define _FP_MUL_MEAT_D(R,X,Y) \
37 _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
38#define _FP_MUL_MEAT_Q(R,X,Y) \
39 _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
40
41#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv(S,R,X,Y)
42#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
43#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
44
45#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
46#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
47#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
48#define _FP_NANSIGN_S 0
49#define _FP_NANSIGN_D 0
50#define _FP_NANSIGN_Q 0
51
52#define _FP_KEEPNANFRACP 1
53
54
55
56
57
58#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
59 do { \
60 if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \
61 && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \
62 { \
63 R##_s = Y##_s; \
64 _FP_FRAC_COPY_##wc(R,Y); \
65 } \
66 else \
67 { \
68 R##_s = X##_s; \
69 _FP_FRAC_COPY_##wc(R,X); \
70 } \
71 R##_c = FP_CLS_NAN; \
72 } while (0)
73
74
75#define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) ({ \
76 unsigned int __r2 = (x2) + (y2); \
77 unsigned int __r1 = (x1); \
78 unsigned int __r0 = (x0); \
79 asm volatile( \
80 " alr %2,%3\n" \
81 " brc 12,0f\n" \
82 " lhi 0,1\n" \
83 " alr %1,0\n" \
84 " brc 12,0f\n" \
85 " alr %0,0\n" \
86 "0:" \
87 : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0) \
88 : "d" (y0), "i" (1) : "cc", "0" ); \
89 asm volatile( \
90 " alr %1,%2\n" \
91 " brc 12,0f\n" \
92 " ahi %0,1\n" \
93 "0:" \
94 : "+&d" (__r2), "+&d" (__r1) \
95 : "d" (y1) : "cc"); \
96 (r2) = __r2; \
97 (r1) = __r1; \
98 (r0) = __r0; \
99})
100
101#define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) ({ \
102 unsigned int __r2 = (x2) - (y2); \
103 unsigned int __r1 = (x1); \
104 unsigned int __r0 = (x0); \
105 asm volatile( \
106 " slr %2,%3\n" \
107 " brc 3,0f\n" \
108 " lhi 0,1\n" \
109 " slr %1,0\n" \
110 " brc 3,0f\n" \
111 " slr %0,0\n" \
112 "0:" \
113 : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0) \
114 : "d" (y0) : "cc", "0"); \
115 asm volatile( \
116 " slr %1,%2\n" \
117 " brc 3,0f\n" \
118 " ahi %0,-1\n" \
119 "0:" \
120 : "+&d" (__r2), "+&d" (__r1) \
121 : "d" (y1) : "cc"); \
122 (r2) = __r2; \
123 (r1) = __r1; \
124 (r0) = __r0; \
125})
126
127#define __FP_FRAC_DEC_3(x2,x1,x0,y2,y1,y0) __FP_FRAC_SUB_3(x2,x1,x0,x2,x1,x0,y2,y1,y0)
128
129
130#define FP_ROUNDMODE mode
131
132
133#define FP_EX_INVALID 0x800000
134#define FP_EX_DIVZERO 0x400000
135#define FP_EX_OVERFLOW 0x200000
136#define FP_EX_UNDERFLOW 0x100000
137#define FP_EX_INEXACT 0x080000
138
139
140#define FP_INHIBIT_RESULTS 0
141
142#endif
143
