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11#ifndef _ASM_X86_UV_UV_BAU_H
12#define _ASM_X86_UV_UV_BAU_H
13
14#include <linux/bitmap.h>
15#define BITSPERBYTE 8
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35
36#define MAX_CPUS_PER_UVHUB 64
37#define MAX_CPUS_PER_SOCKET 32
38#define ADP_SZ 64
39#define UV_CPUS_PER_AS 32
40#define ITEMS_PER_DESC 8
41
42#define MAX_BAU_CONCURRENT 3
43#define UV_ACT_STATUS_MASK 0x3
44#define UV_ACT_STATUS_SIZE 2
45#define UV_DISTRIBUTION_SIZE 256
46#define UV_SW_ACK_NPENDING 8
47#define UV1_NET_ENDPOINT_INTD 0x38
48#define UV2_NET_ENDPOINT_INTD 0x28
49#define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51#define UV_DESC_PSHIFT 49
52#define UV_PAYLOADQ_PNODE_SHIFT 49
53#define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
54#define UV_BAU_BASENAME "sgi_uv/bau_tunables"
55#define UV_BAU_TUNABLES_DIR "sgi_uv"
56#define UV_BAU_TUNABLES_FILE "bau_tunables"
57#define WHITESPACE " \t\n"
58#define uv_mmask ((1UL << uv_hub_info->m_val) - 1)
59#define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
60#define cpubit_isset(cpu, bau_local_cpumask) \
61 test_bit((cpu), (bau_local_cpumask).bits)
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69
70#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
71#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
72
73#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
74 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
75 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
76
77#define BAU_MISC_CONTROL_MULT_MASK 3
78
79#define UVH_AGING_PRESCALE_SEL 0x000000b000UL
80
81#define BAU_URGENCY_7_SHIFT 28
82#define BAU_URGENCY_7_MASK 7
83
84#define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
85
86#define BAU_TRANS_SHIFT 40
87#define BAU_TRANS_MASK 0x3f
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91
92#define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
93#define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
94#define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
95#define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
96#define write_gmmr uv_write_global_mmr64
97#define write_lmmr uv_write_local_mmr
98#define read_lmmr uv_read_local_mmr
99#define read_gmmr uv_read_global_mmr64
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103
104#define DS_IDLE 0
105#define DS_ACTIVE 1
106#define DS_DESTINATION_TIMEOUT 2
107#define DS_SOURCE_TIMEOUT 3
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119
120#define UV2H_DESC_IDLE 0
121#define UV2H_DESC_BUSY 2
122#define UV2H_DESC_DEST_TIMEOUT 4
123#define UV2H_DESC_DEST_STRONG_NACK 5
124#define UV2H_DESC_SOURCE_TIMEOUT 6
125#define UV2H_DESC_DEST_PUT_ERR 7
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129
130#define PLUGGED_DELAY 10
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136#define PLUGSB4RESET 100
137
138#define TIMEOUTSB4RESET 1
139
140#define IPI_RESET_LIMIT 1
141
142#define COMPLETE_THRESHOLD 5
143
144
145#define GIVEUP_LIMIT 100
146
147#define UV_LB_SUBNODEID 0x10
148
149
150#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
151#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
152
153#define UV2_ACK_MASK 0x7UL
154#define UV2_ACK_UNITS_SHFT 3
155#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
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159
160#define DEST_Q_SIZE 20
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164#define DEST_NUM_RESOURCES 8
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168#define FLUSH_RETRY_PLUGGED 1
169#define FLUSH_RETRY_TIMEOUT 2
170#define FLUSH_GIVEUP 3
171#define FLUSH_COMPLETE 4
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175
176#define CONGESTED_RESPONSE_US 1000
177
178#define CONGESTED_REPS 10
179
180#define DISABLED_PERIOD 10
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182
183#define MSG_NOOP 0
184#define MSG_REGULAR 1
185#define MSG_RETRY 2
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196
197struct pnmask {
198 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
199};
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206struct bau_local_cpumask {
207 unsigned long bits;
208};
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227struct bau_msg_payload {
228 unsigned long address;
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231 unsigned short sending_cpu;
232
233 unsigned short acknowledge_count;
234
235 unsigned int reserved1:32;
236};
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242
243struct uv1_bau_msg_header {
244 unsigned int dest_subnodeid:6;
245
246 unsigned int base_dest_nasid:15;
247
248 unsigned int command:8;
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251 unsigned int rsvd_1:3;
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254 unsigned int rsvd_2:9;
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257 unsigned int sequence:16;
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264 unsigned int rsvd_3:1;
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269 unsigned int replied_to:1;
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272 unsigned int msg_type:3;
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275 unsigned int canceled:1;
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278 unsigned int payload_1a:1;
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280 unsigned int payload_1b:2;
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284 unsigned int payload_1ca:6;
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286 unsigned int payload_1c:2;
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290 unsigned int payload_1d:6;
291
292 unsigned int payload_1e:2;
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295 unsigned int rsvd_4:7;
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297 unsigned int swack_flag:1;
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302 unsigned int rsvd_5:6;
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304 unsigned int rsvd_6:5;
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306 unsigned int int_both:1;
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309 unsigned int fairness:3;
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311 unsigned int multilevel:1;
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315 unsigned int chaining:1;
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318 unsigned int rsvd_7:21;
319
320};
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326struct uv2_bau_msg_header {
327 unsigned int base_dest_nasid:15;
328
329 unsigned int dest_subnodeid:5;
330
331 unsigned int rsvd_1:1;
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337 unsigned int replied_to:1;
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340 unsigned int msg_type:3;
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343 unsigned int canceled:1;
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346 unsigned int payload_1:3;
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350 unsigned int payload_2a:3;
351 unsigned int payload_2b:5;
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355 unsigned int payload_3:8;
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358 unsigned int rsvd_2:7;
359
360 unsigned int swack_flag:1;
361
362 unsigned int rsvd_3a:3;
363 unsigned int rsvd_3b:8;
364 unsigned int rsvd_3c:8;
365 unsigned int rsvd_3d:3;
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367 unsigned int fairness:3;
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370 unsigned int sequence:16;
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372 unsigned int chaining:1;
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375 unsigned int multilevel:1;
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378 unsigned int rsvd_4:24;
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382 unsigned int command:8;
383
384};
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391struct bau_desc {
392 struct pnmask distribution;
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396 union bau_msg_header {
397 struct uv1_bau_msg_header uv1_hdr;
398 struct uv2_bau_msg_header uv2_hdr;
399 } header;
400
401 struct bau_msg_payload payload;
402};
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435struct bau_pq_entry {
436 unsigned long address;
437
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439 unsigned short sending_cpu;
440
441 unsigned short acknowledge_count;
442
443
444 unsigned short replied_to:1;
445 unsigned short msg_type:3;
446 unsigned short canceled:1;
447 unsigned short unused1:3;
448
449 unsigned char unused2a;
450
451 unsigned char unused2;
452
453 unsigned char swack_vec;
454
455 unsigned short sequence;
456
457 unsigned char unused4[2];
458
459 int number_of_cpus;
460
461 unsigned char unused5[8];
462
463};
464
465struct msg_desc {
466 struct bau_pq_entry *msg;
467 int msg_slot;
468 struct bau_pq_entry *queue_first;
469 struct bau_pq_entry *queue_last;
470};
471
472struct reset_args {
473 int sender;
474};
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479struct ptc_stats {
480
481 unsigned long s_giveup;
482
483 unsigned long s_requestor;
484
485 unsigned long s_stimeout;
486 unsigned long s_dtimeout;
487 unsigned long s_strongnacks;
488 unsigned long s_time;
489 unsigned long s_retriesok;
490 unsigned long s_ntargcpu;
491
492 unsigned long s_ntargself;
493
494 unsigned long s_ntarglocals;
495
496 unsigned long s_ntargremotes;
497
498 unsigned long s_ntarglocaluvhub;
499 unsigned long s_ntargremoteuvhub;
500 unsigned long s_ntarguvhub;
501
502 unsigned long s_ntarguvhub16;
503
504 unsigned long s_ntarguvhub8;
505
506 unsigned long s_ntarguvhub4;
507
508 unsigned long s_ntarguvhub2;
509
510 unsigned long s_ntarguvhub1;
511
512 unsigned long s_resets_plug;
513
514 unsigned long s_resets_timeout;
515
516 unsigned long s_busy;
517
518 unsigned long s_throttles;
519 unsigned long s_retry_messages;
520 unsigned long s_bau_reenabled;
521 unsigned long s_bau_disabled;
522 unsigned long s_uv2_wars;
523 unsigned long s_uv2_wars_hw;
524 unsigned long s_uv2_war_waits;
525 unsigned long s_overipilimit;
526 unsigned long s_giveuplimit;
527 unsigned long s_enters;
528 unsigned long s_ipifordisabled;
529 unsigned long s_plugged;
530 unsigned long s_congested;
531
532 unsigned long d_alltlb;
533
534 unsigned long d_onetlb;
535
536 unsigned long d_multmsg;
537
538 unsigned long d_nomsg;
539 unsigned long d_time;
540
541 unsigned long d_requestee;
542
543 unsigned long d_retries;
544
545 unsigned long d_canceled;
546
547 unsigned long d_nocanceled;
548
549 unsigned long d_resets;
550
551 unsigned long d_rcanceled;
552
553};
554
555struct tunables {
556 int *tunp;
557 int deflt;
558};
559
560struct hub_and_pnode {
561 short uvhub;
562 short pnode;
563};
564
565struct socket_desc {
566 short num_cpus;
567 short cpu_number[MAX_CPUS_PER_SOCKET];
568};
569
570struct uvhub_desc {
571 unsigned short socket_mask;
572 short num_cpus;
573 short uvhub;
574 short pnode;
575 struct socket_desc socket[2];
576};
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581struct bau_control {
582 struct bau_desc *descriptor_base;
583 struct bau_pq_entry *queue_first;
584 struct bau_pq_entry *queue_last;
585 struct bau_pq_entry *bau_msg_head;
586 struct bau_control *uvhub_master;
587 struct bau_control *socket_master;
588 struct ptc_stats *statp;
589 cpumask_t *cpumask;
590 unsigned long timeout_interval;
591 unsigned long set_bau_on_time;
592 atomic_t active_descriptor_count;
593 int plugged_tries;
594 int timeout_tries;
595 int ipi_attempts;
596 int conseccompletes;
597 short nobau;
598 short baudisabled;
599 short cpu;
600 short osnode;
601 short uvhub_cpu;
602 short uvhub;
603 short uvhub_version;
604 short cpus_in_socket;
605 short cpus_in_uvhub;
606 short partition_base_pnode;
607 short busy;
608 unsigned short message_number;
609 unsigned short uvhub_quiesce;
610 short socket_acknowledge_count[DEST_Q_SIZE];
611 cycles_t send_message;
612 cycles_t period_end;
613 cycles_t period_time;
614 spinlock_t uvhub_lock;
615 spinlock_t queue_lock;
616 spinlock_t disable_lock;
617
618 int max_concurr;
619 int max_concurr_const;
620 int plugged_delay;
621 int plugsb4reset;
622 int timeoutsb4reset;
623 int ipi_reset_limit;
624 int complete_threshold;
625 int cong_response_us;
626 int cong_reps;
627 cycles_t disabled_period;
628 int period_giveups;
629 int giveup_limit;
630 long period_requests;
631 struct hub_and_pnode *thp;
632};
633
634static inline unsigned long read_mmr_uv2_status(void)
635{
636 return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
637}
638
639static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
640{
641 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
642}
643
644static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
645{
646 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
647}
648
649static inline void write_mmr_activation(unsigned long index)
650{
651 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
652}
653
654static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
655{
656 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
657}
658
659static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
660{
661 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
662}
663
664static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
665{
666 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
667}
668
669static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
670{
671 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
672}
673
674static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
675{
676 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
677}
678
679static inline unsigned long read_mmr_misc_control(int pnode)
680{
681 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
682}
683
684static inline void write_mmr_sw_ack(unsigned long mr)
685{
686 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
687}
688
689static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
690{
691 write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
692}
693
694static inline unsigned long read_mmr_sw_ack(void)
695{
696 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
697}
698
699static inline unsigned long read_gmmr_sw_ack(int pnode)
700{
701 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
702}
703
704static inline void write_mmr_data_config(int pnode, unsigned long mr)
705{
706 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
707}
708
709static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
710{
711 return constant_test_bit(uvhub, &dstp->bits[0]);
712}
713static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
714{
715 __set_bit(pnode, &dstp->bits[0]);
716}
717static inline void bau_uvhubs_clear(struct pnmask *dstp,
718 int nbits)
719{
720 bitmap_zero(&dstp->bits[0], nbits);
721}
722static inline int bau_uvhub_weight(struct pnmask *dstp)
723{
724 return bitmap_weight((unsigned long *)&dstp->bits[0],
725 UV_DISTRIBUTION_SIZE);
726}
727
728static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
729{
730 bitmap_zero(&dstp->bits, nbits);
731}
732
733extern void uv_bau_message_intr1(void);
734extern void uv_bau_timeout_intr1(void);
735
736struct atomic_short {
737 short counter;
738};
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746static inline int atomic_read_short(const struct atomic_short *v)
747{
748 return v->counter;
749}
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758static inline int atom_asr(short i, struct atomic_short *v)
759{
760 return i + xadd(&v->counter, i);
761}
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773static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
774{
775 spin_lock(lock);
776 if (atomic_read(v) >= u) {
777 spin_unlock(lock);
778 return 0;
779 }
780 atomic_inc(v);
781 spin_unlock(lock);
782 return 1;
783}
784
785#endif
786