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19#include "irq.h"
20#include "mmu.h"
21#include "cpuid.h"
22
23#include <linux/kvm_host.h>
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/mm.h>
27#include <linux/highmem.h>
28#include <linux/sched.h>
29#include <linux/moduleparam.h>
30#include <linux/mod_devicetable.h>
31#include <linux/ftrace_event.h>
32#include <linux/slab.h>
33#include <linux/tboot.h>
34#include "kvm_cache_regs.h"
35#include "x86.h"
36
37#include <asm/io.h>
38#include <asm/desc.h>
39#include <asm/vmx.h>
40#include <asm/virtext.h>
41#include <asm/mce.h>
42#include <asm/i387.h>
43#include <asm/xcr.h>
44#include <asm/perf_event.h>
45#include <asm/kexec.h>
46
47#include "trace.h"
48
49#define __ex(x) __kvm_handle_fault_on_reboot(x)
50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
52
53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
62static bool __read_mostly enable_vpid = 1;
63module_param_named(vpid, enable_vpid, bool, 0444);
64
65static bool __read_mostly flexpriority_enabled = 1;
66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
67
68static bool __read_mostly enable_ept = 1;
69module_param_named(ept, enable_ept, bool, S_IRUGO);
70
71static bool __read_mostly enable_unrestricted_guest = 1;
72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
78static bool __read_mostly emulate_invalid_guest_state = true;
79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
80
81static bool __read_mostly vmm_exclusive = 1;
82module_param(vmm_exclusive, bool, S_IRUGO);
83
84static bool __read_mostly fasteoi = 1;
85module_param(fasteoi, bool, S_IRUGO);
86
87static bool __read_mostly enable_apicv = 1;
88module_param(enable_apicv, bool, S_IRUGO);
89
90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
92
93
94
95
96
97static bool __read_mostly nested = 0;
98module_param(nested, bool, S_IRUGO);
99
100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
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123
124#define KVM_VMX_DEFAULT_PLE_GAP 128
125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
132extern const ulong vmx_return;
133
134#define NR_AUTOLOAD_MSRS 8
135#define VMCS02_POOL_SIZE 1
136
137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
143
144
145
146
147
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
158 u64 mask;
159};
160
161
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172
173
174typedef u64 natural_width;
175struct __packed vmcs12 {
176
177
178
179 u32 revision_id;
180 u32 abort;
181
182 u32 launch_state;
183 u32 padding[7];
184
185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8];
209
210
211
212
213
214
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8];
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
304 u32 vmx_preemption_timer_value;
305 u32 padding32[7];
306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
322};
323
324
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326
327
328
329#define VMCS12_REVISION 0x11e57ed0
330
331
332
333
334
335
336#define VMCS12_SIZE 0x1000
337
338
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
345
346
347
348
349struct nested_vmx {
350
351 bool vmxon;
352
353
354 gpa_t current_vmptr;
355
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
358 struct vmcs *current_shadow_vmcs;
359
360
361
362
363 bool sync_shadow_vmcs;
364
365
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
368 u64 vmcs01_tsc_offset;
369
370 bool nested_run_pending;
371
372
373
374
375 struct page *apic_access_page;
376};
377
378#define POSTED_INTR_ON 0
379
380struct pi_desc {
381 u32 pir[8];
382 u32 control;
383 u32 rsvd[7];
384} __aligned(64);
385
386static bool pi_test_and_set_on(struct pi_desc *pi_desc)
387{
388 return test_and_set_bit(POSTED_INTR_ON,
389 (unsigned long *)&pi_desc->control);
390}
391
392static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
393{
394 return test_and_clear_bit(POSTED_INTR_ON,
395 (unsigned long *)&pi_desc->control);
396}
397
398static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
399{
400 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
401}
402
403struct vcpu_vmx {
404 struct kvm_vcpu vcpu;
405 unsigned long host_rsp;
406 u8 fail;
407 u8 cpl;
408 bool nmi_known_unmasked;
409 u32 exit_intr_info;
410 u32 idt_vectoring_info;
411 ulong rflags;
412 struct shared_msr_entry *guest_msrs;
413 int nmsrs;
414 int save_nmsrs;
415 unsigned long host_idt_base;
416#ifdef CONFIG_X86_64
417 u64 msr_host_kernel_gs_base;
418 u64 msr_guest_kernel_gs_base;
419#endif
420
421
422
423
424
425 struct loaded_vmcs vmcs01;
426 struct loaded_vmcs *loaded_vmcs;
427 bool __launched;
428 struct msr_autoload {
429 unsigned nr;
430 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
431 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
432 } msr_autoload;
433 struct {
434 int loaded;
435 u16 fs_sel, gs_sel, ldt_sel;
436#ifdef CONFIG_X86_64
437 u16 ds_sel, es_sel;
438#endif
439 int gs_ldt_reload_needed;
440 int fs_reload_needed;
441 } host_state;
442 struct {
443 int vm86_active;
444 ulong save_rflags;
445 struct kvm_segment segs[8];
446 } rmode;
447 struct {
448 u32 bitmask;
449 struct kvm_save_segment {
450 u16 selector;
451 unsigned long base;
452 u32 limit;
453 u32 ar;
454 } seg[8];
455 } segment_cache;
456 int vpid;
457 bool emulation_required;
458
459
460 int soft_vnmi_blocked;
461 ktime_t entry_time;
462 s64 vnmi_blocked_time;
463 u32 exit_reason;
464
465 bool rdtscp_enabled;
466
467
468 struct pi_desc pi_desc;
469
470
471 struct nested_vmx nested;
472};
473
474enum segment_cache_field {
475 SEG_FIELD_SEL = 0,
476 SEG_FIELD_BASE = 1,
477 SEG_FIELD_LIMIT = 2,
478 SEG_FIELD_AR = 3,
479
480 SEG_FIELD_NR = 4
481};
482
483static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
484{
485 return container_of(vcpu, struct vcpu_vmx, vcpu);
486}
487
488#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
489#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
490#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
491 [number##_HIGH] = VMCS12_OFFSET(name)+4
492
493
494static const unsigned long shadow_read_only_fields[] = {
495
496
497
498
499
500
501
502
503
504
505
506
507 VM_EXIT_REASON,
508 VM_EXIT_INTR_INFO,
509 VM_EXIT_INSTRUCTION_LEN,
510 IDT_VECTORING_INFO_FIELD,
511 IDT_VECTORING_ERROR_CODE,
512 VM_EXIT_INTR_ERROR_CODE,
513 EXIT_QUALIFICATION,
514 GUEST_LINEAR_ADDRESS,
515 GUEST_PHYSICAL_ADDRESS
516};
517static const int max_shadow_read_only_fields =
518 ARRAY_SIZE(shadow_read_only_fields);
519
520static const unsigned long shadow_read_write_fields[] = {
521 GUEST_RIP,
522 GUEST_RSP,
523 GUEST_CR0,
524 GUEST_CR3,
525 GUEST_CR4,
526 GUEST_INTERRUPTIBILITY_INFO,
527 GUEST_RFLAGS,
528 GUEST_CS_SELECTOR,
529 GUEST_CS_AR_BYTES,
530 GUEST_CS_LIMIT,
531 GUEST_CS_BASE,
532 GUEST_ES_BASE,
533 CR0_GUEST_HOST_MASK,
534 CR0_READ_SHADOW,
535 CR4_READ_SHADOW,
536 TSC_OFFSET,
537 EXCEPTION_BITMAP,
538 CPU_BASED_VM_EXEC_CONTROL,
539 VM_ENTRY_EXCEPTION_ERROR_CODE,
540 VM_ENTRY_INTR_INFO_FIELD,
541 VM_ENTRY_INSTRUCTION_LEN,
542 VM_ENTRY_EXCEPTION_ERROR_CODE,
543 HOST_FS_BASE,
544 HOST_GS_BASE,
545 HOST_FS_SELECTOR,
546 HOST_GS_SELECTOR
547};
548static const int max_shadow_read_write_fields =
549 ARRAY_SIZE(shadow_read_write_fields);
550
551static const unsigned short vmcs_field_to_offset_table[] = {
552 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
553 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
554 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
555 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
556 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
557 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
558 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
559 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
560 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
561 FIELD(HOST_ES_SELECTOR, host_es_selector),
562 FIELD(HOST_CS_SELECTOR, host_cs_selector),
563 FIELD(HOST_SS_SELECTOR, host_ss_selector),
564 FIELD(HOST_DS_SELECTOR, host_ds_selector),
565 FIELD(HOST_FS_SELECTOR, host_fs_selector),
566 FIELD(HOST_GS_SELECTOR, host_gs_selector),
567 FIELD(HOST_TR_SELECTOR, host_tr_selector),
568 FIELD64(IO_BITMAP_A, io_bitmap_a),
569 FIELD64(IO_BITMAP_B, io_bitmap_b),
570 FIELD64(MSR_BITMAP, msr_bitmap),
571 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
572 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
573 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
574 FIELD64(TSC_OFFSET, tsc_offset),
575 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
576 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
577 FIELD64(EPT_POINTER, ept_pointer),
578 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
579 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
580 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
581 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
582 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
583 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
584 FIELD64(GUEST_PDPTR0, guest_pdptr0),
585 FIELD64(GUEST_PDPTR1, guest_pdptr1),
586 FIELD64(GUEST_PDPTR2, guest_pdptr2),
587 FIELD64(GUEST_PDPTR3, guest_pdptr3),
588 FIELD64(HOST_IA32_PAT, host_ia32_pat),
589 FIELD64(HOST_IA32_EFER, host_ia32_efer),
590 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
591 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
592 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
593 FIELD(EXCEPTION_BITMAP, exception_bitmap),
594 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
595 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
596 FIELD(CR3_TARGET_COUNT, cr3_target_count),
597 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
598 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
599 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
600 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
601 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
602 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
603 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
604 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
605 FIELD(TPR_THRESHOLD, tpr_threshold),
606 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
607 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
608 FIELD(VM_EXIT_REASON, vm_exit_reason),
609 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
610 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
611 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
612 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
613 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
614 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
615 FIELD(GUEST_ES_LIMIT, guest_es_limit),
616 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
617 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
618 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
619 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
620 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
621 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
622 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
623 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
624 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
625 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
626 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
627 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
628 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
629 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
630 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
631 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
632 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
633 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
634 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
635 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
636 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
637 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
638 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
639 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
640 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
641 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
642 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
643 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
644 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
645 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
646 FIELD(EXIT_QUALIFICATION, exit_qualification),
647 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
648 FIELD(GUEST_CR0, guest_cr0),
649 FIELD(GUEST_CR3, guest_cr3),
650 FIELD(GUEST_CR4, guest_cr4),
651 FIELD(GUEST_ES_BASE, guest_es_base),
652 FIELD(GUEST_CS_BASE, guest_cs_base),
653 FIELD(GUEST_SS_BASE, guest_ss_base),
654 FIELD(GUEST_DS_BASE, guest_ds_base),
655 FIELD(GUEST_FS_BASE, guest_fs_base),
656 FIELD(GUEST_GS_BASE, guest_gs_base),
657 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
658 FIELD(GUEST_TR_BASE, guest_tr_base),
659 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
660 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
661 FIELD(GUEST_DR7, guest_dr7),
662 FIELD(GUEST_RSP, guest_rsp),
663 FIELD(GUEST_RIP, guest_rip),
664 FIELD(GUEST_RFLAGS, guest_rflags),
665 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
666 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
667 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
668 FIELD(HOST_CR0, host_cr0),
669 FIELD(HOST_CR3, host_cr3),
670 FIELD(HOST_CR4, host_cr4),
671 FIELD(HOST_FS_BASE, host_fs_base),
672 FIELD(HOST_GS_BASE, host_gs_base),
673 FIELD(HOST_TR_BASE, host_tr_base),
674 FIELD(HOST_GDTR_BASE, host_gdtr_base),
675 FIELD(HOST_IDTR_BASE, host_idtr_base),
676 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
677 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
678 FIELD(HOST_RSP, host_rsp),
679 FIELD(HOST_RIP, host_rip),
680};
681static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
682
683static inline short vmcs_field_to_offset(unsigned long field)
684{
685 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
686 return -1;
687 return vmcs_field_to_offset_table[field];
688}
689
690static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
691{
692 return to_vmx(vcpu)->nested.current_vmcs12;
693}
694
695static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
696{
697 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
698 if (is_error_page(page))
699 return NULL;
700
701 return page;
702}
703
704static void nested_release_page(struct page *page)
705{
706 kvm_release_page_dirty(page);
707}
708
709static void nested_release_page_clean(struct page *page)
710{
711 kvm_release_page_clean(page);
712}
713
714static u64 construct_eptp(unsigned long root_hpa);
715static void kvm_cpu_vmxon(u64 addr);
716static void kvm_cpu_vmxoff(void);
717static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
718static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
719static void vmx_set_segment(struct kvm_vcpu *vcpu,
720 struct kvm_segment *var, int seg);
721static void vmx_get_segment(struct kvm_vcpu *vcpu,
722 struct kvm_segment *var, int seg);
723static bool guest_state_valid(struct kvm_vcpu *vcpu);
724static u32 vmx_segment_access_rights(struct kvm_segment *var);
725static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
726static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
727static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
728
729static DEFINE_PER_CPU(struct vmcs *, vmxarea);
730static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
731
732
733
734
735static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
736static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
737
738static unsigned long *vmx_io_bitmap_a;
739static unsigned long *vmx_io_bitmap_b;
740static unsigned long *vmx_msr_bitmap_legacy;
741static unsigned long *vmx_msr_bitmap_longmode;
742static unsigned long *vmx_msr_bitmap_legacy_x2apic;
743static unsigned long *vmx_msr_bitmap_longmode_x2apic;
744static unsigned long *vmx_vmread_bitmap;
745static unsigned long *vmx_vmwrite_bitmap;
746
747static bool cpu_has_load_ia32_efer;
748static bool cpu_has_load_perf_global_ctrl;
749
750static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
751static DEFINE_SPINLOCK(vmx_vpid_lock);
752
753static struct vmcs_config {
754 int size;
755 int order;
756 u32 revision_id;
757 u32 pin_based_exec_ctrl;
758 u32 cpu_based_exec_ctrl;
759 u32 cpu_based_2nd_exec_ctrl;
760 u32 vmexit_ctrl;
761 u32 vmentry_ctrl;
762} vmcs_config;
763
764static struct vmx_capability {
765 u32 ept;
766 u32 vpid;
767} vmx_capability;
768
769#define VMX_SEGMENT_FIELD(seg) \
770 [VCPU_SREG_##seg] = { \
771 .selector = GUEST_##seg##_SELECTOR, \
772 .base = GUEST_##seg##_BASE, \
773 .limit = GUEST_##seg##_LIMIT, \
774 .ar_bytes = GUEST_##seg##_AR_BYTES, \
775 }
776
777static const struct kvm_vmx_segment_field {
778 unsigned selector;
779 unsigned base;
780 unsigned limit;
781 unsigned ar_bytes;
782} kvm_vmx_segment_fields[] = {
783 VMX_SEGMENT_FIELD(CS),
784 VMX_SEGMENT_FIELD(DS),
785 VMX_SEGMENT_FIELD(ES),
786 VMX_SEGMENT_FIELD(FS),
787 VMX_SEGMENT_FIELD(GS),
788 VMX_SEGMENT_FIELD(SS),
789 VMX_SEGMENT_FIELD(TR),
790 VMX_SEGMENT_FIELD(LDTR),
791};
792
793static u64 host_efer;
794
795static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
796
797
798
799
800
801static const u32 vmx_msr_index[] = {
802#ifdef CONFIG_X86_64
803 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
804#endif
805 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
806};
807#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
808
809static inline bool is_page_fault(u32 intr_info)
810{
811 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
812 INTR_INFO_VALID_MASK)) ==
813 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
814}
815
816static inline bool is_no_device(u32 intr_info)
817{
818 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
819 INTR_INFO_VALID_MASK)) ==
820 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
821}
822
823static inline bool is_invalid_opcode(u32 intr_info)
824{
825 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
826 INTR_INFO_VALID_MASK)) ==
827 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
828}
829
830static inline bool is_external_interrupt(u32 intr_info)
831{
832 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
833 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
834}
835
836static inline bool is_machine_check(u32 intr_info)
837{
838 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
839 INTR_INFO_VALID_MASK)) ==
840 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
841}
842
843static inline bool cpu_has_vmx_msr_bitmap(void)
844{
845 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
846}
847
848static inline bool cpu_has_vmx_tpr_shadow(void)
849{
850 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
851}
852
853static inline bool vm_need_tpr_shadow(struct kvm *kvm)
854{
855 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
856}
857
858static inline bool cpu_has_secondary_exec_ctrls(void)
859{
860 return vmcs_config.cpu_based_exec_ctrl &
861 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
862}
863
864static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
865{
866 return vmcs_config.cpu_based_2nd_exec_ctrl &
867 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
868}
869
870static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
871{
872 return vmcs_config.cpu_based_2nd_exec_ctrl &
873 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
874}
875
876static inline bool cpu_has_vmx_apic_register_virt(void)
877{
878 return vmcs_config.cpu_based_2nd_exec_ctrl &
879 SECONDARY_EXEC_APIC_REGISTER_VIRT;
880}
881
882static inline bool cpu_has_vmx_virtual_intr_delivery(void)
883{
884 return vmcs_config.cpu_based_2nd_exec_ctrl &
885 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
886}
887
888static inline bool cpu_has_vmx_posted_intr(void)
889{
890 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
891}
892
893static inline bool cpu_has_vmx_apicv(void)
894{
895 return cpu_has_vmx_apic_register_virt() &&
896 cpu_has_vmx_virtual_intr_delivery() &&
897 cpu_has_vmx_posted_intr();
898}
899
900static inline bool cpu_has_vmx_flexpriority(void)
901{
902 return cpu_has_vmx_tpr_shadow() &&
903 cpu_has_vmx_virtualize_apic_accesses();
904}
905
906static inline bool cpu_has_vmx_ept_execute_only(void)
907{
908 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
909}
910
911static inline bool cpu_has_vmx_eptp_uncacheable(void)
912{
913 return vmx_capability.ept & VMX_EPTP_UC_BIT;
914}
915
916static inline bool cpu_has_vmx_eptp_writeback(void)
917{
918 return vmx_capability.ept & VMX_EPTP_WB_BIT;
919}
920
921static inline bool cpu_has_vmx_ept_2m_page(void)
922{
923 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
924}
925
926static inline bool cpu_has_vmx_ept_1g_page(void)
927{
928 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
929}
930
931static inline bool cpu_has_vmx_ept_4levels(void)
932{
933 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
934}
935
936static inline bool cpu_has_vmx_ept_ad_bits(void)
937{
938 return vmx_capability.ept & VMX_EPT_AD_BIT;
939}
940
941static inline bool cpu_has_vmx_invept_context(void)
942{
943 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
944}
945
946static inline bool cpu_has_vmx_invept_global(void)
947{
948 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
949}
950
951static inline bool cpu_has_vmx_invvpid_single(void)
952{
953 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
954}
955
956static inline bool cpu_has_vmx_invvpid_global(void)
957{
958 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
959}
960
961static inline bool cpu_has_vmx_ept(void)
962{
963 return vmcs_config.cpu_based_2nd_exec_ctrl &
964 SECONDARY_EXEC_ENABLE_EPT;
965}
966
967static inline bool cpu_has_vmx_unrestricted_guest(void)
968{
969 return vmcs_config.cpu_based_2nd_exec_ctrl &
970 SECONDARY_EXEC_UNRESTRICTED_GUEST;
971}
972
973static inline bool cpu_has_vmx_ple(void)
974{
975 return vmcs_config.cpu_based_2nd_exec_ctrl &
976 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
977}
978
979static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
980{
981 return flexpriority_enabled && irqchip_in_kernel(kvm);
982}
983
984static inline bool cpu_has_vmx_vpid(void)
985{
986 return vmcs_config.cpu_based_2nd_exec_ctrl &
987 SECONDARY_EXEC_ENABLE_VPID;
988}
989
990static inline bool cpu_has_vmx_rdtscp(void)
991{
992 return vmcs_config.cpu_based_2nd_exec_ctrl &
993 SECONDARY_EXEC_RDTSCP;
994}
995
996static inline bool cpu_has_vmx_invpcid(void)
997{
998 return vmcs_config.cpu_based_2nd_exec_ctrl &
999 SECONDARY_EXEC_ENABLE_INVPCID;
1000}
1001
1002static inline bool cpu_has_virtual_nmis(void)
1003{
1004 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1005}
1006
1007static inline bool cpu_has_vmx_wbinvd_exit(void)
1008{
1009 return vmcs_config.cpu_based_2nd_exec_ctrl &
1010 SECONDARY_EXEC_WBINVD_EXITING;
1011}
1012
1013static inline bool cpu_has_vmx_shadow_vmcs(void)
1014{
1015 u64 vmx_msr;
1016 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1017
1018 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1019 return false;
1020
1021 return vmcs_config.cpu_based_2nd_exec_ctrl &
1022 SECONDARY_EXEC_SHADOW_VMCS;
1023}
1024
1025static inline bool report_flexpriority(void)
1026{
1027 return flexpriority_enabled;
1028}
1029
1030static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1031{
1032 return vmcs12->cpu_based_vm_exec_control & bit;
1033}
1034
1035static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1036{
1037 return (vmcs12->cpu_based_vm_exec_control &
1038 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1039 (vmcs12->secondary_vm_exec_control & bit);
1040}
1041
1042static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1043 struct kvm_vcpu *vcpu)
1044{
1045 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046}
1047
1048static inline bool is_exception(u32 intr_info)
1049{
1050 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1051 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1052}
1053
1054static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1055static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1056 struct vmcs12 *vmcs12,
1057 u32 reason, unsigned long qualification);
1058
1059static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1060{
1061 int i;
1062
1063 for (i = 0; i < vmx->nmsrs; ++i)
1064 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1065 return i;
1066 return -1;
1067}
1068
1069static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1070{
1071 struct {
1072 u64 vpid : 16;
1073 u64 rsvd : 48;
1074 u64 gva;
1075 } operand = { vpid, 0, gva };
1076
1077 asm volatile (__ex(ASM_VMX_INVVPID)
1078
1079 "; ja 1f ; ud2 ; 1:"
1080 : : "a"(&operand), "c"(ext) : "cc", "memory");
1081}
1082
1083static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1084{
1085 struct {
1086 u64 eptp, gpa;
1087 } operand = {eptp, gpa};
1088
1089 asm volatile (__ex(ASM_VMX_INVEPT)
1090
1091 "; ja 1f ; ud2 ; 1:\n"
1092 : : "a" (&operand), "c" (ext) : "cc", "memory");
1093}
1094
1095static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1096{
1097 int i;
1098
1099 i = __find_msr_index(vmx, msr);
1100 if (i >= 0)
1101 return &vmx->guest_msrs[i];
1102 return NULL;
1103}
1104
1105static void vmcs_clear(struct vmcs *vmcs)
1106{
1107 u64 phys_addr = __pa(vmcs);
1108 u8 error;
1109
1110 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1111 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1112 : "cc", "memory");
1113 if (error)
1114 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1115 vmcs, phys_addr);
1116}
1117
1118static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1119{
1120 vmcs_clear(loaded_vmcs->vmcs);
1121 loaded_vmcs->cpu = -1;
1122 loaded_vmcs->launched = 0;
1123}
1124
1125static void vmcs_load(struct vmcs *vmcs)
1126{
1127 u64 phys_addr = __pa(vmcs);
1128 u8 error;
1129
1130 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1131 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1132 : "cc", "memory");
1133 if (error)
1134 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1135 vmcs, phys_addr);
1136}
1137
1138#ifdef CONFIG_KEXEC
1139
1140
1141
1142
1143
1144static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1145
1146static inline void crash_enable_local_vmclear(int cpu)
1147{
1148 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1149}
1150
1151static inline void crash_disable_local_vmclear(int cpu)
1152{
1153 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154}
1155
1156static inline int crash_local_vmclear_enabled(int cpu)
1157{
1158 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159}
1160
1161static void crash_vmclear_local_loaded_vmcss(void)
1162{
1163 int cpu = raw_smp_processor_id();
1164 struct loaded_vmcs *v;
1165
1166 if (!crash_local_vmclear_enabled(cpu))
1167 return;
1168
1169 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1170 loaded_vmcss_on_cpu_link)
1171 vmcs_clear(v->vmcs);
1172}
1173#else
1174static inline void crash_enable_local_vmclear(int cpu) { }
1175static inline void crash_disable_local_vmclear(int cpu) { }
1176#endif
1177
1178static void __loaded_vmcs_clear(void *arg)
1179{
1180 struct loaded_vmcs *loaded_vmcs = arg;
1181 int cpu = raw_smp_processor_id();
1182
1183 if (loaded_vmcs->cpu != cpu)
1184 return;
1185 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1186 per_cpu(current_vmcs, cpu) = NULL;
1187 crash_disable_local_vmclear(cpu);
1188 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1189
1190
1191
1192
1193
1194
1195
1196 smp_wmb();
1197
1198 loaded_vmcs_init(loaded_vmcs);
1199 crash_enable_local_vmclear(cpu);
1200}
1201
1202static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1203{
1204 int cpu = loaded_vmcs->cpu;
1205
1206 if (cpu != -1)
1207 smp_call_function_single(cpu,
1208 __loaded_vmcs_clear, loaded_vmcs, 1);
1209}
1210
1211static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1212{
1213 if (vmx->vpid == 0)
1214 return;
1215
1216 if (cpu_has_vmx_invvpid_single())
1217 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1218}
1219
1220static inline void vpid_sync_vcpu_global(void)
1221{
1222 if (cpu_has_vmx_invvpid_global())
1223 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1224}
1225
1226static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1227{
1228 if (cpu_has_vmx_invvpid_single())
1229 vpid_sync_vcpu_single(vmx);
1230 else
1231 vpid_sync_vcpu_global();
1232}
1233
1234static inline void ept_sync_global(void)
1235{
1236 if (cpu_has_vmx_invept_global())
1237 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1238}
1239
1240static inline void ept_sync_context(u64 eptp)
1241{
1242 if (enable_ept) {
1243 if (cpu_has_vmx_invept_context())
1244 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1245 else
1246 ept_sync_global();
1247 }
1248}
1249
1250static __always_inline unsigned long vmcs_readl(unsigned long field)
1251{
1252 unsigned long value;
1253
1254 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1255 : "=a"(value) : "d"(field) : "cc");
1256 return value;
1257}
1258
1259static __always_inline u16 vmcs_read16(unsigned long field)
1260{
1261 return vmcs_readl(field);
1262}
1263
1264static __always_inline u32 vmcs_read32(unsigned long field)
1265{
1266 return vmcs_readl(field);
1267}
1268
1269static __always_inline u64 vmcs_read64(unsigned long field)
1270{
1271#ifdef CONFIG_X86_64
1272 return vmcs_readl(field);
1273#else
1274 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1275#endif
1276}
1277
1278static noinline void vmwrite_error(unsigned long field, unsigned long value)
1279{
1280 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1281 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1282 dump_stack();
1283}
1284
1285static void vmcs_writel(unsigned long field, unsigned long value)
1286{
1287 u8 error;
1288
1289 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1290 : "=q"(error) : "a"(value), "d"(field) : "cc");
1291 if (unlikely(error))
1292 vmwrite_error(field, value);
1293}
1294
1295static void vmcs_write16(unsigned long field, u16 value)
1296{
1297 vmcs_writel(field, value);
1298}
1299
1300static void vmcs_write32(unsigned long field, u32 value)
1301{
1302 vmcs_writel(field, value);
1303}
1304
1305static void vmcs_write64(unsigned long field, u64 value)
1306{
1307 vmcs_writel(field, value);
1308#ifndef CONFIG_X86_64
1309 asm volatile ("");
1310 vmcs_writel(field+1, value >> 32);
1311#endif
1312}
1313
1314static void vmcs_clear_bits(unsigned long field, u32 mask)
1315{
1316 vmcs_writel(field, vmcs_readl(field) & ~mask);
1317}
1318
1319static void vmcs_set_bits(unsigned long field, u32 mask)
1320{
1321 vmcs_writel(field, vmcs_readl(field) | mask);
1322}
1323
1324static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1325{
1326 vmx->segment_cache.bitmask = 0;
1327}
1328
1329static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1330 unsigned field)
1331{
1332 bool ret;
1333 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1334
1335 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1336 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1337 vmx->segment_cache.bitmask = 0;
1338 }
1339 ret = vmx->segment_cache.bitmask & mask;
1340 vmx->segment_cache.bitmask |= mask;
1341 return ret;
1342}
1343
1344static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1345{
1346 u16 *p = &vmx->segment_cache.seg[seg].selector;
1347
1348 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1349 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1350 return *p;
1351}
1352
1353static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1354{
1355 ulong *p = &vmx->segment_cache.seg[seg].base;
1356
1357 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1358 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1359 return *p;
1360}
1361
1362static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1363{
1364 u32 *p = &vmx->segment_cache.seg[seg].limit;
1365
1366 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1367 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1368 return *p;
1369}
1370
1371static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1372{
1373 u32 *p = &vmx->segment_cache.seg[seg].ar;
1374
1375 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1376 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1377 return *p;
1378}
1379
1380static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1381{
1382 u32 eb;
1383
1384 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1385 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1386 if ((vcpu->guest_debug &
1387 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1388 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1389 eb |= 1u << BP_VECTOR;
1390 if (to_vmx(vcpu)->rmode.vm86_active)
1391 eb = ~0;
1392 if (enable_ept)
1393 eb &= ~(1u << PF_VECTOR);
1394 if (vcpu->fpu_active)
1395 eb &= ~(1u << NM_VECTOR);
1396
1397
1398
1399
1400
1401
1402 if (is_guest_mode(vcpu))
1403 eb |= get_vmcs12(vcpu)->exception_bitmap;
1404
1405 vmcs_write32(EXCEPTION_BITMAP, eb);
1406}
1407
1408static void clear_atomic_switch_msr_special(unsigned long entry,
1409 unsigned long exit)
1410{
1411 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1412 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1413}
1414
1415static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1416{
1417 unsigned i;
1418 struct msr_autoload *m = &vmx->msr_autoload;
1419
1420 switch (msr) {
1421 case MSR_EFER:
1422 if (cpu_has_load_ia32_efer) {
1423 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1424 VM_EXIT_LOAD_IA32_EFER);
1425 return;
1426 }
1427 break;
1428 case MSR_CORE_PERF_GLOBAL_CTRL:
1429 if (cpu_has_load_perf_global_ctrl) {
1430 clear_atomic_switch_msr_special(
1431 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1432 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1433 return;
1434 }
1435 break;
1436 }
1437
1438 for (i = 0; i < m->nr; ++i)
1439 if (m->guest[i].index == msr)
1440 break;
1441
1442 if (i == m->nr)
1443 return;
1444 --m->nr;
1445 m->guest[i] = m->guest[m->nr];
1446 m->host[i] = m->host[m->nr];
1447 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1448 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1449}
1450
1451static void add_atomic_switch_msr_special(unsigned long entry,
1452 unsigned long exit, unsigned long guest_val_vmcs,
1453 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1454{
1455 vmcs_write64(guest_val_vmcs, guest_val);
1456 vmcs_write64(host_val_vmcs, host_val);
1457 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1458 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1459}
1460
1461static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1462 u64 guest_val, u64 host_val)
1463{
1464 unsigned i;
1465 struct msr_autoload *m = &vmx->msr_autoload;
1466
1467 switch (msr) {
1468 case MSR_EFER:
1469 if (cpu_has_load_ia32_efer) {
1470 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1471 VM_EXIT_LOAD_IA32_EFER,
1472 GUEST_IA32_EFER,
1473 HOST_IA32_EFER,
1474 guest_val, host_val);
1475 return;
1476 }
1477 break;
1478 case MSR_CORE_PERF_GLOBAL_CTRL:
1479 if (cpu_has_load_perf_global_ctrl) {
1480 add_atomic_switch_msr_special(
1481 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1482 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1483 GUEST_IA32_PERF_GLOBAL_CTRL,
1484 HOST_IA32_PERF_GLOBAL_CTRL,
1485 guest_val, host_val);
1486 return;
1487 }
1488 break;
1489 }
1490
1491 for (i = 0; i < m->nr; ++i)
1492 if (m->guest[i].index == msr)
1493 break;
1494
1495 if (i == NR_AUTOLOAD_MSRS) {
1496 printk_once(KERN_WARNING"Not enough mst switch entries. "
1497 "Can't add msr %x\n", msr);
1498 return;
1499 } else if (i == m->nr) {
1500 ++m->nr;
1501 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1502 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1503 }
1504
1505 m->guest[i].index = msr;
1506 m->guest[i].value = guest_val;
1507 m->host[i].index = msr;
1508 m->host[i].value = host_val;
1509}
1510
1511static void reload_tss(void)
1512{
1513
1514
1515
1516 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1517 struct desc_struct *descs;
1518
1519 descs = (void *)gdt->address;
1520 descs[GDT_ENTRY_TSS].type = 9;
1521 load_TR_desc();
1522}
1523
1524static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1525{
1526 u64 guest_efer;
1527 u64 ignore_bits;
1528
1529 guest_efer = vmx->vcpu.arch.efer;
1530
1531
1532
1533
1534
1535 ignore_bits = EFER_NX | EFER_SCE;
1536#ifdef CONFIG_X86_64
1537 ignore_bits |= EFER_LMA | EFER_LME;
1538
1539 if (guest_efer & EFER_LMA)
1540 ignore_bits &= ~(u64)EFER_SCE;
1541#endif
1542 guest_efer &= ~ignore_bits;
1543 guest_efer |= host_efer & ignore_bits;
1544 vmx->guest_msrs[efer_offset].data = guest_efer;
1545 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1546
1547 clear_atomic_switch_msr(vmx, MSR_EFER);
1548
1549 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1550 guest_efer = vmx->vcpu.arch.efer;
1551 if (!(guest_efer & EFER_LMA))
1552 guest_efer &= ~EFER_LME;
1553 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1554 return false;
1555 }
1556
1557 return true;
1558}
1559
1560static unsigned long segment_base(u16 selector)
1561{
1562 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1563 struct desc_struct *d;
1564 unsigned long table_base;
1565 unsigned long v;
1566
1567 if (!(selector & ~3))
1568 return 0;
1569
1570 table_base = gdt->address;
1571
1572 if (selector & 4) {
1573 u16 ldt_selector = kvm_read_ldt();
1574
1575 if (!(ldt_selector & ~3))
1576 return 0;
1577
1578 table_base = segment_base(ldt_selector);
1579 }
1580 d = (struct desc_struct *)(table_base + (selector & ~7));
1581 v = get_desc_base(d);
1582#ifdef CONFIG_X86_64
1583 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1584 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1585#endif
1586 return v;
1587}
1588
1589static inline unsigned long kvm_read_tr_base(void)
1590{
1591 u16 tr;
1592 asm("str %0" : "=g"(tr));
1593 return segment_base(tr);
1594}
1595
1596static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1597{
1598 struct vcpu_vmx *vmx = to_vmx(vcpu);
1599 int i;
1600
1601 if (vmx->host_state.loaded)
1602 return;
1603
1604 vmx->host_state.loaded = 1;
1605
1606
1607
1608
1609 vmx->host_state.ldt_sel = kvm_read_ldt();
1610 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1611 savesegment(fs, vmx->host_state.fs_sel);
1612 if (!(vmx->host_state.fs_sel & 7)) {
1613 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1614 vmx->host_state.fs_reload_needed = 0;
1615 } else {
1616 vmcs_write16(HOST_FS_SELECTOR, 0);
1617 vmx->host_state.fs_reload_needed = 1;
1618 }
1619 savesegment(gs, vmx->host_state.gs_sel);
1620 if (!(vmx->host_state.gs_sel & 7))
1621 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1622 else {
1623 vmcs_write16(HOST_GS_SELECTOR, 0);
1624 vmx->host_state.gs_ldt_reload_needed = 1;
1625 }
1626
1627#ifdef CONFIG_X86_64
1628 savesegment(ds, vmx->host_state.ds_sel);
1629 savesegment(es, vmx->host_state.es_sel);
1630#endif
1631
1632#ifdef CONFIG_X86_64
1633 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1634 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1635#else
1636 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1637 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1638#endif
1639
1640#ifdef CONFIG_X86_64
1641 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1642 if (is_long_mode(&vmx->vcpu))
1643 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1644#endif
1645 for (i = 0; i < vmx->save_nmsrs; ++i)
1646 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1647 vmx->guest_msrs[i].data,
1648 vmx->guest_msrs[i].mask);
1649}
1650
1651static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1652{
1653 if (!vmx->host_state.loaded)
1654 return;
1655
1656 ++vmx->vcpu.stat.host_state_reload;
1657 vmx->host_state.loaded = 0;
1658#ifdef CONFIG_X86_64
1659 if (is_long_mode(&vmx->vcpu))
1660 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1661#endif
1662 if (vmx->host_state.gs_ldt_reload_needed) {
1663 kvm_load_ldt(vmx->host_state.ldt_sel);
1664#ifdef CONFIG_X86_64
1665 load_gs_index(vmx->host_state.gs_sel);
1666#else
1667 loadsegment(gs, vmx->host_state.gs_sel);
1668#endif
1669 }
1670 if (vmx->host_state.fs_reload_needed)
1671 loadsegment(fs, vmx->host_state.fs_sel);
1672#ifdef CONFIG_X86_64
1673 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1674 loadsegment(ds, vmx->host_state.ds_sel);
1675 loadsegment(es, vmx->host_state.es_sel);
1676 }
1677#endif
1678 reload_tss();
1679#ifdef CONFIG_X86_64
1680 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1681#endif
1682
1683
1684
1685
1686 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1687 stts();
1688 load_gdt(&__get_cpu_var(host_gdt));
1689}
1690
1691static void vmx_load_host_state(struct vcpu_vmx *vmx)
1692{
1693 preempt_disable();
1694 __vmx_load_host_state(vmx);
1695 preempt_enable();
1696}
1697
1698
1699
1700
1701
1702static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1703{
1704 struct vcpu_vmx *vmx = to_vmx(vcpu);
1705 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1706
1707 if (!vmm_exclusive)
1708 kvm_cpu_vmxon(phys_addr);
1709 else if (vmx->loaded_vmcs->cpu != cpu)
1710 loaded_vmcs_clear(vmx->loaded_vmcs);
1711
1712 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1713 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1714 vmcs_load(vmx->loaded_vmcs->vmcs);
1715 }
1716
1717 if (vmx->loaded_vmcs->cpu != cpu) {
1718 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1719 unsigned long sysenter_esp;
1720
1721 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1722 local_irq_disable();
1723 crash_disable_local_vmclear(cpu);
1724
1725
1726
1727
1728
1729
1730 smp_rmb();
1731
1732 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1733 &per_cpu(loaded_vmcss_on_cpu, cpu));
1734 crash_enable_local_vmclear(cpu);
1735 local_irq_enable();
1736
1737
1738
1739
1740
1741 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base());
1742 vmcs_writel(HOST_GDTR_BASE, gdt->address);
1743
1744 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1745 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp);
1746 vmx->loaded_vmcs->cpu = cpu;
1747 }
1748}
1749
1750static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1751{
1752 __vmx_load_host_state(to_vmx(vcpu));
1753 if (!vmm_exclusive) {
1754 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1755 vcpu->cpu = -1;
1756 kvm_cpu_vmxoff();
1757 }
1758}
1759
1760static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1761{
1762 ulong cr0;
1763
1764 if (vcpu->fpu_active)
1765 return;
1766 vcpu->fpu_active = 1;
1767 cr0 = vmcs_readl(GUEST_CR0);
1768 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1769 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1770 vmcs_writel(GUEST_CR0, cr0);
1771 update_exception_bitmap(vcpu);
1772 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1773 if (is_guest_mode(vcpu))
1774 vcpu->arch.cr0_guest_owned_bits &=
1775 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1776 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1777}
1778
1779static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1780
1781
1782
1783
1784
1785
1786static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1787{
1788 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1789 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1790}
1791static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1792{
1793 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1794 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1795}
1796
1797static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1798{
1799
1800
1801
1802 vmx_decache_cr0_guest_bits(vcpu);
1803 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1804 update_exception_bitmap(vcpu);
1805 vcpu->arch.cr0_guest_owned_bits = 0;
1806 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1807 if (is_guest_mode(vcpu)) {
1808
1809
1810
1811
1812
1813
1814
1815
1816 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1817 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1818 (vcpu->arch.cr0 & X86_CR0_TS);
1819 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1820 } else
1821 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1822}
1823
1824static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1825{
1826 unsigned long rflags, save_rflags;
1827
1828 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1829 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1830 rflags = vmcs_readl(GUEST_RFLAGS);
1831 if (to_vmx(vcpu)->rmode.vm86_active) {
1832 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1833 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1834 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1835 }
1836 to_vmx(vcpu)->rflags = rflags;
1837 }
1838 return to_vmx(vcpu)->rflags;
1839}
1840
1841static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1842{
1843 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1844 to_vmx(vcpu)->rflags = rflags;
1845 if (to_vmx(vcpu)->rmode.vm86_active) {
1846 to_vmx(vcpu)->rmode.save_rflags = rflags;
1847 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1848 }
1849 vmcs_writel(GUEST_RFLAGS, rflags);
1850}
1851
1852static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1853{
1854 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1855 int ret = 0;
1856
1857 if (interruptibility & GUEST_INTR_STATE_STI)
1858 ret |= KVM_X86_SHADOW_INT_STI;
1859 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1860 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1861
1862 return ret & mask;
1863}
1864
1865static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1866{
1867 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1868 u32 interruptibility = interruptibility_old;
1869
1870 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1871
1872 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1873 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1874 else if (mask & KVM_X86_SHADOW_INT_STI)
1875 interruptibility |= GUEST_INTR_STATE_STI;
1876
1877 if ((interruptibility != interruptibility_old))
1878 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1879}
1880
1881static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1882{
1883 unsigned long rip;
1884
1885 rip = kvm_rip_read(vcpu);
1886 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1887 kvm_rip_write(vcpu, rip);
1888
1889
1890 vmx_set_interrupt_shadow(vcpu, 0);
1891}
1892
1893
1894
1895
1896
1897
1898
1899
1900static int nested_pf_handled(struct kvm_vcpu *vcpu)
1901{
1902 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1903
1904
1905 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1906 return 0;
1907
1908 nested_vmx_vmexit(vcpu);
1909 return 1;
1910}
1911
1912static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1913 bool has_error_code, u32 error_code,
1914 bool reinject)
1915{
1916 struct vcpu_vmx *vmx = to_vmx(vcpu);
1917 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1918
1919 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1920 !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
1921 return;
1922
1923 if (has_error_code) {
1924 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1925 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1926 }
1927
1928 if (vmx->rmode.vm86_active) {
1929 int inc_eip = 0;
1930 if (kvm_exception_is_soft(nr))
1931 inc_eip = vcpu->arch.event_exit_inst_len;
1932 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1933 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1934 return;
1935 }
1936
1937 if (kvm_exception_is_soft(nr)) {
1938 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1939 vmx->vcpu.arch.event_exit_inst_len);
1940 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1941 } else
1942 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1943
1944 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1945}
1946
1947static bool vmx_rdtscp_supported(void)
1948{
1949 return cpu_has_vmx_rdtscp();
1950}
1951
1952static bool vmx_invpcid_supported(void)
1953{
1954 return cpu_has_vmx_invpcid() && enable_ept;
1955}
1956
1957
1958
1959
1960static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1961{
1962 struct shared_msr_entry tmp;
1963
1964 tmp = vmx->guest_msrs[to];
1965 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1966 vmx->guest_msrs[from] = tmp;
1967}
1968
1969static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1970{
1971 unsigned long *msr_bitmap;
1972
1973 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1974 if (is_long_mode(vcpu))
1975 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1976 else
1977 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1978 } else {
1979 if (is_long_mode(vcpu))
1980 msr_bitmap = vmx_msr_bitmap_longmode;
1981 else
1982 msr_bitmap = vmx_msr_bitmap_legacy;
1983 }
1984
1985 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1986}
1987
1988
1989
1990
1991
1992
1993static void setup_msrs(struct vcpu_vmx *vmx)
1994{
1995 int save_nmsrs, index;
1996
1997 save_nmsrs = 0;
1998#ifdef CONFIG_X86_64
1999 if (is_long_mode(&vmx->vcpu)) {
2000 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2001 if (index >= 0)
2002 move_msr_up(vmx, index, save_nmsrs++);
2003 index = __find_msr_index(vmx, MSR_LSTAR);
2004 if (index >= 0)
2005 move_msr_up(vmx, index, save_nmsrs++);
2006 index = __find_msr_index(vmx, MSR_CSTAR);
2007 if (index >= 0)
2008 move_msr_up(vmx, index, save_nmsrs++);
2009 index = __find_msr_index(vmx, MSR_TSC_AUX);
2010 if (index >= 0 && vmx->rdtscp_enabled)
2011 move_msr_up(vmx, index, save_nmsrs++);
2012
2013
2014
2015
2016 index = __find_msr_index(vmx, MSR_STAR);
2017 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2018 move_msr_up(vmx, index, save_nmsrs++);
2019 }
2020#endif
2021 index = __find_msr_index(vmx, MSR_EFER);
2022 if (index >= 0 && update_transition_efer(vmx, index))
2023 move_msr_up(vmx, index, save_nmsrs++);
2024
2025 vmx->save_nmsrs = save_nmsrs;
2026
2027 if (cpu_has_vmx_msr_bitmap())
2028 vmx_set_msr_bitmap(&vmx->vcpu);
2029}
2030
2031
2032
2033
2034
2035static u64 guest_read_tsc(void)
2036{
2037 u64 host_tsc, tsc_offset;
2038
2039 rdtscll(host_tsc);
2040 tsc_offset = vmcs_read64(TSC_OFFSET);
2041 return host_tsc + tsc_offset;
2042}
2043
2044
2045
2046
2047
2048u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2049{
2050 u64 tsc_offset;
2051
2052 tsc_offset = is_guest_mode(vcpu) ?
2053 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2054 vmcs_read64(TSC_OFFSET);
2055 return host_tsc + tsc_offset;
2056}
2057
2058
2059
2060
2061
2062static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2063{
2064 if (!scale)
2065 return;
2066
2067 if (user_tsc_khz > tsc_khz) {
2068 vcpu->arch.tsc_catchup = 1;
2069 vcpu->arch.tsc_always_catchup = 1;
2070 } else
2071 WARN(1, "user requested TSC rate below hardware speed\n");
2072}
2073
2074static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2075{
2076 return vmcs_read64(TSC_OFFSET);
2077}
2078
2079
2080
2081
2082static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2083{
2084 if (is_guest_mode(vcpu)) {
2085
2086
2087
2088
2089
2090
2091 struct vmcs12 *vmcs12;
2092 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2093
2094 vmcs12 = get_vmcs12(vcpu);
2095 vmcs_write64(TSC_OFFSET, offset +
2096 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2097 vmcs12->tsc_offset : 0));
2098 } else {
2099 vmcs_write64(TSC_OFFSET, offset);
2100 }
2101}
2102
2103static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2104{
2105 u64 offset = vmcs_read64(TSC_OFFSET);
2106 vmcs_write64(TSC_OFFSET, offset + adjustment);
2107 if (is_guest_mode(vcpu)) {
2108
2109 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2110 }
2111}
2112
2113static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2114{
2115 return target_tsc - native_read_tsc();
2116}
2117
2118static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2119{
2120 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2121 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2122}
2123
2124
2125
2126
2127
2128
2129
2130static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2131{
2132 return nested && guest_cpuid_has_vmx(vcpu);
2133}
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2148static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2149static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2150static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2151static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2152static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2153static __init void nested_vmx_setup_ctls_msrs(void)
2154{
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2172 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2173
2174
2175
2176
2177 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2178 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2179 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2180 PIN_BASED_VMX_PREEMPTION_TIMER;
2181 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2182
2183
2184
2185
2186
2187
2188 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2189
2190#ifdef CONFIG_X86_64
2191 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2192#else
2193 nested_vmx_exit_ctls_high = 0;
2194#endif
2195 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2196
2197
2198 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2199 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2200
2201 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2202 nested_vmx_entry_ctls_high &=
2203 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2204 nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2205
2206
2207 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2208 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2209 nested_vmx_procbased_ctls_low = 0;
2210 nested_vmx_procbased_ctls_high &=
2211 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2212 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2213 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2214 CPU_BASED_CR3_STORE_EXITING |
2215#ifdef CONFIG_X86_64
2216 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2217#endif
2218 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2219 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2220 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2221 CPU_BASED_PAUSE_EXITING |
2222 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2223
2224
2225
2226
2227
2228
2229 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2230
2231
2232 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2233 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2234 nested_vmx_secondary_ctls_low = 0;
2235 nested_vmx_secondary_ctls_high &=
2236 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2237 SECONDARY_EXEC_WBINVD_EXITING;
2238
2239
2240 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2241 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2242 VMX_MISC_SAVE_EFER_LMA;
2243 nested_vmx_misc_high = 0;
2244}
2245
2246static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2247{
2248
2249
2250
2251 return ((control & high) | low) == control;
2252}
2253
2254static inline u64 vmx_control_msr(u32 low, u32 high)
2255{
2256 return low | ((u64)high << 32);
2257}
2258
2259
2260
2261
2262
2263
2264
2265
2266static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2267{
2268 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2269 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2270
2271
2272
2273
2274 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2275 return 1;
2276 }
2277
2278 switch (msr_index) {
2279 case MSR_IA32_FEATURE_CONTROL:
2280 *pdata = 0;
2281 break;
2282 case MSR_IA32_VMX_BASIC:
2283
2284
2285
2286
2287
2288
2289 *pdata = VMCS12_REVISION |
2290 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2291 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2292 break;
2293 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2294 case MSR_IA32_VMX_PINBASED_CTLS:
2295 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2296 nested_vmx_pinbased_ctls_high);
2297 break;
2298 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2299 case MSR_IA32_VMX_PROCBASED_CTLS:
2300 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2301 nested_vmx_procbased_ctls_high);
2302 break;
2303 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2304 case MSR_IA32_VMX_EXIT_CTLS:
2305 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2306 nested_vmx_exit_ctls_high);
2307 break;
2308 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2309 case MSR_IA32_VMX_ENTRY_CTLS:
2310 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2311 nested_vmx_entry_ctls_high);
2312 break;
2313 case MSR_IA32_VMX_MISC:
2314 *pdata = vmx_control_msr(nested_vmx_misc_low,
2315 nested_vmx_misc_high);
2316 break;
2317
2318
2319
2320
2321
2322#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2323#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2324 case MSR_IA32_VMX_CR0_FIXED0:
2325 *pdata = VMXON_CR0_ALWAYSON;
2326 break;
2327 case MSR_IA32_VMX_CR0_FIXED1:
2328 *pdata = -1ULL;
2329 break;
2330 case MSR_IA32_VMX_CR4_FIXED0:
2331 *pdata = VMXON_CR4_ALWAYSON;
2332 break;
2333 case MSR_IA32_VMX_CR4_FIXED1:
2334 *pdata = -1ULL;
2335 break;
2336 case MSR_IA32_VMX_VMCS_ENUM:
2337 *pdata = 0x1f;
2338 break;
2339 case MSR_IA32_VMX_PROCBASED_CTLS2:
2340 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2341 nested_vmx_secondary_ctls_high);
2342 break;
2343 case MSR_IA32_VMX_EPT_VPID_CAP:
2344
2345 *pdata = 0;
2346 break;
2347 default:
2348 return 0;
2349 }
2350
2351 return 1;
2352}
2353
2354static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2355{
2356 if (!nested_vmx_allowed(vcpu))
2357 return 0;
2358
2359 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2360
2361 return 1;
2362
2363
2364
2365
2366 return 0;
2367}
2368
2369
2370
2371
2372
2373
2374static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2375{
2376 u64 data;
2377 struct shared_msr_entry *msr;
2378
2379 if (!pdata) {
2380 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2381 return -EINVAL;
2382 }
2383
2384 switch (msr_index) {
2385#ifdef CONFIG_X86_64
2386 case MSR_FS_BASE:
2387 data = vmcs_readl(GUEST_FS_BASE);
2388 break;
2389 case MSR_GS_BASE:
2390 data = vmcs_readl(GUEST_GS_BASE);
2391 break;
2392 case MSR_KERNEL_GS_BASE:
2393 vmx_load_host_state(to_vmx(vcpu));
2394 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2395 break;
2396#endif
2397 case MSR_EFER:
2398 return kvm_get_msr_common(vcpu, msr_index, pdata);
2399 case MSR_IA32_TSC:
2400 data = guest_read_tsc();
2401 break;
2402 case MSR_IA32_SYSENTER_CS:
2403 data = vmcs_read32(GUEST_SYSENTER_CS);
2404 break;
2405 case MSR_IA32_SYSENTER_EIP:
2406 data = vmcs_readl(GUEST_SYSENTER_EIP);
2407 break;
2408 case MSR_IA32_SYSENTER_ESP:
2409 data = vmcs_readl(GUEST_SYSENTER_ESP);
2410 break;
2411 case MSR_TSC_AUX:
2412 if (!to_vmx(vcpu)->rdtscp_enabled)
2413 return 1;
2414
2415 default:
2416 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2417 return 0;
2418 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2419 if (msr) {
2420 data = msr->data;
2421 break;
2422 }
2423 return kvm_get_msr_common(vcpu, msr_index, pdata);
2424 }
2425
2426 *pdata = data;
2427 return 0;
2428}
2429
2430
2431
2432
2433
2434
2435static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2436{
2437 struct vcpu_vmx *vmx = to_vmx(vcpu);
2438 struct shared_msr_entry *msr;
2439 int ret = 0;
2440 u32 msr_index = msr_info->index;
2441 u64 data = msr_info->data;
2442
2443 switch (msr_index) {
2444 case MSR_EFER:
2445 ret = kvm_set_msr_common(vcpu, msr_info);
2446 break;
2447#ifdef CONFIG_X86_64
2448 case MSR_FS_BASE:
2449 vmx_segment_cache_clear(vmx);
2450 vmcs_writel(GUEST_FS_BASE, data);
2451 break;
2452 case MSR_GS_BASE:
2453 vmx_segment_cache_clear(vmx);
2454 vmcs_writel(GUEST_GS_BASE, data);
2455 break;
2456 case MSR_KERNEL_GS_BASE:
2457 vmx_load_host_state(vmx);
2458 vmx->msr_guest_kernel_gs_base = data;
2459 break;
2460#endif
2461 case MSR_IA32_SYSENTER_CS:
2462 vmcs_write32(GUEST_SYSENTER_CS, data);
2463 break;
2464 case MSR_IA32_SYSENTER_EIP:
2465 vmcs_writel(GUEST_SYSENTER_EIP, data);
2466 break;
2467 case MSR_IA32_SYSENTER_ESP:
2468 vmcs_writel(GUEST_SYSENTER_ESP, data);
2469 break;
2470 case MSR_IA32_TSC:
2471 kvm_write_tsc(vcpu, msr_info);
2472 break;
2473 case MSR_IA32_CR_PAT:
2474 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2475 vmcs_write64(GUEST_IA32_PAT, data);
2476 vcpu->arch.pat = data;
2477 break;
2478 }
2479 ret = kvm_set_msr_common(vcpu, msr_info);
2480 break;
2481 case MSR_IA32_TSC_ADJUST:
2482 ret = kvm_set_msr_common(vcpu, msr_info);
2483 break;
2484 case MSR_TSC_AUX:
2485 if (!vmx->rdtscp_enabled)
2486 return 1;
2487
2488 if ((data >> 32) != 0)
2489 return 1;
2490
2491 default:
2492 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2493 break;
2494 msr = find_msr_entry(vmx, msr_index);
2495 if (msr) {
2496 msr->data = data;
2497 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2498 preempt_disable();
2499 kvm_set_shared_msr(msr->index, msr->data,
2500 msr->mask);
2501 preempt_enable();
2502 }
2503 break;
2504 }
2505 ret = kvm_set_msr_common(vcpu, msr_info);
2506 }
2507
2508 return ret;
2509}
2510
2511static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2512{
2513 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2514 switch (reg) {
2515 case VCPU_REGS_RSP:
2516 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2517 break;
2518 case VCPU_REGS_RIP:
2519 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2520 break;
2521 case VCPU_EXREG_PDPTR:
2522 if (enable_ept)
2523 ept_save_pdptrs(vcpu);
2524 break;
2525 default:
2526 break;
2527 }
2528}
2529
2530static __init int cpu_has_kvm_support(void)
2531{
2532 return cpu_has_vmx();
2533}
2534
2535static __init int vmx_disabled_by_bios(void)
2536{
2537 u64 msr;
2538
2539 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2540 if (msr & FEATURE_CONTROL_LOCKED) {
2541
2542 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2543 && tboot_enabled())
2544 return 1;
2545
2546 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2547 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2548 && !tboot_enabled()) {
2549 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2550 "activate TXT before enabling KVM\n");
2551 return 1;
2552 }
2553
2554 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2555 && !tboot_enabled())
2556 return 1;
2557 }
2558
2559 return 0;
2560}
2561
2562static void kvm_cpu_vmxon(u64 addr)
2563{
2564 asm volatile (ASM_VMX_VMXON_RAX
2565 : : "a"(&addr), "m"(addr)
2566 : "memory", "cc");
2567}
2568
2569static int hardware_enable(void *garbage)
2570{
2571 int cpu = raw_smp_processor_id();
2572 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2573 u64 old, test_bits;
2574
2575 if (read_cr4() & X86_CR4_VMXE)
2576 return -EBUSY;
2577
2578 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589 crash_enable_local_vmclear(cpu);
2590
2591 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2592
2593 test_bits = FEATURE_CONTROL_LOCKED;
2594 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2595 if (tboot_enabled())
2596 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2597
2598 if ((old & test_bits) != test_bits) {
2599
2600 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2601 }
2602 write_cr4(read_cr4() | X86_CR4_VMXE);
2603
2604 if (vmm_exclusive) {
2605 kvm_cpu_vmxon(phys_addr);
2606 ept_sync_global();
2607 }
2608
2609 native_store_gdt(&__get_cpu_var(host_gdt));
2610
2611 return 0;
2612}
2613
2614static void vmclear_local_loaded_vmcss(void)
2615{
2616 int cpu = raw_smp_processor_id();
2617 struct loaded_vmcs *v, *n;
2618
2619 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2620 loaded_vmcss_on_cpu_link)
2621 __loaded_vmcs_clear(v);
2622}
2623
2624
2625
2626
2627
2628static void kvm_cpu_vmxoff(void)
2629{
2630 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2631}
2632
2633static void hardware_disable(void *garbage)
2634{
2635 if (vmm_exclusive) {
2636 vmclear_local_loaded_vmcss();
2637 kvm_cpu_vmxoff();
2638 }
2639 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2640}
2641
2642static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2643 u32 msr, u32 *result)
2644{
2645 u32 vmx_msr_low, vmx_msr_high;
2646 u32 ctl = ctl_min | ctl_opt;
2647
2648 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2649
2650 ctl &= vmx_msr_high;
2651 ctl |= vmx_msr_low;
2652
2653
2654 if (ctl_min & ~ctl)
2655 return -EIO;
2656
2657 *result = ctl;
2658 return 0;
2659}
2660
2661static __init bool allow_1_setting(u32 msr, u32 ctl)
2662{
2663 u32 vmx_msr_low, vmx_msr_high;
2664
2665 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2666 return vmx_msr_high & ctl;
2667}
2668
2669static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2670{
2671 u32 vmx_msr_low, vmx_msr_high;
2672 u32 min, opt, min2, opt2;
2673 u32 _pin_based_exec_control = 0;
2674 u32 _cpu_based_exec_control = 0;
2675 u32 _cpu_based_2nd_exec_control = 0;
2676 u32 _vmexit_control = 0;
2677 u32 _vmentry_control = 0;
2678
2679 min = CPU_BASED_HLT_EXITING |
2680#ifdef CONFIG_X86_64
2681 CPU_BASED_CR8_LOAD_EXITING |
2682 CPU_BASED_CR8_STORE_EXITING |
2683#endif
2684 CPU_BASED_CR3_LOAD_EXITING |
2685 CPU_BASED_CR3_STORE_EXITING |
2686 CPU_BASED_USE_IO_BITMAPS |
2687 CPU_BASED_MOV_DR_EXITING |
2688 CPU_BASED_USE_TSC_OFFSETING |
2689 CPU_BASED_MWAIT_EXITING |
2690 CPU_BASED_MONITOR_EXITING |
2691 CPU_BASED_INVLPG_EXITING |
2692 CPU_BASED_RDPMC_EXITING;
2693
2694 opt = CPU_BASED_TPR_SHADOW |
2695 CPU_BASED_USE_MSR_BITMAPS |
2696 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2697 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2698 &_cpu_based_exec_control) < 0)
2699 return -EIO;
2700#ifdef CONFIG_X86_64
2701 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2702 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2703 ~CPU_BASED_CR8_STORE_EXITING;
2704#endif
2705 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2706 min2 = 0;
2707 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2708 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2709 SECONDARY_EXEC_WBINVD_EXITING |
2710 SECONDARY_EXEC_ENABLE_VPID |
2711 SECONDARY_EXEC_ENABLE_EPT |
2712 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2713 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2714 SECONDARY_EXEC_RDTSCP |
2715 SECONDARY_EXEC_ENABLE_INVPCID |
2716 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2717 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2718 SECONDARY_EXEC_SHADOW_VMCS;
2719 if (adjust_vmx_controls(min2, opt2,
2720 MSR_IA32_VMX_PROCBASED_CTLS2,
2721 &_cpu_based_2nd_exec_control) < 0)
2722 return -EIO;
2723 }
2724#ifndef CONFIG_X86_64
2725 if (!(_cpu_based_2nd_exec_control &
2726 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2727 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2728#endif
2729
2730 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2731 _cpu_based_2nd_exec_control &= ~(
2732 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2733 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2734 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2735
2736 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2737
2738
2739 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2740 CPU_BASED_CR3_STORE_EXITING |
2741 CPU_BASED_INVLPG_EXITING);
2742 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2743 vmx_capability.ept, vmx_capability.vpid);
2744 }
2745
2746 min = 0;
2747#ifdef CONFIG_X86_64
2748 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2749#endif
2750 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2751 VM_EXIT_ACK_INTR_ON_EXIT;
2752 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2753 &_vmexit_control) < 0)
2754 return -EIO;
2755
2756 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2757 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2758 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2759 &_pin_based_exec_control) < 0)
2760 return -EIO;
2761
2762 if (!(_cpu_based_2nd_exec_control &
2763 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2764 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2765 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2766
2767 min = 0;
2768 opt = VM_ENTRY_LOAD_IA32_PAT;
2769 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2770 &_vmentry_control) < 0)
2771 return -EIO;
2772
2773 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2774
2775
2776 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2777 return -EIO;
2778
2779#ifdef CONFIG_X86_64
2780
2781 if (vmx_msr_high & (1u<<16))
2782 return -EIO;
2783#endif
2784
2785
2786 if (((vmx_msr_high >> 18) & 15) != 6)
2787 return -EIO;
2788
2789 vmcs_conf->size = vmx_msr_high & 0x1fff;
2790 vmcs_conf->order = get_order(vmcs_config.size);
2791 vmcs_conf->revision_id = vmx_msr_low;
2792
2793 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2794 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2795 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2796 vmcs_conf->vmexit_ctrl = _vmexit_control;
2797 vmcs_conf->vmentry_ctrl = _vmentry_control;
2798
2799 cpu_has_load_ia32_efer =
2800 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2801 VM_ENTRY_LOAD_IA32_EFER)
2802 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2803 VM_EXIT_LOAD_IA32_EFER);
2804
2805 cpu_has_load_perf_global_ctrl =
2806 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2807 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2808 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2809 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2826 switch (boot_cpu_data.x86_model) {
2827 case 26:
2828 case 30:
2829 case 37:
2830 case 44:
2831 case 46:
2832 cpu_has_load_perf_global_ctrl = false;
2833 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2834 "does not work properly. Using workaround\n");
2835 break;
2836 default:
2837 break;
2838 }
2839 }
2840
2841 return 0;
2842}
2843
2844static struct vmcs *alloc_vmcs_cpu(int cpu)
2845{
2846 int node = cpu_to_node(cpu);
2847 struct page *pages;
2848 struct vmcs *vmcs;
2849
2850 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2851 if (!pages)
2852 return NULL;
2853 vmcs = page_address(pages);
2854 memset(vmcs, 0, vmcs_config.size);
2855 vmcs->revision_id = vmcs_config.revision_id;
2856 return vmcs;
2857}
2858
2859static struct vmcs *alloc_vmcs(void)
2860{
2861 return alloc_vmcs_cpu(raw_smp_processor_id());
2862}
2863
2864static void free_vmcs(struct vmcs *vmcs)
2865{
2866 free_pages((unsigned long)vmcs, vmcs_config.order);
2867}
2868
2869
2870
2871
2872static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2873{
2874 if (!loaded_vmcs->vmcs)
2875 return;
2876 loaded_vmcs_clear(loaded_vmcs);
2877 free_vmcs(loaded_vmcs->vmcs);
2878 loaded_vmcs->vmcs = NULL;
2879}
2880
2881static void free_kvm_area(void)
2882{
2883 int cpu;
2884
2885 for_each_possible_cpu(cpu) {
2886 free_vmcs(per_cpu(vmxarea, cpu));
2887 per_cpu(vmxarea, cpu) = NULL;
2888 }
2889}
2890
2891static __init int alloc_kvm_area(void)
2892{
2893 int cpu;
2894
2895 for_each_possible_cpu(cpu) {
2896 struct vmcs *vmcs;
2897
2898 vmcs = alloc_vmcs_cpu(cpu);
2899 if (!vmcs) {
2900 free_kvm_area();
2901 return -ENOMEM;
2902 }
2903
2904 per_cpu(vmxarea, cpu) = vmcs;
2905 }
2906 return 0;
2907}
2908
2909static __init int hardware_setup(void)
2910{
2911 if (setup_vmcs_config(&vmcs_config) < 0)
2912 return -EIO;
2913
2914 if (boot_cpu_has(X86_FEATURE_NX))
2915 kvm_enable_efer_bits(EFER_NX);
2916
2917 if (!cpu_has_vmx_vpid())
2918 enable_vpid = 0;
2919 if (!cpu_has_vmx_shadow_vmcs())
2920 enable_shadow_vmcs = 0;
2921
2922 if (!cpu_has_vmx_ept() ||
2923 !cpu_has_vmx_ept_4levels()) {
2924 enable_ept = 0;
2925 enable_unrestricted_guest = 0;
2926 enable_ept_ad_bits = 0;
2927 }
2928
2929 if (!cpu_has_vmx_ept_ad_bits())
2930 enable_ept_ad_bits = 0;
2931
2932 if (!cpu_has_vmx_unrestricted_guest())
2933 enable_unrestricted_guest = 0;
2934
2935 if (!cpu_has_vmx_flexpriority())
2936 flexpriority_enabled = 0;
2937
2938 if (!cpu_has_vmx_tpr_shadow())
2939 kvm_x86_ops->update_cr8_intercept = NULL;
2940
2941 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2942 kvm_disable_largepages();
2943
2944 if (!cpu_has_vmx_ple())
2945 ple_gap = 0;
2946
2947 if (!cpu_has_vmx_apicv())
2948 enable_apicv = 0;
2949
2950 if (enable_apicv)
2951 kvm_x86_ops->update_cr8_intercept = NULL;
2952 else {
2953 kvm_x86_ops->hwapic_irr_update = NULL;
2954 kvm_x86_ops->deliver_posted_interrupt = NULL;
2955 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2956 }
2957
2958 if (nested)
2959 nested_vmx_setup_ctls_msrs();
2960
2961 return alloc_kvm_area();
2962}
2963
2964static __exit void hardware_unsetup(void)
2965{
2966 free_kvm_area();
2967}
2968
2969static bool emulation_required(struct kvm_vcpu *vcpu)
2970{
2971 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2972}
2973
2974static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2975 struct kvm_segment *save)
2976{
2977 if (!emulate_invalid_guest_state) {
2978
2979
2980
2981
2982
2983
2984
2985 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2986 save->selector &= ~SELECTOR_RPL_MASK;
2987 save->dpl = save->selector & SELECTOR_RPL_MASK;
2988 save->s = 1;
2989 }
2990 vmx_set_segment(vcpu, save, seg);
2991}
2992
2993static void enter_pmode(struct kvm_vcpu *vcpu)
2994{
2995 unsigned long flags;
2996 struct vcpu_vmx *vmx = to_vmx(vcpu);
2997
2998
2999
3000
3001
3002 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3003 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3004 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3005 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3006 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3007 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3008
3009 vmx->rmode.vm86_active = 0;
3010
3011 vmx_segment_cache_clear(vmx);
3012
3013 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3014
3015 flags = vmcs_readl(GUEST_RFLAGS);
3016 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3017 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3018 vmcs_writel(GUEST_RFLAGS, flags);
3019
3020 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3021 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3022
3023 update_exception_bitmap(vcpu);
3024
3025 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3026 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3027 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3028 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3029 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3030 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3031
3032
3033 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3034 vmx->cpl = 0;
3035}
3036
3037static void fix_rmode_seg(int seg, struct kvm_segment *save)
3038{
3039 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3040 struct kvm_segment var = *save;
3041
3042 var.dpl = 0x3;
3043 if (seg == VCPU_SREG_CS)
3044 var.type = 0x3;
3045
3046 if (!emulate_invalid_guest_state) {
3047 var.selector = var.base >> 4;
3048 var.base = var.base & 0xffff0;
3049 var.limit = 0xffff;
3050 var.g = 0;
3051 var.db = 0;
3052 var.present = 1;
3053 var.s = 1;
3054 var.l = 0;
3055 var.unusable = 0;
3056 var.type = 0x3;
3057 var.avl = 0;
3058 if (save->base & 0xf)
3059 printk_once(KERN_WARNING "kvm: segment base is not "
3060 "paragraph aligned when entering "
3061 "protected mode (seg=%d)", seg);
3062 }
3063
3064 vmcs_write16(sf->selector, var.selector);
3065 vmcs_write32(sf->base, var.base);
3066 vmcs_write32(sf->limit, var.limit);
3067 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3068}
3069
3070static void enter_rmode(struct kvm_vcpu *vcpu)
3071{
3072 unsigned long flags;
3073 struct vcpu_vmx *vmx = to_vmx(vcpu);
3074
3075 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3076 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3077 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3078 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3079 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3080 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3081 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3082
3083 vmx->rmode.vm86_active = 1;
3084
3085
3086
3087
3088
3089 if (!vcpu->kvm->arch.tss_addr)
3090 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3091 "called before entering vcpu\n");
3092
3093 vmx_segment_cache_clear(vmx);
3094
3095 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3096 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3097 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3098
3099 flags = vmcs_readl(GUEST_RFLAGS);
3100 vmx->rmode.save_rflags = flags;
3101
3102 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3103
3104 vmcs_writel(GUEST_RFLAGS, flags);
3105 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3106 update_exception_bitmap(vcpu);
3107
3108 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3109 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3110 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3111 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3112 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3113 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3114
3115 kvm_mmu_reset_context(vcpu);
3116}
3117
3118static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3119{
3120 struct vcpu_vmx *vmx = to_vmx(vcpu);
3121 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3122
3123 if (!msr)
3124 return;
3125
3126
3127
3128
3129
3130 vmx_load_host_state(to_vmx(vcpu));
3131 vcpu->arch.efer = efer;
3132 if (efer & EFER_LMA) {
3133 vmcs_write32(VM_ENTRY_CONTROLS,
3134 vmcs_read32(VM_ENTRY_CONTROLS) |
3135 VM_ENTRY_IA32E_MODE);
3136 msr->data = efer;
3137 } else {
3138 vmcs_write32(VM_ENTRY_CONTROLS,
3139 vmcs_read32(VM_ENTRY_CONTROLS) &
3140 ~VM_ENTRY_IA32E_MODE);
3141
3142 msr->data = efer & ~EFER_LME;
3143 }
3144 setup_msrs(vmx);
3145}
3146
3147#ifdef CONFIG_X86_64
3148
3149static void enter_lmode(struct kvm_vcpu *vcpu)
3150{
3151 u32 guest_tr_ar;
3152
3153 vmx_segment_cache_clear(to_vmx(vcpu));
3154
3155 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3156 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3157 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3158 __func__);
3159 vmcs_write32(GUEST_TR_AR_BYTES,
3160 (guest_tr_ar & ~AR_TYPE_MASK)
3161 | AR_TYPE_BUSY_64_TSS);
3162 }
3163 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3164}
3165
3166static void exit_lmode(struct kvm_vcpu *vcpu)
3167{
3168 vmcs_write32(VM_ENTRY_CONTROLS,
3169 vmcs_read32(VM_ENTRY_CONTROLS)
3170 & ~VM_ENTRY_IA32E_MODE);
3171 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3172}
3173
3174#endif
3175
3176static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3177{
3178 vpid_sync_context(to_vmx(vcpu));
3179 if (enable_ept) {
3180 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3181 return;
3182 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3183 }
3184}
3185
3186static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3187{
3188 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3189
3190 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3191 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3192}
3193
3194static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3195{
3196 if (enable_ept && is_paging(vcpu))
3197 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3198 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3199}
3200
3201static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3202{
3203 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3204
3205 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3206 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3207}
3208
3209static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3210{
3211 if (!test_bit(VCPU_EXREG_PDPTR,
3212 (unsigned long *)&vcpu->arch.regs_dirty))
3213 return;
3214
3215 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3216 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3217 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3218 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3219 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3220 }
3221}
3222
3223static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3224{
3225 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3226 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3227 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3228 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3229 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3230 }
3231
3232 __set_bit(VCPU_EXREG_PDPTR,
3233 (unsigned long *)&vcpu->arch.regs_avail);
3234 __set_bit(VCPU_EXREG_PDPTR,
3235 (unsigned long *)&vcpu->arch.regs_dirty);
3236}
3237
3238static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3239
3240static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3241 unsigned long cr0,
3242 struct kvm_vcpu *vcpu)
3243{
3244 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3245 vmx_decache_cr3(vcpu);
3246 if (!(cr0 & X86_CR0_PG)) {
3247
3248 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3249 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3250 (CPU_BASED_CR3_LOAD_EXITING |
3251 CPU_BASED_CR3_STORE_EXITING));
3252 vcpu->arch.cr0 = cr0;
3253 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3254 } else if (!is_paging(vcpu)) {
3255
3256 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3257 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3258 ~(CPU_BASED_CR3_LOAD_EXITING |
3259 CPU_BASED_CR3_STORE_EXITING));
3260 vcpu->arch.cr0 = cr0;
3261 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3262 }
3263
3264 if (!(cr0 & X86_CR0_WP))
3265 *hw_cr0 &= ~X86_CR0_WP;
3266}
3267
3268static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3269{
3270 struct vcpu_vmx *vmx = to_vmx(vcpu);
3271 unsigned long hw_cr0;
3272
3273 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3274 if (enable_unrestricted_guest)
3275 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3276 else {
3277 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3278
3279 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3280 enter_pmode(vcpu);
3281
3282 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3283 enter_rmode(vcpu);
3284 }
3285
3286#ifdef CONFIG_X86_64
3287 if (vcpu->arch.efer & EFER_LME) {
3288 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3289 enter_lmode(vcpu);
3290 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3291 exit_lmode(vcpu);
3292 }
3293#endif
3294
3295 if (enable_ept)
3296 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3297
3298 if (!vcpu->fpu_active)
3299 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3300
3301 vmcs_writel(CR0_READ_SHADOW, cr0);
3302 vmcs_writel(GUEST_CR0, hw_cr0);
3303 vcpu->arch.cr0 = cr0;
3304
3305
3306 vmx->emulation_required = emulation_required(vcpu);
3307}
3308
3309static u64 construct_eptp(unsigned long root_hpa)
3310{
3311 u64 eptp;
3312
3313
3314 eptp = VMX_EPT_DEFAULT_MT |
3315 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3316 if (enable_ept_ad_bits)
3317 eptp |= VMX_EPT_AD_ENABLE_BIT;
3318 eptp |= (root_hpa & PAGE_MASK);
3319
3320 return eptp;
3321}
3322
3323static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3324{
3325 unsigned long guest_cr3;
3326 u64 eptp;
3327
3328 guest_cr3 = cr3;
3329 if (enable_ept) {
3330 eptp = construct_eptp(cr3);
3331 vmcs_write64(EPT_POINTER, eptp);
3332 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3333 vcpu->kvm->arch.ept_identity_map_addr;
3334 ept_load_pdptrs(vcpu);
3335 }
3336
3337 vmx_flush_tlb(vcpu);
3338 vmcs_writel(GUEST_CR3, guest_cr3);
3339}
3340
3341static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3342{
3343 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3344 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3345
3346 if (cr4 & X86_CR4_VMXE) {
3347
3348
3349
3350
3351
3352
3353 if (!nested_vmx_allowed(vcpu))
3354 return 1;
3355 }
3356 if (to_vmx(vcpu)->nested.vmxon &&
3357 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3358 return 1;
3359
3360 vcpu->arch.cr4 = cr4;
3361 if (enable_ept) {
3362 if (!is_paging(vcpu)) {
3363 hw_cr4 &= ~X86_CR4_PAE;
3364 hw_cr4 |= X86_CR4_PSE;
3365
3366
3367
3368
3369
3370
3371
3372 hw_cr4 &= ~X86_CR4_SMEP;
3373 } else if (!(cr4 & X86_CR4_PAE)) {
3374 hw_cr4 &= ~X86_CR4_PAE;
3375 }
3376 }
3377
3378 vmcs_writel(CR4_READ_SHADOW, cr4);
3379 vmcs_writel(GUEST_CR4, hw_cr4);
3380 return 0;
3381}
3382
3383static void vmx_get_segment(struct kvm_vcpu *vcpu,
3384 struct kvm_segment *var, int seg)
3385{
3386 struct vcpu_vmx *vmx = to_vmx(vcpu);
3387 u32 ar;
3388
3389 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3390 *var = vmx->rmode.segs[seg];
3391 if (seg == VCPU_SREG_TR
3392 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3393 return;
3394 var->base = vmx_read_guest_seg_base(vmx, seg);
3395 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3396 return;
3397 }
3398 var->base = vmx_read_guest_seg_base(vmx, seg);
3399 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3400 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3401 ar = vmx_read_guest_seg_ar(vmx, seg);
3402 var->type = ar & 15;
3403 var->s = (ar >> 4) & 1;
3404 var->dpl = (ar >> 5) & 3;
3405 var->present = (ar >> 7) & 1;
3406 var->avl = (ar >> 12) & 1;
3407 var->l = (ar >> 13) & 1;
3408 var->db = (ar >> 14) & 1;
3409 var->g = (ar >> 15) & 1;
3410 var->unusable = (ar >> 16) & 1;
3411}
3412
3413static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3414{
3415 struct kvm_segment s;
3416
3417 if (to_vmx(vcpu)->rmode.vm86_active) {
3418 vmx_get_segment(vcpu, &s, seg);
3419 return s.base;
3420 }
3421 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3422}
3423
3424static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3425{
3426 struct vcpu_vmx *vmx = to_vmx(vcpu);
3427
3428 if (!is_protmode(vcpu))
3429 return 0;
3430
3431 if (!is_long_mode(vcpu)
3432 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM))
3433 return 3;
3434
3435 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3436 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3437 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3438 }
3439
3440 return vmx->cpl;
3441}
3442
3443
3444static u32 vmx_segment_access_rights(struct kvm_segment *var)
3445{
3446 u32 ar;
3447
3448 if (var->unusable || !var->present)
3449 ar = 1 << 16;
3450 else {
3451 ar = var->type & 15;
3452 ar |= (var->s & 1) << 4;
3453 ar |= (var->dpl & 3) << 5;
3454 ar |= (var->present & 1) << 7;
3455 ar |= (var->avl & 1) << 12;
3456 ar |= (var->l & 1) << 13;
3457 ar |= (var->db & 1) << 14;
3458 ar |= (var->g & 1) << 15;
3459 }
3460
3461 return ar;
3462}
3463
3464static void vmx_set_segment(struct kvm_vcpu *vcpu,
3465 struct kvm_segment *var, int seg)
3466{
3467 struct vcpu_vmx *vmx = to_vmx(vcpu);
3468 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3469
3470 vmx_segment_cache_clear(vmx);
3471 if (seg == VCPU_SREG_CS)
3472 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3473
3474 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3475 vmx->rmode.segs[seg] = *var;
3476 if (seg == VCPU_SREG_TR)
3477 vmcs_write16(sf->selector, var->selector);
3478 else if (var->s)
3479 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3480 goto out;
3481 }
3482
3483 vmcs_writel(sf->base, var->base);
3484 vmcs_write32(sf->limit, var->limit);
3485 vmcs_write16(sf->selector, var->selector);
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3499 var->type |= 0x1;
3500
3501 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3502
3503out:
3504 vmx->emulation_required |= emulation_required(vcpu);
3505}
3506
3507static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3508{
3509 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3510
3511 *db = (ar >> 14) & 1;
3512 *l = (ar >> 13) & 1;
3513}
3514
3515static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3516{
3517 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3518 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3519}
3520
3521static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3522{
3523 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3524 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3525}
3526
3527static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3528{
3529 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3530 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3531}
3532
3533static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3534{
3535 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3536 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3537}
3538
3539static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3540{
3541 struct kvm_segment var;
3542 u32 ar;
3543
3544 vmx_get_segment(vcpu, &var, seg);
3545 var.dpl = 0x3;
3546 if (seg == VCPU_SREG_CS)
3547 var.type = 0x3;
3548 ar = vmx_segment_access_rights(&var);
3549
3550 if (var.base != (var.selector << 4))
3551 return false;
3552 if (var.limit != 0xffff)
3553 return false;
3554 if (ar != 0xf3)
3555 return false;
3556
3557 return true;
3558}
3559
3560static bool code_segment_valid(struct kvm_vcpu *vcpu)
3561{
3562 struct kvm_segment cs;
3563 unsigned int cs_rpl;
3564
3565 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3566 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3567
3568 if (cs.unusable)
3569 return false;
3570 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3571 return false;
3572 if (!cs.s)
3573 return false;
3574 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3575 if (cs.dpl > cs_rpl)
3576 return false;
3577 } else {
3578 if (cs.dpl != cs_rpl)
3579 return false;
3580 }
3581 if (!cs.present)
3582 return false;
3583
3584
3585 return true;
3586}
3587
3588static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3589{
3590 struct kvm_segment ss;
3591 unsigned int ss_rpl;
3592
3593 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3594 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3595
3596 if (ss.unusable)
3597 return true;
3598 if (ss.type != 3 && ss.type != 7)
3599 return false;
3600 if (!ss.s)
3601 return false;
3602 if (ss.dpl != ss_rpl)
3603 return false;
3604 if (!ss.present)
3605 return false;
3606
3607 return true;
3608}
3609
3610static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3611{
3612 struct kvm_segment var;
3613 unsigned int rpl;
3614
3615 vmx_get_segment(vcpu, &var, seg);
3616 rpl = var.selector & SELECTOR_RPL_MASK;
3617
3618 if (var.unusable)
3619 return true;
3620 if (!var.s)
3621 return false;
3622 if (!var.present)
3623 return false;
3624 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3625 if (var.dpl < rpl)
3626 return false;
3627 }
3628
3629
3630
3631
3632 return true;
3633}
3634
3635static bool tr_valid(struct kvm_vcpu *vcpu)
3636{
3637 struct kvm_segment tr;
3638
3639 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3640
3641 if (tr.unusable)
3642 return false;
3643 if (tr.selector & SELECTOR_TI_MASK)
3644 return false;
3645 if (tr.type != 3 && tr.type != 11)
3646 return false;
3647 if (!tr.present)
3648 return false;
3649
3650 return true;
3651}
3652
3653static bool ldtr_valid(struct kvm_vcpu *vcpu)
3654{
3655 struct kvm_segment ldtr;
3656
3657 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3658
3659 if (ldtr.unusable)
3660 return true;
3661 if (ldtr.selector & SELECTOR_TI_MASK)
3662 return false;
3663 if (ldtr.type != 2)
3664 return false;
3665 if (!ldtr.present)
3666 return false;
3667
3668 return true;
3669}
3670
3671static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3672{
3673 struct kvm_segment cs, ss;
3674
3675 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3676 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3677
3678 return ((cs.selector & SELECTOR_RPL_MASK) ==
3679 (ss.selector & SELECTOR_RPL_MASK));
3680}
3681
3682
3683
3684
3685
3686
3687static bool guest_state_valid(struct kvm_vcpu *vcpu)
3688{
3689 if (enable_unrestricted_guest)
3690 return true;
3691
3692
3693 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3694 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3695 return false;
3696 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3697 return false;
3698 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3699 return false;
3700 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3701 return false;
3702 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3703 return false;
3704 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3705 return false;
3706 } else {
3707
3708 if (!cs_ss_rpl_check(vcpu))
3709 return false;
3710 if (!code_segment_valid(vcpu))
3711 return false;
3712 if (!stack_segment_valid(vcpu))
3713 return false;
3714 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3715 return false;
3716 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3717 return false;
3718 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3719 return false;
3720 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3721 return false;
3722 if (!tr_valid(vcpu))
3723 return false;
3724 if (!ldtr_valid(vcpu))
3725 return false;
3726 }
3727
3728
3729
3730
3731
3732 return true;
3733}
3734
3735static int init_rmode_tss(struct kvm *kvm)
3736{
3737 gfn_t fn;
3738 u16 data = 0;
3739 int r, idx, ret = 0;
3740
3741 idx = srcu_read_lock(&kvm->srcu);
3742 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3743 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3744 if (r < 0)
3745 goto out;
3746 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3747 r = kvm_write_guest_page(kvm, fn++, &data,
3748 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3749 if (r < 0)
3750 goto out;
3751 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3752 if (r < 0)
3753 goto out;
3754 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3755 if (r < 0)
3756 goto out;
3757 data = ~0;
3758 r = kvm_write_guest_page(kvm, fn, &data,
3759 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3760 sizeof(u8));
3761 if (r < 0)
3762 goto out;
3763
3764 ret = 1;
3765out:
3766 srcu_read_unlock(&kvm->srcu, idx);
3767 return ret;
3768}
3769
3770static int init_rmode_identity_map(struct kvm *kvm)
3771{
3772 int i, idx, r, ret;
3773 pfn_t identity_map_pfn;
3774 u32 tmp;
3775
3776 if (!enable_ept)
3777 return 1;
3778 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3779 printk(KERN_ERR "EPT: identity-mapping pagetable "
3780 "haven't been allocated!\n");
3781 return 0;
3782 }
3783 if (likely(kvm->arch.ept_identity_pagetable_done))
3784 return 1;
3785 ret = 0;
3786 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3787 idx = srcu_read_lock(&kvm->srcu);
3788 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3789 if (r < 0)
3790 goto out;
3791
3792 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3793 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3794 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3795 r = kvm_write_guest_page(kvm, identity_map_pfn,
3796 &tmp, i * sizeof(tmp), sizeof(tmp));
3797 if (r < 0)
3798 goto out;
3799 }
3800 kvm->arch.ept_identity_pagetable_done = true;
3801 ret = 1;
3802out:
3803 srcu_read_unlock(&kvm->srcu, idx);
3804 return ret;
3805}
3806
3807static void seg_setup(int seg)
3808{
3809 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3810 unsigned int ar;
3811
3812 vmcs_write16(sf->selector, 0);
3813 vmcs_writel(sf->base, 0);
3814 vmcs_write32(sf->limit, 0xffff);
3815 ar = 0x93;
3816 if (seg == VCPU_SREG_CS)
3817 ar |= 0x08;
3818
3819 vmcs_write32(sf->ar_bytes, ar);
3820}
3821
3822static int alloc_apic_access_page(struct kvm *kvm)
3823{
3824 struct page *page;
3825 struct kvm_userspace_memory_region kvm_userspace_mem;
3826 int r = 0;
3827
3828 mutex_lock(&kvm->slots_lock);
3829 if (kvm->arch.apic_access_page)
3830 goto out;
3831 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3832 kvm_userspace_mem.flags = 0;
3833 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3834 kvm_userspace_mem.memory_size = PAGE_SIZE;
3835 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3836 if (r)
3837 goto out;
3838
3839 page = gfn_to_page(kvm, 0xfee00);
3840 if (is_error_page(page)) {
3841 r = -EFAULT;
3842 goto out;
3843 }
3844
3845 kvm->arch.apic_access_page = page;
3846out:
3847 mutex_unlock(&kvm->slots_lock);
3848 return r;
3849}
3850
3851static int alloc_identity_pagetable(struct kvm *kvm)
3852{
3853 struct page *page;
3854 struct kvm_userspace_memory_region kvm_userspace_mem;
3855 int r = 0;
3856
3857 mutex_lock(&kvm->slots_lock);
3858 if (kvm->arch.ept_identity_pagetable)
3859 goto out;
3860 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3861 kvm_userspace_mem.flags = 0;
3862 kvm_userspace_mem.guest_phys_addr =
3863 kvm->arch.ept_identity_map_addr;
3864 kvm_userspace_mem.memory_size = PAGE_SIZE;
3865 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3866 if (r)
3867 goto out;
3868
3869 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3870 if (is_error_page(page)) {
3871 r = -EFAULT;
3872 goto out;
3873 }
3874
3875 kvm->arch.ept_identity_pagetable = page;
3876out:
3877 mutex_unlock(&kvm->slots_lock);
3878 return r;
3879}
3880
3881static void allocate_vpid(struct vcpu_vmx *vmx)
3882{
3883 int vpid;
3884
3885 vmx->vpid = 0;
3886 if (!enable_vpid)
3887 return;
3888 spin_lock(&vmx_vpid_lock);
3889 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3890 if (vpid < VMX_NR_VPIDS) {
3891 vmx->vpid = vpid;
3892 __set_bit(vpid, vmx_vpid_bitmap);
3893 }
3894 spin_unlock(&vmx_vpid_lock);
3895}
3896
3897static void free_vpid(struct vcpu_vmx *vmx)
3898{
3899 if (!enable_vpid)
3900 return;
3901 spin_lock(&vmx_vpid_lock);
3902 if (vmx->vpid != 0)
3903 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3904 spin_unlock(&vmx_vpid_lock);
3905}
3906
3907#define MSR_TYPE_R 1
3908#define MSR_TYPE_W 2
3909static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3910 u32 msr, int type)
3911{
3912 int f = sizeof(unsigned long);
3913
3914 if (!cpu_has_vmx_msr_bitmap())
3915 return;
3916
3917
3918
3919
3920
3921
3922 if (msr <= 0x1fff) {
3923 if (type & MSR_TYPE_R)
3924
3925 __clear_bit(msr, msr_bitmap + 0x000 / f);
3926
3927 if (type & MSR_TYPE_W)
3928
3929 __clear_bit(msr, msr_bitmap + 0x800 / f);
3930
3931 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3932 msr &= 0x1fff;
3933 if (type & MSR_TYPE_R)
3934
3935 __clear_bit(msr, msr_bitmap + 0x400 / f);
3936
3937 if (type & MSR_TYPE_W)
3938
3939 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3940
3941 }
3942}
3943
3944static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3945 u32 msr, int type)
3946{
3947 int f = sizeof(unsigned long);
3948
3949 if (!cpu_has_vmx_msr_bitmap())
3950 return;
3951
3952
3953
3954
3955
3956
3957 if (msr <= 0x1fff) {
3958 if (type & MSR_TYPE_R)
3959
3960 __set_bit(msr, msr_bitmap + 0x000 / f);
3961
3962 if (type & MSR_TYPE_W)
3963
3964 __set_bit(msr, msr_bitmap + 0x800 / f);
3965
3966 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3967 msr &= 0x1fff;
3968 if (type & MSR_TYPE_R)
3969
3970 __set_bit(msr, msr_bitmap + 0x400 / f);
3971
3972 if (type & MSR_TYPE_W)
3973
3974 __set_bit(msr, msr_bitmap + 0xc00 / f);
3975
3976 }
3977}
3978
3979static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3980{
3981 if (!longmode_only)
3982 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3983 msr, MSR_TYPE_R | MSR_TYPE_W);
3984 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3985 msr, MSR_TYPE_R | MSR_TYPE_W);
3986}
3987
3988static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3989{
3990 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3991 msr, MSR_TYPE_R);
3992 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3993 msr, MSR_TYPE_R);
3994}
3995
3996static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3997{
3998 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3999 msr, MSR_TYPE_R);
4000 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4001 msr, MSR_TYPE_R);
4002}
4003
4004static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4005{
4006 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4007 msr, MSR_TYPE_W);
4008 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4009 msr, MSR_TYPE_W);
4010}
4011
4012static int vmx_vm_has_apicv(struct kvm *kvm)
4013{
4014 return enable_apicv && irqchip_in_kernel(kvm);
4015}
4016
4017
4018
4019
4020
4021
4022
4023
4024static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4025{
4026 struct vcpu_vmx *vmx = to_vmx(vcpu);
4027 int r;
4028
4029 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4030 return;
4031
4032 r = pi_test_and_set_on(&vmx->pi_desc);
4033 kvm_make_request(KVM_REQ_EVENT, vcpu);
4034#ifdef CONFIG_SMP
4035 if (!r && (vcpu->mode == IN_GUEST_MODE))
4036 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4037 POSTED_INTR_VECTOR);
4038 else
4039#endif
4040 kvm_vcpu_kick(vcpu);
4041}
4042
4043static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4044{
4045 struct vcpu_vmx *vmx = to_vmx(vcpu);
4046
4047 if (!pi_test_and_clear_on(&vmx->pi_desc))
4048 return;
4049
4050 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4051}
4052
4053static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4054{
4055 return;
4056}
4057
4058
4059
4060
4061
4062
4063
4064static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4065{
4066 u32 low32, high32;
4067 unsigned long tmpl;
4068 struct desc_ptr dt;
4069
4070 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);
4071 vmcs_writel(HOST_CR4, read_cr4());
4072 vmcs_writel(HOST_CR3, read_cr3());
4073
4074 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);
4075#ifdef CONFIG_X86_64
4076
4077
4078
4079
4080
4081 vmcs_write16(HOST_DS_SELECTOR, 0);
4082 vmcs_write16(HOST_ES_SELECTOR, 0);
4083#else
4084 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);
4085 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);
4086#endif
4087 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);
4088 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);
4089
4090 native_store_idt(&dt);
4091 vmcs_writel(HOST_IDTR_BASE, dt.address);
4092 vmx->host_idt_base = dt.address;
4093
4094 vmcs_writel(HOST_RIP, vmx_return);
4095
4096 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4097 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4098 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4099 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);
4100
4101 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4102 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4103 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4104 }
4105}
4106
4107static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4108{
4109 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4110 if (enable_ept)
4111 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4112 if (is_guest_mode(&vmx->vcpu))
4113 vmx->vcpu.arch.cr4_guest_owned_bits &=
4114 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4115 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4116}
4117
4118static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4119{
4120 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4121
4122 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4123 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4124 return pin_based_exec_ctrl;
4125}
4126
4127static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4128{
4129 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4130 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4131 exec_control &= ~CPU_BASED_TPR_SHADOW;
4132#ifdef CONFIG_X86_64
4133 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4134 CPU_BASED_CR8_LOAD_EXITING;
4135#endif
4136 }
4137 if (!enable_ept)
4138 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4139 CPU_BASED_CR3_LOAD_EXITING |
4140 CPU_BASED_INVLPG_EXITING;
4141 return exec_control;
4142}
4143
4144static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4145{
4146 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4147 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4148 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4149 if (vmx->vpid == 0)
4150 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4151 if (!enable_ept) {
4152 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4153 enable_unrestricted_guest = 0;
4154
4155 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4156 }
4157 if (!enable_unrestricted_guest)
4158 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4159 if (!ple_gap)
4160 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4161 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4162 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4163 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4164 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4165
4166
4167
4168
4169
4170 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4171 return exec_control;
4172}
4173
4174static void ept_set_mmio_spte_mask(void)
4175{
4176
4177
4178
4179
4180
4181
4182 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
4183}
4184
4185
4186
4187
4188static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4189{
4190#ifdef CONFIG_X86_64
4191 unsigned long a;
4192#endif
4193 int i;
4194
4195
4196 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4197 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4198
4199 if (enable_shadow_vmcs) {
4200 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4201 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4202 }
4203 if (cpu_has_vmx_msr_bitmap())
4204 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4205
4206 vmcs_write64(VMCS_LINK_POINTER, -1ull);
4207
4208
4209 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4210
4211 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4212
4213 if (cpu_has_secondary_exec_ctrls()) {
4214 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4215 vmx_secondary_exec_control(vmx));
4216 }
4217
4218 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4219 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4220 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4221 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4222 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4223
4224 vmcs_write16(GUEST_INTR_STATUS, 0);
4225
4226 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4227 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4228 }
4229
4230 if (ple_gap) {
4231 vmcs_write32(PLE_GAP, ple_gap);
4232 vmcs_write32(PLE_WINDOW, ple_window);
4233 }
4234
4235 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4236 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4237 vmcs_write32(CR3_TARGET_COUNT, 0);
4238
4239 vmcs_write16(HOST_FS_SELECTOR, 0);
4240 vmcs_write16(HOST_GS_SELECTOR, 0);
4241 vmx_set_constant_host_state(vmx);
4242#ifdef CONFIG_X86_64
4243 rdmsrl(MSR_FS_BASE, a);
4244 vmcs_writel(HOST_FS_BASE, a);
4245 rdmsrl(MSR_GS_BASE, a);
4246 vmcs_writel(HOST_GS_BASE, a);
4247#else
4248 vmcs_writel(HOST_FS_BASE, 0);
4249 vmcs_writel(HOST_GS_BASE, 0);
4250#endif
4251
4252 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4253 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4254 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4255 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4256 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4257
4258 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4259 u32 msr_low, msr_high;
4260 u64 host_pat;
4261 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4262 host_pat = msr_low | ((u64) msr_high << 32);
4263
4264 vmcs_write64(GUEST_IA32_PAT, host_pat);
4265
4266 vmx->vcpu.arch.pat = host_pat;
4267 }
4268
4269 for (i = 0; i < NR_VMX_MSR; ++i) {
4270 u32 index = vmx_msr_index[i];
4271 u32 data_low, data_high;
4272 int j = vmx->nmsrs;
4273
4274 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4275 continue;
4276 if (wrmsr_safe(index, data_low, data_high) < 0)
4277 continue;
4278 vmx->guest_msrs[j].index = i;
4279 vmx->guest_msrs[j].data = 0;
4280 vmx->guest_msrs[j].mask = -1ull;
4281 ++vmx->nmsrs;
4282 }
4283
4284 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4285
4286
4287 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4288
4289 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4290 set_cr4_guest_host_mask(vmx);
4291
4292 return 0;
4293}
4294
4295static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4296{
4297 struct vcpu_vmx *vmx = to_vmx(vcpu);
4298 u64 msr;
4299
4300 vmx->rmode.vm86_active = 0;
4301
4302 vmx->soft_vnmi_blocked = 0;
4303
4304 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4305 kvm_set_cr8(&vmx->vcpu, 0);
4306 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4307 if (kvm_vcpu_is_bsp(&vmx->vcpu))
4308 msr |= MSR_IA32_APICBASE_BSP;
4309 kvm_set_apic_base(&vmx->vcpu, msr);
4310
4311 vmx_segment_cache_clear(vmx);
4312
4313 seg_setup(VCPU_SREG_CS);
4314 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4315 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4316
4317 seg_setup(VCPU_SREG_DS);
4318 seg_setup(VCPU_SREG_ES);
4319 seg_setup(VCPU_SREG_FS);
4320 seg_setup(VCPU_SREG_GS);
4321 seg_setup(VCPU_SREG_SS);
4322
4323 vmcs_write16(GUEST_TR_SELECTOR, 0);
4324 vmcs_writel(GUEST_TR_BASE, 0);
4325 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4326 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4327
4328 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4329 vmcs_writel(GUEST_LDTR_BASE, 0);
4330 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4331 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4332
4333 vmcs_write32(GUEST_SYSENTER_CS, 0);
4334 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4335 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4336
4337 vmcs_writel(GUEST_RFLAGS, 0x02);
4338 kvm_rip_write(vcpu, 0xfff0);
4339
4340 vmcs_writel(GUEST_GDTR_BASE, 0);
4341 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4342
4343 vmcs_writel(GUEST_IDTR_BASE, 0);
4344 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4345
4346 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4347 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4348 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4349
4350
4351 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4352
4353 setup_msrs(vmx);
4354
4355 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
4356
4357 if (cpu_has_vmx_tpr_shadow()) {
4358 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4359 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4360 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4361 __pa(vmx->vcpu.arch.apic->regs));
4362 vmcs_write32(TPR_THRESHOLD, 0);
4363 }
4364
4365 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4366 vmcs_write64(APIC_ACCESS_ADDR,
4367 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4368
4369 if (vmx_vm_has_apicv(vcpu->kvm))
4370 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4371
4372 if (vmx->vpid != 0)
4373 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4374
4375 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4376 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu));
4377 vmx_set_cr4(&vmx->vcpu, 0);
4378 vmx_set_efer(&vmx->vcpu, 0);
4379 vmx_fpu_activate(&vmx->vcpu);
4380 update_exception_bitmap(&vmx->vcpu);
4381
4382 vpid_sync_context(vmx);
4383}
4384
4385
4386
4387
4388
4389static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4390{
4391 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4392 PIN_BASED_EXT_INTR_MASK;
4393}
4394
4395static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4396{
4397 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4398 PIN_BASED_NMI_EXITING;
4399}
4400
4401static int enable_irq_window(struct kvm_vcpu *vcpu)
4402{
4403 u32 cpu_based_vm_exec_control;
4404
4405 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4406
4407
4408
4409
4410
4411
4412 return -EBUSY;
4413
4414 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4415 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4416 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4417 return 0;
4418}
4419
4420static int enable_nmi_window(struct kvm_vcpu *vcpu)
4421{
4422 u32 cpu_based_vm_exec_control;
4423
4424 if (!cpu_has_virtual_nmis())
4425 return enable_irq_window(vcpu);
4426
4427 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4428 return enable_irq_window(vcpu);
4429
4430 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4431 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4432 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4433 return 0;
4434}
4435
4436static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4437{
4438 struct vcpu_vmx *vmx = to_vmx(vcpu);
4439 uint32_t intr;
4440 int irq = vcpu->arch.interrupt.nr;
4441
4442 trace_kvm_inj_virq(irq);
4443
4444 ++vcpu->stat.irq_injections;
4445 if (vmx->rmode.vm86_active) {
4446 int inc_eip = 0;
4447 if (vcpu->arch.interrupt.soft)
4448 inc_eip = vcpu->arch.event_exit_inst_len;
4449 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4450 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4451 return;
4452 }
4453 intr = irq | INTR_INFO_VALID_MASK;
4454 if (vcpu->arch.interrupt.soft) {
4455 intr |= INTR_TYPE_SOFT_INTR;
4456 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4457 vmx->vcpu.arch.event_exit_inst_len);
4458 } else
4459 intr |= INTR_TYPE_EXT_INTR;
4460 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4461}
4462
4463static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4464{
4465 struct vcpu_vmx *vmx = to_vmx(vcpu);
4466
4467 if (is_guest_mode(vcpu))
4468 return;
4469
4470 if (!cpu_has_virtual_nmis()) {
4471
4472
4473
4474
4475
4476
4477
4478
4479 vmx->soft_vnmi_blocked = 1;
4480 vmx->vnmi_blocked_time = 0;
4481 }
4482
4483 ++vcpu->stat.nmi_injections;
4484 vmx->nmi_known_unmasked = false;
4485 if (vmx->rmode.vm86_active) {
4486 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4487 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4488 return;
4489 }
4490 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4491 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4492}
4493
4494static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4495{
4496 if (!cpu_has_virtual_nmis())
4497 return to_vmx(vcpu)->soft_vnmi_blocked;
4498 if (to_vmx(vcpu)->nmi_known_unmasked)
4499 return false;
4500 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4501}
4502
4503static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4504{
4505 struct vcpu_vmx *vmx = to_vmx(vcpu);
4506
4507 if (!cpu_has_virtual_nmis()) {
4508 if (vmx->soft_vnmi_blocked != masked) {
4509 vmx->soft_vnmi_blocked = masked;
4510 vmx->vnmi_blocked_time = 0;
4511 }
4512 } else {
4513 vmx->nmi_known_unmasked = !masked;
4514 if (masked)
4515 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4516 GUEST_INTR_STATE_NMI);
4517 else
4518 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4519 GUEST_INTR_STATE_NMI);
4520 }
4521}
4522
4523static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4524{
4525 if (is_guest_mode(vcpu)) {
4526 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4527
4528 if (to_vmx(vcpu)->nested.nested_run_pending)
4529 return 0;
4530 if (nested_exit_on_nmi(vcpu)) {
4531 nested_vmx_vmexit(vcpu);
4532 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4533 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4534 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4535
4536
4537
4538
4539 vcpu->arch.nmi_pending = 0;
4540 vmx_set_nmi_mask(vcpu, true);
4541 return 0;
4542 }
4543 }
4544
4545 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4546 return 0;
4547
4548 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4549 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4550 | GUEST_INTR_STATE_NMI));
4551}
4552
4553static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4554{
4555 if (is_guest_mode(vcpu)) {
4556 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4557
4558 if (to_vmx(vcpu)->nested.nested_run_pending)
4559 return 0;
4560 if (nested_exit_on_intr(vcpu)) {
4561 nested_vmx_vmexit(vcpu);
4562 vmcs12->vm_exit_reason =
4563 EXIT_REASON_EXTERNAL_INTERRUPT;
4564 vmcs12->vm_exit_intr_info = 0;
4565
4566
4567
4568 }
4569 }
4570
4571 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4572 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4573 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4574}
4575
4576static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4577{
4578 int ret;
4579 struct kvm_userspace_memory_region tss_mem = {
4580 .slot = TSS_PRIVATE_MEMSLOT,
4581 .guest_phys_addr = addr,
4582 .memory_size = PAGE_SIZE * 3,
4583 .flags = 0,
4584 };
4585
4586 ret = kvm_set_memory_region(kvm, &tss_mem);
4587 if (ret)
4588 return ret;
4589 kvm->arch.tss_addr = addr;
4590 if (!init_rmode_tss(kvm))
4591 return -ENOMEM;
4592
4593 return 0;
4594}
4595
4596static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4597{
4598 switch (vec) {
4599 case BP_VECTOR:
4600
4601
4602
4603
4604 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4605 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4606 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4607 return false;
4608
4609 case DB_VECTOR:
4610 if (vcpu->guest_debug &
4611 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4612 return false;
4613
4614 case DE_VECTOR:
4615 case OF_VECTOR:
4616 case BR_VECTOR:
4617 case UD_VECTOR:
4618 case DF_VECTOR:
4619 case SS_VECTOR:
4620 case GP_VECTOR:
4621 case MF_VECTOR:
4622 return true;
4623 break;
4624 }
4625 return false;
4626}
4627
4628static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4629 int vec, u32 err_code)
4630{
4631
4632
4633
4634
4635 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4636 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4637 if (vcpu->arch.halt_request) {
4638 vcpu->arch.halt_request = 0;
4639 return kvm_emulate_halt(vcpu);
4640 }
4641 return 1;
4642 }
4643 return 0;
4644 }
4645
4646
4647
4648
4649
4650
4651 kvm_queue_exception(vcpu, vec);
4652 return 1;
4653}
4654
4655
4656
4657
4658
4659
4660
4661
4662static void kvm_machine_check(void)
4663{
4664#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4665 struct pt_regs regs = {
4666 .cs = 3,
4667 .flags = X86_EFLAGS_IF,
4668 };
4669
4670 do_machine_check(®s, 0);
4671#endif
4672}
4673
4674static int handle_machine_check(struct kvm_vcpu *vcpu)
4675{
4676
4677 return 1;
4678}
4679
4680static int handle_exception(struct kvm_vcpu *vcpu)
4681{
4682 struct vcpu_vmx *vmx = to_vmx(vcpu);
4683 struct kvm_run *kvm_run = vcpu->run;
4684 u32 intr_info, ex_no, error_code;
4685 unsigned long cr2, rip, dr6;
4686 u32 vect_info;
4687 enum emulation_result er;
4688
4689 vect_info = vmx->idt_vectoring_info;
4690 intr_info = vmx->exit_intr_info;
4691
4692 if (is_machine_check(intr_info))
4693 return handle_machine_check(vcpu);
4694
4695 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4696 return 1;
4697
4698 if (is_no_device(intr_info)) {
4699 vmx_fpu_activate(vcpu);
4700 return 1;
4701 }
4702
4703 if (is_invalid_opcode(intr_info)) {
4704 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4705 if (er != EMULATE_DONE)
4706 kvm_queue_exception(vcpu, UD_VECTOR);
4707 return 1;
4708 }
4709
4710 error_code = 0;
4711 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4712 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4713
4714
4715
4716
4717
4718
4719 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4720 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4721 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4722 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4723 vcpu->run->internal.ndata = 2;
4724 vcpu->run->internal.data[0] = vect_info;
4725 vcpu->run->internal.data[1] = intr_info;
4726 return 0;
4727 }
4728
4729 if (is_page_fault(intr_info)) {
4730
4731 BUG_ON(enable_ept);
4732 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4733 trace_kvm_page_fault(cr2, error_code);
4734
4735 if (kvm_event_needs_reinjection(vcpu))
4736 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4737 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4738 }
4739
4740 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4741
4742 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4743 return handle_rmode_exception(vcpu, ex_no, error_code);
4744
4745 switch (ex_no) {
4746 case DB_VECTOR:
4747 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4748 if (!(vcpu->guest_debug &
4749 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4750 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4751 kvm_queue_exception(vcpu, DB_VECTOR);
4752 return 1;
4753 }
4754 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4755 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4756
4757 case BP_VECTOR:
4758
4759
4760
4761
4762
4763 vmx->vcpu.arch.event_exit_inst_len =
4764 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4765 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4766 rip = kvm_rip_read(vcpu);
4767 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4768 kvm_run->debug.arch.exception = ex_no;
4769 break;
4770 default:
4771 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4772 kvm_run->ex.exception = ex_no;
4773 kvm_run->ex.error_code = error_code;
4774 break;
4775 }
4776 return 0;
4777}
4778
4779static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4780{
4781 ++vcpu->stat.irq_exits;
4782 return 1;
4783}
4784
4785static int handle_triple_fault(struct kvm_vcpu *vcpu)
4786{
4787 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4788 return 0;
4789}
4790
4791static int handle_io(struct kvm_vcpu *vcpu)
4792{
4793 unsigned long exit_qualification;
4794 int size, in, string;
4795 unsigned port;
4796
4797 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4798 string = (exit_qualification & 16) != 0;
4799 in = (exit_qualification & 8) != 0;
4800
4801 ++vcpu->stat.io_exits;
4802
4803 if (string || in)
4804 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4805
4806 port = exit_qualification >> 16;
4807 size = (exit_qualification & 7) + 1;
4808 skip_emulated_instruction(vcpu);
4809
4810 return kvm_fast_pio_out(vcpu, size, port);
4811}
4812
4813static void
4814vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4815{
4816
4817
4818
4819 hypercall[0] = 0x0f;
4820 hypercall[1] = 0x01;
4821 hypercall[2] = 0xc1;
4822}
4823
4824
4825static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4826{
4827 if (is_guest_mode(vcpu)) {
4828 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4829 unsigned long orig_val = val;
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839 val = (val & ~vmcs12->cr0_guest_host_mask) |
4840 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4841
4842
4843
4844 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4845 return 1;
4846
4847 if (kvm_set_cr0(vcpu, val))
4848 return 1;
4849 vmcs_writel(CR0_READ_SHADOW, orig_val);
4850 return 0;
4851 } else {
4852 if (to_vmx(vcpu)->nested.vmxon &&
4853 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4854 return 1;
4855 return kvm_set_cr0(vcpu, val);
4856 }
4857}
4858
4859static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4860{
4861 if (is_guest_mode(vcpu)) {
4862 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4863 unsigned long orig_val = val;
4864
4865
4866 val = (val & ~vmcs12->cr4_guest_host_mask) |
4867 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4868 if (kvm_set_cr4(vcpu, val))
4869 return 1;
4870 vmcs_writel(CR4_READ_SHADOW, orig_val);
4871 return 0;
4872 } else
4873 return kvm_set_cr4(vcpu, val);
4874}
4875
4876
4877static void handle_clts(struct kvm_vcpu *vcpu)
4878{
4879 if (is_guest_mode(vcpu)) {
4880
4881
4882
4883
4884
4885 vmcs_writel(CR0_READ_SHADOW,
4886 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4887 vcpu->arch.cr0 &= ~X86_CR0_TS;
4888 } else
4889 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4890}
4891
4892static int handle_cr(struct kvm_vcpu *vcpu)
4893{
4894 unsigned long exit_qualification, val;
4895 int cr;
4896 int reg;
4897 int err;
4898
4899 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4900 cr = exit_qualification & 15;
4901 reg = (exit_qualification >> 8) & 15;
4902 switch ((exit_qualification >> 4) & 3) {
4903 case 0:
4904 val = kvm_register_read(vcpu, reg);
4905 trace_kvm_cr_write(cr, val);
4906 switch (cr) {
4907 case 0:
4908 err = handle_set_cr0(vcpu, val);
4909 kvm_complete_insn_gp(vcpu, err);
4910 return 1;
4911 case 3:
4912 err = kvm_set_cr3(vcpu, val);
4913 kvm_complete_insn_gp(vcpu, err);
4914 return 1;
4915 case 4:
4916 err = handle_set_cr4(vcpu, val);
4917 kvm_complete_insn_gp(vcpu, err);
4918 return 1;
4919 case 8: {
4920 u8 cr8_prev = kvm_get_cr8(vcpu);
4921 u8 cr8 = kvm_register_read(vcpu, reg);
4922 err = kvm_set_cr8(vcpu, cr8);
4923 kvm_complete_insn_gp(vcpu, err);
4924 if (irqchip_in_kernel(vcpu->kvm))
4925 return 1;
4926 if (cr8_prev <= cr8)
4927 return 1;
4928 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4929 return 0;
4930 }
4931 }
4932 break;
4933 case 2:
4934 handle_clts(vcpu);
4935 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4936 skip_emulated_instruction(vcpu);
4937 vmx_fpu_activate(vcpu);
4938 return 1;
4939 case 1:
4940 switch (cr) {
4941 case 3:
4942 val = kvm_read_cr3(vcpu);
4943 kvm_register_write(vcpu, reg, val);
4944 trace_kvm_cr_read(cr, val);
4945 skip_emulated_instruction(vcpu);
4946 return 1;
4947 case 8:
4948 val = kvm_get_cr8(vcpu);
4949 kvm_register_write(vcpu, reg, val);
4950 trace_kvm_cr_read(cr, val);
4951 skip_emulated_instruction(vcpu);
4952 return 1;
4953 }
4954 break;
4955 case 3:
4956 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4957 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4958 kvm_lmsw(vcpu, val);
4959
4960 skip_emulated_instruction(vcpu);
4961 return 1;
4962 default:
4963 break;
4964 }
4965 vcpu->run->exit_reason = 0;
4966 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4967 (int)(exit_qualification >> 4) & 3, cr);
4968 return 0;
4969}
4970
4971static int handle_dr(struct kvm_vcpu *vcpu)
4972{
4973 unsigned long exit_qualification;
4974 int dr, reg;
4975
4976
4977 if (!kvm_require_cpl(vcpu, 0))
4978 return 1;
4979 dr = vmcs_readl(GUEST_DR7);
4980 if (dr & DR7_GD) {
4981
4982
4983
4984
4985
4986 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4987 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4988 vcpu->run->debug.arch.dr7 = dr;
4989 vcpu->run->debug.arch.pc =
4990 vmcs_readl(GUEST_CS_BASE) +
4991 vmcs_readl(GUEST_RIP);
4992 vcpu->run->debug.arch.exception = DB_VECTOR;
4993 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4994 return 0;
4995 } else {
4996 vcpu->arch.dr7 &= ~DR7_GD;
4997 vcpu->arch.dr6 |= DR6_BD;
4998 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4999 kvm_queue_exception(vcpu, DB_VECTOR);
5000 return 1;
5001 }
5002 }
5003
5004 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5005 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5006 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5007 if (exit_qualification & TYPE_MOV_FROM_DR) {
5008 unsigned long val;
5009 if (!kvm_get_dr(vcpu, dr, &val))
5010 kvm_register_write(vcpu, reg, val);
5011 } else
5012 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5013 skip_emulated_instruction(vcpu);
5014 return 1;
5015}
5016
5017static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5018{
5019 vmcs_writel(GUEST_DR7, val);
5020}
5021
5022static int handle_cpuid(struct kvm_vcpu *vcpu)
5023{
5024 kvm_emulate_cpuid(vcpu);
5025 return 1;
5026}
5027
5028static int handle_rdmsr(struct kvm_vcpu *vcpu)
5029{
5030 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5031 u64 data;
5032
5033 if (vmx_get_msr(vcpu, ecx, &data)) {
5034 trace_kvm_msr_read_ex(ecx);
5035 kvm_inject_gp(vcpu, 0);
5036 return 1;
5037 }
5038
5039 trace_kvm_msr_read(ecx, data);
5040
5041
5042 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5043 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5044 skip_emulated_instruction(vcpu);
5045 return 1;
5046}
5047
5048static int handle_wrmsr(struct kvm_vcpu *vcpu)
5049{
5050 struct msr_data msr;
5051 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5052 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5053 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5054
5055 msr.data = data;
5056 msr.index = ecx;
5057 msr.host_initiated = false;
5058 if (vmx_set_msr(vcpu, &msr) != 0) {
5059 trace_kvm_msr_write_ex(ecx, data);
5060 kvm_inject_gp(vcpu, 0);
5061 return 1;
5062 }
5063
5064 trace_kvm_msr_write(ecx, data);
5065 skip_emulated_instruction(vcpu);
5066 return 1;
5067}
5068
5069static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5070{
5071 kvm_make_request(KVM_REQ_EVENT, vcpu);
5072 return 1;
5073}
5074
5075static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5076{
5077 u32 cpu_based_vm_exec_control;
5078
5079
5080 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5081 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5082 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5083
5084 kvm_make_request(KVM_REQ_EVENT, vcpu);
5085
5086 ++vcpu->stat.irq_window_exits;
5087
5088
5089
5090
5091
5092 if (!irqchip_in_kernel(vcpu->kvm) &&
5093 vcpu->run->request_interrupt_window &&
5094 !kvm_cpu_has_interrupt(vcpu)) {
5095 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5096 return 0;
5097 }
5098 return 1;
5099}
5100
5101static int handle_halt(struct kvm_vcpu *vcpu)
5102{
5103 skip_emulated_instruction(vcpu);
5104 return kvm_emulate_halt(vcpu);
5105}
5106
5107static int handle_vmcall(struct kvm_vcpu *vcpu)
5108{
5109 skip_emulated_instruction(vcpu);
5110 kvm_emulate_hypercall(vcpu);
5111 return 1;
5112}
5113
5114static int handle_invd(struct kvm_vcpu *vcpu)
5115{
5116 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5117}
5118
5119static int handle_invlpg(struct kvm_vcpu *vcpu)
5120{
5121 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5122
5123 kvm_mmu_invlpg(vcpu, exit_qualification);
5124 skip_emulated_instruction(vcpu);
5125 return 1;
5126}
5127
5128static int handle_rdpmc(struct kvm_vcpu *vcpu)
5129{
5130 int err;
5131
5132 err = kvm_rdpmc(vcpu);
5133 kvm_complete_insn_gp(vcpu, err);
5134
5135 return 1;
5136}
5137
5138static int handle_wbinvd(struct kvm_vcpu *vcpu)
5139{
5140 skip_emulated_instruction(vcpu);
5141 kvm_emulate_wbinvd(vcpu);
5142 return 1;
5143}
5144
5145static int handle_xsetbv(struct kvm_vcpu *vcpu)
5146{
5147 u64 new_bv = kvm_read_edx_eax(vcpu);
5148 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5149
5150 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5151 skip_emulated_instruction(vcpu);
5152 return 1;
5153}
5154
5155static int handle_apic_access(struct kvm_vcpu *vcpu)
5156{
5157 if (likely(fasteoi)) {
5158 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5159 int access_type, offset;
5160
5161 access_type = exit_qualification & APIC_ACCESS_TYPE;
5162 offset = exit_qualification & APIC_ACCESS_OFFSET;
5163
5164
5165
5166
5167
5168 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5169 (offset == APIC_EOI)) {
5170 kvm_lapic_set_eoi(vcpu);
5171 skip_emulated_instruction(vcpu);
5172 return 1;
5173 }
5174 }
5175 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5176}
5177
5178static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5179{
5180 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5181 int vector = exit_qualification & 0xff;
5182
5183
5184 kvm_apic_set_eoi_accelerated(vcpu, vector);
5185 return 1;
5186}
5187
5188static int handle_apic_write(struct kvm_vcpu *vcpu)
5189{
5190 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5191 u32 offset = exit_qualification & 0xfff;
5192
5193
5194 kvm_apic_write_nodecode(vcpu, offset);
5195 return 1;
5196}
5197
5198static int handle_task_switch(struct kvm_vcpu *vcpu)
5199{
5200 struct vcpu_vmx *vmx = to_vmx(vcpu);
5201 unsigned long exit_qualification;
5202 bool has_error_code = false;
5203 u32 error_code = 0;
5204 u16 tss_selector;
5205 int reason, type, idt_v, idt_index;
5206
5207 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5208 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5209 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5210
5211 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5212
5213 reason = (u32)exit_qualification >> 30;
5214 if (reason == TASK_SWITCH_GATE && idt_v) {
5215 switch (type) {
5216 case INTR_TYPE_NMI_INTR:
5217 vcpu->arch.nmi_injected = false;
5218 vmx_set_nmi_mask(vcpu, true);
5219 break;
5220 case INTR_TYPE_EXT_INTR:
5221 case INTR_TYPE_SOFT_INTR:
5222 kvm_clear_interrupt_queue(vcpu);
5223 break;
5224 case INTR_TYPE_HARD_EXCEPTION:
5225 if (vmx->idt_vectoring_info &
5226 VECTORING_INFO_DELIVER_CODE_MASK) {
5227 has_error_code = true;
5228 error_code =
5229 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5230 }
5231
5232 case INTR_TYPE_SOFT_EXCEPTION:
5233 kvm_clear_exception_queue(vcpu);
5234 break;
5235 default:
5236 break;
5237 }
5238 }
5239 tss_selector = exit_qualification;
5240
5241 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5242 type != INTR_TYPE_EXT_INTR &&
5243 type != INTR_TYPE_NMI_INTR))
5244 skip_emulated_instruction(vcpu);
5245
5246 if (kvm_task_switch(vcpu, tss_selector,
5247 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5248 has_error_code, error_code) == EMULATE_FAIL) {
5249 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5250 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5251 vcpu->run->internal.ndata = 0;
5252 return 0;
5253 }
5254
5255
5256 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5257
5258
5259
5260
5261
5262
5263 return 1;
5264}
5265
5266static int handle_ept_violation(struct kvm_vcpu *vcpu)
5267{
5268 unsigned long exit_qualification;
5269 gpa_t gpa;
5270 u32 error_code;
5271 int gla_validity;
5272
5273 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5274
5275 gla_validity = (exit_qualification >> 7) & 0x3;
5276 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5277 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5278 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5279 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5280 vmcs_readl(GUEST_LINEAR_ADDRESS));
5281 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5282 (long unsigned int)exit_qualification);
5283 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5284 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5285 return 0;
5286 }
5287
5288 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5289 trace_kvm_page_fault(gpa, exit_qualification);
5290
5291
5292 error_code = exit_qualification & (1U << 1);
5293
5294 error_code |= (exit_qualification >> 3) & 0x1;
5295
5296 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5297}
5298
5299static u64 ept_rsvd_mask(u64 spte, int level)
5300{
5301 int i;
5302 u64 mask = 0;
5303
5304 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5305 mask |= (1ULL << i);
5306
5307 if (level > 2)
5308
5309 mask |= 0xf8;
5310 else if (level == 2) {
5311 if (spte & (1ULL << 7))
5312
5313 mask |= 0x1ff000;
5314 else
5315
5316 mask |= 0x78;
5317 }
5318
5319 return mask;
5320}
5321
5322static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5323 int level)
5324{
5325 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5326
5327
5328 WARN_ON((spte & 0x7) == 0x2);
5329
5330
5331 WARN_ON((spte & 0x7) == 0x6);
5332
5333
5334 if (!cpu_has_vmx_ept_execute_only())
5335 WARN_ON((spte & 0x7) == 0x4);
5336
5337
5338 if ((spte & 0x7)) {
5339 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5340
5341 if (rsvd_bits != 0) {
5342 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5343 __func__, rsvd_bits);
5344 WARN_ON(1);
5345 }
5346
5347 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5348 u64 ept_mem_type = (spte & 0x38) >> 3;
5349
5350 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5351 ept_mem_type == 7) {
5352 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5353 __func__, ept_mem_type);
5354 WARN_ON(1);
5355 }
5356 }
5357 }
5358}
5359
5360static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5361{
5362 u64 sptes[4];
5363 int nr_sptes, i, ret;
5364 gpa_t gpa;
5365
5366 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5367
5368 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5369 if (likely(ret == 1))
5370 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5371 EMULATE_DONE;
5372 if (unlikely(!ret))
5373 return 1;
5374
5375
5376 printk(KERN_ERR "EPT: Misconfiguration.\n");
5377 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5378
5379 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5380
5381 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5382 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5383
5384 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5385 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5386
5387 return 0;
5388}
5389
5390static int handle_nmi_window(struct kvm_vcpu *vcpu)
5391{
5392 u32 cpu_based_vm_exec_control;
5393
5394
5395 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5396 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5397 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5398 ++vcpu->stat.nmi_window_exits;
5399 kvm_make_request(KVM_REQ_EVENT, vcpu);
5400
5401 return 1;
5402}
5403
5404static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5405{
5406 struct vcpu_vmx *vmx = to_vmx(vcpu);
5407 enum emulation_result err = EMULATE_DONE;
5408 int ret = 1;
5409 u32 cpu_exec_ctrl;
5410 bool intr_window_requested;
5411 unsigned count = 130;
5412
5413 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5414 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5415
5416 while (!guest_state_valid(vcpu) && count-- != 0) {
5417 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5418 return handle_interrupt_window(&vmx->vcpu);
5419
5420 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5421 return 1;
5422
5423 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5424
5425 if (err == EMULATE_DO_MMIO) {
5426 ret = 0;
5427 goto out;
5428 }
5429
5430 if (err != EMULATE_DONE) {
5431 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5432 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5433 vcpu->run->internal.ndata = 0;
5434 return 0;
5435 }
5436
5437 if (vcpu->arch.halt_request) {
5438 vcpu->arch.halt_request = 0;
5439 ret = kvm_emulate_halt(vcpu);
5440 goto out;
5441 }
5442
5443 if (signal_pending(current))
5444 goto out;
5445 if (need_resched())
5446 schedule();
5447 }
5448
5449 vmx->emulation_required = emulation_required(vcpu);
5450out:
5451 return ret;
5452}
5453
5454
5455
5456
5457
5458static int handle_pause(struct kvm_vcpu *vcpu)
5459{
5460 skip_emulated_instruction(vcpu);
5461 kvm_vcpu_on_spin(vcpu);
5462
5463 return 1;
5464}
5465
5466static int handle_invalid_op(struct kvm_vcpu *vcpu)
5467{
5468 kvm_queue_exception(vcpu, UD_VECTOR);
5469 return 1;
5470}
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5487{
5488 struct vmcs02_list *item;
5489 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5490 if (item->vmptr == vmx->nested.current_vmptr) {
5491 list_move(&item->list, &vmx->nested.vmcs02_pool);
5492 return &item->vmcs02;
5493 }
5494
5495 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5496
5497 item = list_entry(vmx->nested.vmcs02_pool.prev,
5498 struct vmcs02_list, list);
5499 item->vmptr = vmx->nested.current_vmptr;
5500 list_move(&item->list, &vmx->nested.vmcs02_pool);
5501 return &item->vmcs02;
5502 }
5503
5504
5505 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5506 if (!item)
5507 return NULL;
5508 item->vmcs02.vmcs = alloc_vmcs();
5509 if (!item->vmcs02.vmcs) {
5510 kfree(item);
5511 return NULL;
5512 }
5513 loaded_vmcs_init(&item->vmcs02);
5514 item->vmptr = vmx->nested.current_vmptr;
5515 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5516 vmx->nested.vmcs02_num++;
5517 return &item->vmcs02;
5518}
5519
5520
5521static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5522{
5523 struct vmcs02_list *item;
5524 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5525 if (item->vmptr == vmptr) {
5526 free_loaded_vmcs(&item->vmcs02);
5527 list_del(&item->list);
5528 kfree(item);
5529 vmx->nested.vmcs02_num--;
5530 return;
5531 }
5532}
5533
5534
5535
5536
5537
5538
5539static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5540{
5541 struct vmcs02_list *item, *n;
5542 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5543 if (vmx->loaded_vmcs != &item->vmcs02)
5544 free_loaded_vmcs(&item->vmcs02);
5545 list_del(&item->list);
5546 kfree(item);
5547 }
5548 vmx->nested.vmcs02_num = 0;
5549
5550 if (vmx->loaded_vmcs != &vmx->vmcs01)
5551 free_loaded_vmcs(&vmx->vmcs01);
5552}
5553
5554static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5555 u32 vm_instruction_error);
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565static int handle_vmon(struct kvm_vcpu *vcpu)
5566{
5567 struct kvm_segment cs;
5568 struct vcpu_vmx *vmx = to_vmx(vcpu);
5569 struct vmcs *shadow_vmcs;
5570
5571
5572
5573
5574
5575
5576 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5577 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5578 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5579 kvm_queue_exception(vcpu, UD_VECTOR);
5580 return 1;
5581 }
5582
5583 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5584 if (is_long_mode(vcpu) && !cs.l) {
5585 kvm_queue_exception(vcpu, UD_VECTOR);
5586 return 1;
5587 }
5588
5589 if (vmx_get_cpl(vcpu)) {
5590 kvm_inject_gp(vcpu, 0);
5591 return 1;
5592 }
5593 if (vmx->nested.vmxon) {
5594 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5595 skip_emulated_instruction(vcpu);
5596 return 1;
5597 }
5598 if (enable_shadow_vmcs) {
5599 shadow_vmcs = alloc_vmcs();
5600 if (!shadow_vmcs)
5601 return -ENOMEM;
5602
5603 shadow_vmcs->revision_id |= (1u << 31);
5604
5605 vmcs_clear(shadow_vmcs);
5606 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5607 }
5608
5609 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5610 vmx->nested.vmcs02_num = 0;
5611
5612 vmx->nested.vmxon = true;
5613
5614 skip_emulated_instruction(vcpu);
5615 return 1;
5616}
5617
5618
5619
5620
5621
5622
5623static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5624{
5625 struct kvm_segment cs;
5626 struct vcpu_vmx *vmx = to_vmx(vcpu);
5627
5628 if (!vmx->nested.vmxon) {
5629 kvm_queue_exception(vcpu, UD_VECTOR);
5630 return 0;
5631 }
5632
5633 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5634 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5635 (is_long_mode(vcpu) && !cs.l)) {
5636 kvm_queue_exception(vcpu, UD_VECTOR);
5637 return 0;
5638 }
5639
5640 if (vmx_get_cpl(vcpu)) {
5641 kvm_inject_gp(vcpu, 0);
5642 return 0;
5643 }
5644
5645 return 1;
5646}
5647
5648static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5649{
5650 u32 exec_control;
5651 if (enable_shadow_vmcs) {
5652 if (vmx->nested.current_vmcs12 != NULL) {
5653
5654
5655 copy_shadow_to_vmcs12(vmx);
5656 vmx->nested.sync_shadow_vmcs = false;
5657 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5658 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5659 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5660 vmcs_write64(VMCS_LINK_POINTER, -1ull);
5661 }
5662 }
5663 kunmap(vmx->nested.current_vmcs12_page);
5664 nested_release_page(vmx->nested.current_vmcs12_page);
5665}
5666
5667
5668
5669
5670
5671static void free_nested(struct vcpu_vmx *vmx)
5672{
5673 if (!vmx->nested.vmxon)
5674 return;
5675 vmx->nested.vmxon = false;
5676 if (vmx->nested.current_vmptr != -1ull) {
5677 nested_release_vmcs12(vmx);
5678 vmx->nested.current_vmptr = -1ull;
5679 vmx->nested.current_vmcs12 = NULL;
5680 }
5681 if (enable_shadow_vmcs)
5682 free_vmcs(vmx->nested.current_shadow_vmcs);
5683
5684 if (vmx->nested.apic_access_page) {
5685 nested_release_page(vmx->nested.apic_access_page);
5686 vmx->nested.apic_access_page = 0;
5687 }
5688
5689 nested_free_all_saved_vmcss(vmx);
5690}
5691
5692
5693static int handle_vmoff(struct kvm_vcpu *vcpu)
5694{
5695 if (!nested_vmx_check_permission(vcpu))
5696 return 1;
5697 free_nested(to_vmx(vcpu));
5698 skip_emulated_instruction(vcpu);
5699 return 1;
5700}
5701
5702
5703
5704
5705
5706
5707
5708static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5709 unsigned long exit_qualification,
5710 u32 vmx_instruction_info, gva_t *ret)
5711{
5712
5713
5714
5715
5716
5717
5718
5719
5720 int scaling = vmx_instruction_info & 3;
5721 int addr_size = (vmx_instruction_info >> 7) & 7;
5722 bool is_reg = vmx_instruction_info & (1u << 10);
5723 int seg_reg = (vmx_instruction_info >> 15) & 7;
5724 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5725 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5726 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5727 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5728
5729 if (is_reg) {
5730 kvm_queue_exception(vcpu, UD_VECTOR);
5731 return 1;
5732 }
5733
5734
5735
5736 *ret = vmx_get_segment_base(vcpu, seg_reg);
5737 if (base_is_valid)
5738 *ret += kvm_register_read(vcpu, base_reg);
5739 if (index_is_valid)
5740 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5741 *ret += exit_qualification;
5742
5743 if (addr_size == 1)
5744 *ret &= 0xffffffff;
5745
5746
5747
5748
5749
5750
5751
5752 return 0;
5753}
5754
5755
5756
5757
5758
5759
5760static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5761{
5762 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5763 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5764 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5765}
5766
5767static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5768{
5769 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5770 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5771 X86_EFLAGS_SF | X86_EFLAGS_OF))
5772 | X86_EFLAGS_CF);
5773}
5774
5775static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5776 u32 vm_instruction_error)
5777{
5778 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5779
5780
5781
5782
5783 nested_vmx_failInvalid(vcpu);
5784 return;
5785 }
5786 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5787 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5788 X86_EFLAGS_SF | X86_EFLAGS_OF))
5789 | X86_EFLAGS_ZF);
5790 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5791
5792
5793
5794
5795}
5796
5797
5798static int handle_vmclear(struct kvm_vcpu *vcpu)
5799{
5800 struct vcpu_vmx *vmx = to_vmx(vcpu);
5801 gva_t gva;
5802 gpa_t vmptr;
5803 struct vmcs12 *vmcs12;
5804 struct page *page;
5805 struct x86_exception e;
5806
5807 if (!nested_vmx_check_permission(vcpu))
5808 return 1;
5809
5810 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5811 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5812 return 1;
5813
5814 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5815 sizeof(vmptr), &e)) {
5816 kvm_inject_page_fault(vcpu, &e);
5817 return 1;
5818 }
5819
5820 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5821 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5822 skip_emulated_instruction(vcpu);
5823 return 1;
5824 }
5825
5826 if (vmptr == vmx->nested.current_vmptr) {
5827 nested_release_vmcs12(vmx);
5828 vmx->nested.current_vmptr = -1ull;
5829 vmx->nested.current_vmcs12 = NULL;
5830 }
5831
5832 page = nested_get_page(vcpu, vmptr);
5833 if (page == NULL) {
5834
5835
5836
5837
5838
5839
5840
5841 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5842 return 1;
5843 }
5844 vmcs12 = kmap(page);
5845 vmcs12->launch_state = 0;
5846 kunmap(page);
5847 nested_release_page(page);
5848
5849 nested_free_vmcs02(vmx, vmptr);
5850
5851 skip_emulated_instruction(vcpu);
5852 nested_vmx_succeed(vcpu);
5853 return 1;
5854}
5855
5856static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5857
5858
5859static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5860{
5861 return nested_vmx_run(vcpu, true);
5862}
5863
5864
5865static int handle_vmresume(struct kvm_vcpu *vcpu)
5866{
5867
5868 return nested_vmx_run(vcpu, false);
5869}
5870
5871enum vmcs_field_type {
5872 VMCS_FIELD_TYPE_U16 = 0,
5873 VMCS_FIELD_TYPE_U64 = 1,
5874 VMCS_FIELD_TYPE_U32 = 2,
5875 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5876};
5877
5878static inline int vmcs_field_type(unsigned long field)
5879{
5880 if (0x1 & field)
5881 return VMCS_FIELD_TYPE_U32;
5882 return (field >> 13) & 0x3 ;
5883}
5884
5885static inline int vmcs_field_readonly(unsigned long field)
5886{
5887 return (((field >> 10) & 0x3) == 1);
5888}
5889
5890
5891
5892
5893
5894
5895
5896
5897static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5898 unsigned long field, u64 *ret)
5899{
5900 short offset = vmcs_field_to_offset(field);
5901 char *p;
5902
5903 if (offset < 0)
5904 return 0;
5905
5906 p = ((char *)(get_vmcs12(vcpu))) + offset;
5907
5908 switch (vmcs_field_type(field)) {
5909 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5910 *ret = *((natural_width *)p);
5911 return 1;
5912 case VMCS_FIELD_TYPE_U16:
5913 *ret = *((u16 *)p);
5914 return 1;
5915 case VMCS_FIELD_TYPE_U32:
5916 *ret = *((u32 *)p);
5917 return 1;
5918 case VMCS_FIELD_TYPE_U64:
5919 *ret = *((u64 *)p);
5920 return 1;
5921 default:
5922 return 0;
5923 }
5924}
5925
5926
5927static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5928 unsigned long field, u64 field_value){
5929 short offset = vmcs_field_to_offset(field);
5930 char *p = ((char *) get_vmcs12(vcpu)) + offset;
5931 if (offset < 0)
5932 return false;
5933
5934 switch (vmcs_field_type(field)) {
5935 case VMCS_FIELD_TYPE_U16:
5936 *(u16 *)p = field_value;
5937 return true;
5938 case VMCS_FIELD_TYPE_U32:
5939 *(u32 *)p = field_value;
5940 return true;
5941 case VMCS_FIELD_TYPE_U64:
5942 *(u64 *)p = field_value;
5943 return true;
5944 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5945 *(natural_width *)p = field_value;
5946 return true;
5947 default:
5948 return false;
5949 }
5950
5951}
5952
5953static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
5954{
5955 int i;
5956 unsigned long field;
5957 u64 field_value;
5958 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
5959 unsigned long *fields = (unsigned long *)shadow_read_write_fields;
5960 int num_fields = max_shadow_read_write_fields;
5961
5962 vmcs_load(shadow_vmcs);
5963
5964 for (i = 0; i < num_fields; i++) {
5965 field = fields[i];
5966 switch (vmcs_field_type(field)) {
5967 case VMCS_FIELD_TYPE_U16:
5968 field_value = vmcs_read16(field);
5969 break;
5970 case VMCS_FIELD_TYPE_U32:
5971 field_value = vmcs_read32(field);
5972 break;
5973 case VMCS_FIELD_TYPE_U64:
5974 field_value = vmcs_read64(field);
5975 break;
5976 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5977 field_value = vmcs_readl(field);
5978 break;
5979 }
5980 vmcs12_write_any(&vmx->vcpu, field, field_value);
5981 }
5982
5983 vmcs_clear(shadow_vmcs);
5984 vmcs_load(vmx->loaded_vmcs->vmcs);
5985}
5986
5987static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
5988{
5989 unsigned long *fields[] = {
5990 (unsigned long *)shadow_read_write_fields,
5991 (unsigned long *)shadow_read_only_fields
5992 };
5993 int num_lists = ARRAY_SIZE(fields);
5994 int max_fields[] = {
5995 max_shadow_read_write_fields,
5996 max_shadow_read_only_fields
5997 };
5998 int i, q;
5999 unsigned long field;
6000 u64 field_value = 0;
6001 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6002
6003 vmcs_load(shadow_vmcs);
6004
6005 for (q = 0; q < num_lists; q++) {
6006 for (i = 0; i < max_fields[q]; i++) {
6007 field = fields[q][i];
6008 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6009
6010 switch (vmcs_field_type(field)) {
6011 case VMCS_FIELD_TYPE_U16:
6012 vmcs_write16(field, (u16)field_value);
6013 break;
6014 case VMCS_FIELD_TYPE_U32:
6015 vmcs_write32(field, (u32)field_value);
6016 break;
6017 case VMCS_FIELD_TYPE_U64:
6018 vmcs_write64(field, (u64)field_value);
6019 break;
6020 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6021 vmcs_writel(field, (long)field_value);
6022 break;
6023 }
6024 }
6025 }
6026
6027 vmcs_clear(shadow_vmcs);
6028 vmcs_load(vmx->loaded_vmcs->vmcs);
6029}
6030
6031
6032
6033
6034
6035static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6036{
6037 struct vcpu_vmx *vmx = to_vmx(vcpu);
6038 if (vmx->nested.current_vmptr == -1ull) {
6039 nested_vmx_failInvalid(vcpu);
6040 skip_emulated_instruction(vcpu);
6041 return 0;
6042 }
6043 return 1;
6044}
6045
6046static int handle_vmread(struct kvm_vcpu *vcpu)
6047{
6048 unsigned long field;
6049 u64 field_value;
6050 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6051 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6052 gva_t gva = 0;
6053
6054 if (!nested_vmx_check_permission(vcpu) ||
6055 !nested_vmx_check_vmcs12(vcpu))
6056 return 1;
6057
6058
6059 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6060
6061 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6062 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6063 skip_emulated_instruction(vcpu);
6064 return 1;
6065 }
6066
6067
6068
6069
6070
6071 if (vmx_instruction_info & (1u << 10)) {
6072 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6073 field_value);
6074 } else {
6075 if (get_vmx_mem_address(vcpu, exit_qualification,
6076 vmx_instruction_info, &gva))
6077 return 1;
6078
6079 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6080 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6081 }
6082
6083 nested_vmx_succeed(vcpu);
6084 skip_emulated_instruction(vcpu);
6085 return 1;
6086}
6087
6088
6089static int handle_vmwrite(struct kvm_vcpu *vcpu)
6090{
6091 unsigned long field;
6092 gva_t gva;
6093 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6094 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6095
6096
6097
6098
6099
6100
6101 u64 field_value = 0;
6102 struct x86_exception e;
6103
6104 if (!nested_vmx_check_permission(vcpu) ||
6105 !nested_vmx_check_vmcs12(vcpu))
6106 return 1;
6107
6108 if (vmx_instruction_info & (1u << 10))
6109 field_value = kvm_register_read(vcpu,
6110 (((vmx_instruction_info) >> 3) & 0xf));
6111 else {
6112 if (get_vmx_mem_address(vcpu, exit_qualification,
6113 vmx_instruction_info, &gva))
6114 return 1;
6115 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6116 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6117 kvm_inject_page_fault(vcpu, &e);
6118 return 1;
6119 }
6120 }
6121
6122
6123 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6124 if (vmcs_field_readonly(field)) {
6125 nested_vmx_failValid(vcpu,
6126 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6127 skip_emulated_instruction(vcpu);
6128 return 1;
6129 }
6130
6131 if (!vmcs12_write_any(vcpu, field, field_value)) {
6132 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6133 skip_emulated_instruction(vcpu);
6134 return 1;
6135 }
6136
6137 nested_vmx_succeed(vcpu);
6138 skip_emulated_instruction(vcpu);
6139 return 1;
6140}
6141
6142
6143static int handle_vmptrld(struct kvm_vcpu *vcpu)
6144{
6145 struct vcpu_vmx *vmx = to_vmx(vcpu);
6146 gva_t gva;
6147 gpa_t vmptr;
6148 struct x86_exception e;
6149 u32 exec_control;
6150
6151 if (!nested_vmx_check_permission(vcpu))
6152 return 1;
6153
6154 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6155 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6156 return 1;
6157
6158 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6159 sizeof(vmptr), &e)) {
6160 kvm_inject_page_fault(vcpu, &e);
6161 return 1;
6162 }
6163
6164 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6165 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6166 skip_emulated_instruction(vcpu);
6167 return 1;
6168 }
6169
6170 if (vmx->nested.current_vmptr != vmptr) {
6171 struct vmcs12 *new_vmcs12;
6172 struct page *page;
6173 page = nested_get_page(vcpu, vmptr);
6174 if (page == NULL) {
6175 nested_vmx_failInvalid(vcpu);
6176 skip_emulated_instruction(vcpu);
6177 return 1;
6178 }
6179 new_vmcs12 = kmap(page);
6180 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6181 kunmap(page);
6182 nested_release_page_clean(page);
6183 nested_vmx_failValid(vcpu,
6184 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6185 skip_emulated_instruction(vcpu);
6186 return 1;
6187 }
6188 if (vmx->nested.current_vmptr != -1ull)
6189 nested_release_vmcs12(vmx);
6190
6191 vmx->nested.current_vmptr = vmptr;
6192 vmx->nested.current_vmcs12 = new_vmcs12;
6193 vmx->nested.current_vmcs12_page = page;
6194 if (enable_shadow_vmcs) {
6195 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6196 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6197 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6198 vmcs_write64(VMCS_LINK_POINTER,
6199 __pa(vmx->nested.current_shadow_vmcs));
6200 vmx->nested.sync_shadow_vmcs = true;
6201 }
6202 }
6203
6204 nested_vmx_succeed(vcpu);
6205 skip_emulated_instruction(vcpu);
6206 return 1;
6207}
6208
6209
6210static int handle_vmptrst(struct kvm_vcpu *vcpu)
6211{
6212 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6213 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6214 gva_t vmcs_gva;
6215 struct x86_exception e;
6216
6217 if (!nested_vmx_check_permission(vcpu))
6218 return 1;
6219
6220 if (get_vmx_mem_address(vcpu, exit_qualification,
6221 vmx_instruction_info, &vmcs_gva))
6222 return 1;
6223
6224 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6225 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6226 sizeof(u64), &e)) {
6227 kvm_inject_page_fault(vcpu, &e);
6228 return 1;
6229 }
6230 nested_vmx_succeed(vcpu);
6231 skip_emulated_instruction(vcpu);
6232 return 1;
6233}
6234
6235
6236
6237
6238
6239
6240static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6241 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6242 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
6243 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6244 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6245 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6246 [EXIT_REASON_CR_ACCESS] = handle_cr,
6247 [EXIT_REASON_DR_ACCESS] = handle_dr,
6248 [EXIT_REASON_CPUID] = handle_cpuid,
6249 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6250 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6251 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6252 [EXIT_REASON_HLT] = handle_halt,
6253 [EXIT_REASON_INVD] = handle_invd,
6254 [EXIT_REASON_INVLPG] = handle_invlpg,
6255 [EXIT_REASON_RDPMC] = handle_rdpmc,
6256 [EXIT_REASON_VMCALL] = handle_vmcall,
6257 [EXIT_REASON_VMCLEAR] = handle_vmclear,
6258 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
6259 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6260 [EXIT_REASON_VMPTRST] = handle_vmptrst,
6261 [EXIT_REASON_VMREAD] = handle_vmread,
6262 [EXIT_REASON_VMRESUME] = handle_vmresume,
6263 [EXIT_REASON_VMWRITE] = handle_vmwrite,
6264 [EXIT_REASON_VMOFF] = handle_vmoff,
6265 [EXIT_REASON_VMON] = handle_vmon,
6266 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6267 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
6268 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
6269 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
6270 [EXIT_REASON_WBINVD] = handle_wbinvd,
6271 [EXIT_REASON_XSETBV] = handle_xsetbv,
6272 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
6273 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
6274 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6275 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
6276 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
6277 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6278 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6279};
6280
6281static const int kvm_vmx_max_exit_handlers =
6282 ARRAY_SIZE(kvm_vmx_exit_handlers);
6283
6284static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6285 struct vmcs12 *vmcs12)
6286{
6287 unsigned long exit_qualification;
6288 gpa_t bitmap, last_bitmap;
6289 unsigned int port;
6290 int size;
6291 u8 b;
6292
6293 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6294 return 1;
6295
6296 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6297 return 0;
6298
6299 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6300
6301 port = exit_qualification >> 16;
6302 size = (exit_qualification & 7) + 1;
6303
6304 last_bitmap = (gpa_t)-1;
6305 b = -1;
6306
6307 while (size > 0) {
6308 if (port < 0x8000)
6309 bitmap = vmcs12->io_bitmap_a;
6310 else if (port < 0x10000)
6311 bitmap = vmcs12->io_bitmap_b;
6312 else
6313 return 1;
6314 bitmap += (port & 0x7fff) / 8;
6315
6316 if (last_bitmap != bitmap)
6317 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6318 return 1;
6319 if (b & (1 << (port & 7)))
6320 return 1;
6321
6322 port++;
6323 size--;
6324 last_bitmap = bitmap;
6325 }
6326
6327 return 0;
6328}
6329
6330
6331
6332
6333
6334
6335
6336static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6337 struct vmcs12 *vmcs12, u32 exit_reason)
6338{
6339 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6340 gpa_t bitmap;
6341
6342 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6343 return 1;
6344
6345
6346
6347
6348
6349
6350 bitmap = vmcs12->msr_bitmap;
6351 if (exit_reason == EXIT_REASON_MSR_WRITE)
6352 bitmap += 2048;
6353 if (msr_index >= 0xc0000000) {
6354 msr_index -= 0xc0000000;
6355 bitmap += 1024;
6356 }
6357
6358
6359 if (msr_index < 1024*8) {
6360 unsigned char b;
6361 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6362 return 1;
6363 return 1 & (b >> (msr_index & 7));
6364 } else
6365 return 1;
6366}
6367
6368
6369
6370
6371
6372
6373static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6374 struct vmcs12 *vmcs12)
6375{
6376 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6377 int cr = exit_qualification & 15;
6378 int reg = (exit_qualification >> 8) & 15;
6379 unsigned long val = kvm_register_read(vcpu, reg);
6380
6381 switch ((exit_qualification >> 4) & 3) {
6382 case 0:
6383 switch (cr) {
6384 case 0:
6385 if (vmcs12->cr0_guest_host_mask &
6386 (val ^ vmcs12->cr0_read_shadow))
6387 return 1;
6388 break;
6389 case 3:
6390 if ((vmcs12->cr3_target_count >= 1 &&
6391 vmcs12->cr3_target_value0 == val) ||
6392 (vmcs12->cr3_target_count >= 2 &&
6393 vmcs12->cr3_target_value1 == val) ||
6394 (vmcs12->cr3_target_count >= 3 &&
6395 vmcs12->cr3_target_value2 == val) ||
6396 (vmcs12->cr3_target_count >= 4 &&
6397 vmcs12->cr3_target_value3 == val))
6398 return 0;
6399 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6400 return 1;
6401 break;
6402 case 4:
6403 if (vmcs12->cr4_guest_host_mask &
6404 (vmcs12->cr4_read_shadow ^ val))
6405 return 1;
6406 break;
6407 case 8:
6408 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6409 return 1;
6410 break;
6411 }
6412 break;
6413 case 2:
6414 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6415 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6416 return 1;
6417 break;
6418 case 1:
6419 switch (cr) {
6420 case 3:
6421 if (vmcs12->cpu_based_vm_exec_control &
6422 CPU_BASED_CR3_STORE_EXITING)
6423 return 1;
6424 break;
6425 case 8:
6426 if (vmcs12->cpu_based_vm_exec_control &
6427 CPU_BASED_CR8_STORE_EXITING)
6428 return 1;
6429 break;
6430 }
6431 break;
6432 case 3:
6433
6434
6435
6436
6437 if (vmcs12->cr0_guest_host_mask & 0xe &
6438 (val ^ vmcs12->cr0_read_shadow))
6439 return 1;
6440 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6441 !(vmcs12->cr0_read_shadow & 0x1) &&
6442 (val & 0x1))
6443 return 1;
6444 break;
6445 }
6446 return 0;
6447}
6448
6449
6450
6451
6452
6453
6454static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6455{
6456 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6457 struct vcpu_vmx *vmx = to_vmx(vcpu);
6458 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6459 u32 exit_reason = vmx->exit_reason;
6460
6461 if (vmx->nested.nested_run_pending)
6462 return 0;
6463
6464 if (unlikely(vmx->fail)) {
6465 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6466 vmcs_read32(VM_INSTRUCTION_ERROR));
6467 return 1;
6468 }
6469
6470 switch (exit_reason) {
6471 case EXIT_REASON_EXCEPTION_NMI:
6472 if (!is_exception(intr_info))
6473 return 0;
6474 else if (is_page_fault(intr_info))
6475 return enable_ept;
6476 return vmcs12->exception_bitmap &
6477 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6478 case EXIT_REASON_EXTERNAL_INTERRUPT:
6479 return 0;
6480 case EXIT_REASON_TRIPLE_FAULT:
6481 return 1;
6482 case EXIT_REASON_PENDING_INTERRUPT:
6483 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6484 case EXIT_REASON_NMI_WINDOW:
6485 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6486 case EXIT_REASON_TASK_SWITCH:
6487 return 1;
6488 case EXIT_REASON_CPUID:
6489 return 1;
6490 case EXIT_REASON_HLT:
6491 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6492 case EXIT_REASON_INVD:
6493 return 1;
6494 case EXIT_REASON_INVLPG:
6495 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6496 case EXIT_REASON_RDPMC:
6497 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6498 case EXIT_REASON_RDTSC:
6499 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6500 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6501 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6502 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6503 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6504 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6505
6506
6507
6508
6509 return 1;
6510 case EXIT_REASON_CR_ACCESS:
6511 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6512 case EXIT_REASON_DR_ACCESS:
6513 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6514 case EXIT_REASON_IO_INSTRUCTION:
6515 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6516 case EXIT_REASON_MSR_READ:
6517 case EXIT_REASON_MSR_WRITE:
6518 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6519 case EXIT_REASON_INVALID_STATE:
6520 return 1;
6521 case EXIT_REASON_MWAIT_INSTRUCTION:
6522 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6523 case EXIT_REASON_MONITOR_INSTRUCTION:
6524 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6525 case EXIT_REASON_PAUSE_INSTRUCTION:
6526 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6527 nested_cpu_has2(vmcs12,
6528 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6529 case EXIT_REASON_MCE_DURING_VMENTRY:
6530 return 0;
6531 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6532 return 1;
6533 case EXIT_REASON_APIC_ACCESS:
6534 return nested_cpu_has2(vmcs12,
6535 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6536 case EXIT_REASON_EPT_VIOLATION:
6537 case EXIT_REASON_EPT_MISCONFIG:
6538 return 0;
6539 case EXIT_REASON_PREEMPTION_TIMER:
6540 return vmcs12->pin_based_vm_exec_control &
6541 PIN_BASED_VMX_PREEMPTION_TIMER;
6542 case EXIT_REASON_WBINVD:
6543 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6544 case EXIT_REASON_XSETBV:
6545 return 1;
6546 default:
6547 return 1;
6548 }
6549}
6550
6551static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6552{
6553 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6554 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6555}
6556
6557
6558
6559
6560
6561static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6562{
6563 struct vcpu_vmx *vmx = to_vmx(vcpu);
6564 u32 exit_reason = vmx->exit_reason;
6565 u32 vectoring_info = vmx->idt_vectoring_info;
6566
6567
6568 if (vmx->emulation_required)
6569 return handle_invalid_guest_state(vcpu);
6570
6571
6572
6573
6574
6575
6576 if (vmx->nested.nested_run_pending)
6577 kvm_make_request(KVM_REQ_EVENT, vcpu);
6578
6579 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6580 exit_reason == EXIT_REASON_VMRESUME))
6581 vmx->nested.nested_run_pending = 1;
6582 else
6583 vmx->nested.nested_run_pending = 0;
6584
6585 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6586 nested_vmx_vmexit(vcpu);
6587 return 1;
6588 }
6589
6590 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6591 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6592 vcpu->run->fail_entry.hardware_entry_failure_reason
6593 = exit_reason;
6594 return 0;
6595 }
6596
6597 if (unlikely(vmx->fail)) {
6598 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6599 vcpu->run->fail_entry.hardware_entry_failure_reason
6600 = vmcs_read32(VM_INSTRUCTION_ERROR);
6601 return 0;
6602 }
6603
6604
6605
6606
6607
6608
6609
6610
6611 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6612 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6613 exit_reason != EXIT_REASON_EPT_VIOLATION &&
6614 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6615 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6616 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6617 vcpu->run->internal.ndata = 2;
6618 vcpu->run->internal.data[0] = vectoring_info;
6619 vcpu->run->internal.data[1] = exit_reason;
6620 return 0;
6621 }
6622
6623 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6624 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6625 get_vmcs12(vcpu), vcpu)))) {
6626 if (vmx_interrupt_allowed(vcpu)) {
6627 vmx->soft_vnmi_blocked = 0;
6628 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6629 vcpu->arch.nmi_pending) {
6630
6631
6632
6633
6634
6635
6636 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6637 "state on VCPU %d after 1 s timeout\n",
6638 __func__, vcpu->vcpu_id);
6639 vmx->soft_vnmi_blocked = 0;
6640 }
6641 }
6642
6643 if (exit_reason < kvm_vmx_max_exit_handlers
6644 && kvm_vmx_exit_handlers[exit_reason])
6645 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6646 else {
6647 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6648 vcpu->run->hw.hardware_exit_reason = exit_reason;
6649 }
6650 return 0;
6651}
6652
6653static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6654{
6655 if (irr == -1 || tpr < irr) {
6656 vmcs_write32(TPR_THRESHOLD, 0);
6657 return;
6658 }
6659
6660 vmcs_write32(TPR_THRESHOLD, irr);
6661}
6662
6663static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6664{
6665 u32 sec_exec_control;
6666
6667
6668
6669
6670
6671 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6672 !vmx_vm_has_apicv(vcpu->kvm))
6673 return;
6674
6675 if (!vm_need_tpr_shadow(vcpu->kvm))
6676 return;
6677
6678 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6679
6680 if (set) {
6681 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6682 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6683 } else {
6684 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6685 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6686 }
6687 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6688
6689 vmx_set_msr_bitmap(vcpu);
6690}
6691
6692static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6693{
6694 u16 status;
6695 u8 old;
6696
6697 if (!vmx_vm_has_apicv(kvm))
6698 return;
6699
6700 if (isr == -1)
6701 isr = 0;
6702
6703 status = vmcs_read16(GUEST_INTR_STATUS);
6704 old = status >> 8;
6705 if (isr != old) {
6706 status &= 0xff;
6707 status |= isr << 8;
6708 vmcs_write16(GUEST_INTR_STATUS, status);
6709 }
6710}
6711
6712static void vmx_set_rvi(int vector)
6713{
6714 u16 status;
6715 u8 old;
6716
6717 status = vmcs_read16(GUEST_INTR_STATUS);
6718 old = (u8)status & 0xff;
6719 if ((u8)vector != old) {
6720 status &= ~0xff;
6721 status |= (u8)vector;
6722 vmcs_write16(GUEST_INTR_STATUS, status);
6723 }
6724}
6725
6726static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6727{
6728 if (max_irr == -1)
6729 return;
6730
6731 vmx_set_rvi(max_irr);
6732}
6733
6734static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6735{
6736 if (!vmx_vm_has_apicv(vcpu->kvm))
6737 return;
6738
6739 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6740 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6741 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6742 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6743}
6744
6745static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6746{
6747 u32 exit_intr_info;
6748
6749 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6750 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6751 return;
6752
6753 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6754 exit_intr_info = vmx->exit_intr_info;
6755
6756
6757 if (is_machine_check(exit_intr_info))
6758 kvm_machine_check();
6759
6760
6761 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6762 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6763 kvm_before_handle_nmi(&vmx->vcpu);
6764 asm("int $2");
6765 kvm_after_handle_nmi(&vmx->vcpu);
6766 }
6767}
6768
6769static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6770{
6771 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6772
6773
6774
6775
6776
6777
6778 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6779 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6780 unsigned int vector;
6781 unsigned long entry;
6782 gate_desc *desc;
6783 struct vcpu_vmx *vmx = to_vmx(vcpu);
6784#ifdef CONFIG_X86_64
6785 unsigned long tmp;
6786#endif
6787
6788 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6789 desc = (gate_desc *)vmx->host_idt_base + vector;
6790 entry = gate_offset(*desc);
6791 asm volatile(
6792#ifdef CONFIG_X86_64
6793 "mov %%" _ASM_SP ", %[sp]\n\t"
6794 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6795 "push $%c[ss]\n\t"
6796 "push %[sp]\n\t"
6797#endif
6798 "pushf\n\t"
6799 "orl $0x200, (%%" _ASM_SP ")\n\t"
6800 __ASM_SIZE(push) " $%c[cs]\n\t"
6801 "call *%[entry]\n\t"
6802 :
6803#ifdef CONFIG_X86_64
6804 [sp]"=&r"(tmp)
6805#endif
6806 :
6807 [entry]"r"(entry),
6808 [ss]"i"(__KERNEL_DS),
6809 [cs]"i"(__KERNEL_CS)
6810 );
6811 } else
6812 local_irq_enable();
6813}
6814
6815static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6816{
6817 u32 exit_intr_info;
6818 bool unblock_nmi;
6819 u8 vector;
6820 bool idtv_info_valid;
6821
6822 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6823
6824 if (cpu_has_virtual_nmis()) {
6825 if (vmx->nmi_known_unmasked)
6826 return;
6827
6828
6829
6830
6831 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6832 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6833 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6834
6835
6836
6837
6838
6839
6840
6841
6842
6843
6844 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6845 vector != DF_VECTOR && !idtv_info_valid)
6846 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6847 GUEST_INTR_STATE_NMI);
6848 else
6849 vmx->nmi_known_unmasked =
6850 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6851 & GUEST_INTR_STATE_NMI);
6852 } else if (unlikely(vmx->soft_vnmi_blocked))
6853 vmx->vnmi_blocked_time +=
6854 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6855}
6856
6857static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6858 u32 idt_vectoring_info,
6859 int instr_len_field,
6860 int error_code_field)
6861{
6862 u8 vector;
6863 int type;
6864 bool idtv_info_valid;
6865
6866 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6867
6868 vcpu->arch.nmi_injected = false;
6869 kvm_clear_exception_queue(vcpu);
6870 kvm_clear_interrupt_queue(vcpu);
6871
6872 if (!idtv_info_valid)
6873 return;
6874
6875 kvm_make_request(KVM_REQ_EVENT, vcpu);
6876
6877 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6878 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6879
6880 switch (type) {
6881 case INTR_TYPE_NMI_INTR:
6882 vcpu->arch.nmi_injected = true;
6883
6884
6885
6886
6887
6888 vmx_set_nmi_mask(vcpu, false);
6889 break;
6890 case INTR_TYPE_SOFT_EXCEPTION:
6891 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6892
6893 case INTR_TYPE_HARD_EXCEPTION:
6894 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6895 u32 err = vmcs_read32(error_code_field);
6896 kvm_queue_exception_e(vcpu, vector, err);
6897 } else
6898 kvm_queue_exception(vcpu, vector);
6899 break;
6900 case INTR_TYPE_SOFT_INTR:
6901 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6902
6903 case INTR_TYPE_EXT_INTR:
6904 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6905 break;
6906 default:
6907 break;
6908 }
6909}
6910
6911static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6912{
6913 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6914 VM_EXIT_INSTRUCTION_LEN,
6915 IDT_VECTORING_ERROR_CODE);
6916}
6917
6918static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6919{
6920 __vmx_complete_interrupts(vcpu,
6921 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6922 VM_ENTRY_INSTRUCTION_LEN,
6923 VM_ENTRY_EXCEPTION_ERROR_CODE);
6924
6925 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6926}
6927
6928static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6929{
6930 int i, nr_msrs;
6931 struct perf_guest_switch_msr *msrs;
6932
6933 msrs = perf_guest_get_msrs(&nr_msrs);
6934
6935 if (!msrs)
6936 return;
6937
6938 for (i = 0; i < nr_msrs; i++)
6939 if (msrs[i].host == msrs[i].guest)
6940 clear_atomic_switch_msr(vmx, msrs[i].msr);
6941 else
6942 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6943 msrs[i].host);
6944}
6945
6946static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6947{
6948 struct vcpu_vmx *vmx = to_vmx(vcpu);
6949 unsigned long debugctlmsr;
6950
6951
6952 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6953 vmx->entry_time = ktime_get();
6954
6955
6956
6957 if (vmx->emulation_required)
6958 return;
6959
6960 if (vmx->nested.sync_shadow_vmcs) {
6961 copy_vmcs12_to_shadow(vmx);
6962 vmx->nested.sync_shadow_vmcs = false;
6963 }
6964
6965 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6966 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6967 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6968 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6969
6970
6971
6972
6973
6974
6975 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6976 vmx_set_interrupt_shadow(vcpu, 0);
6977
6978 atomic_switch_perf_msrs(vmx);
6979 debugctlmsr = get_debugctlmsr();
6980
6981 vmx->__launched = vmx->loaded_vmcs->launched;
6982 asm(
6983
6984 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6985 "push %%" _ASM_CX " \n\t"
6986 "push %%" _ASM_CX " \n\t"
6987 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6988 "je 1f \n\t"
6989 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6990 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6991 "1: \n\t"
6992
6993 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6994 "mov %%cr2, %%" _ASM_DX " \n\t"
6995 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
6996 "je 2f \n\t"
6997 "mov %%" _ASM_AX", %%cr2 \n\t"
6998 "2: \n\t"
6999
7000 "cmpl $0, %c[launched](%0) \n\t"
7001
7002 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7003 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7004 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7005 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7006 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7007 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7008#ifdef CONFIG_X86_64
7009 "mov %c[r8](%0), %%r8 \n\t"
7010 "mov %c[r9](%0), %%r9 \n\t"
7011 "mov %c[r10](%0), %%r10 \n\t"
7012 "mov %c[r11](%0), %%r11 \n\t"
7013 "mov %c[r12](%0), %%r12 \n\t"
7014 "mov %c[r13](%0), %%r13 \n\t"
7015 "mov %c[r14](%0), %%r14 \n\t"
7016 "mov %c[r15](%0), %%r15 \n\t"
7017#endif
7018 "mov %c[rcx](%0), %%" _ASM_CX " \n\t"
7019
7020
7021 "jne 1f \n\t"
7022 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7023 "jmp 2f \n\t"
7024 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7025 "2: "
7026
7027 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7028 "pop %0 \n\t"
7029 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7030 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7031 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7032 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7033 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7034 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7035 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7036#ifdef CONFIG_X86_64
7037 "mov %%r8, %c[r8](%0) \n\t"
7038 "mov %%r9, %c[r9](%0) \n\t"
7039 "mov %%r10, %c[r10](%0) \n\t"
7040 "mov %%r11, %c[r11](%0) \n\t"
7041 "mov %%r12, %c[r12](%0) \n\t"
7042 "mov %%r13, %c[r13](%0) \n\t"
7043 "mov %%r14, %c[r14](%0) \n\t"
7044 "mov %%r15, %c[r15](%0) \n\t"
7045#endif
7046 "mov %%cr2, %%" _ASM_AX " \n\t"
7047 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7048
7049 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
7050 "setbe %c[fail](%0) \n\t"
7051 ".pushsection .rodata \n\t"
7052 ".global vmx_return \n\t"
7053 "vmx_return: " _ASM_PTR " 2b \n\t"
7054 ".popsection"
7055 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7056 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7057 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7058 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7059 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7060 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7061 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7062 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7063 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7064 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7065 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7066#ifdef CONFIG_X86_64
7067 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7068 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7069 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7070 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7071 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7072 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7073 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7074 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7075#endif
7076 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7077 [wordsize]"i"(sizeof(ulong))
7078 : "cc", "memory"
7079#ifdef CONFIG_X86_64
7080 , "rax", "rbx", "rdi", "rsi"
7081 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7082#else
7083 , "eax", "ebx", "edi", "esi"
7084#endif
7085 );
7086
7087
7088 if (debugctlmsr)
7089 update_debugctlmsr(debugctlmsr);
7090
7091#ifndef CONFIG_X86_64
7092
7093
7094
7095
7096
7097
7098
7099
7100 loadsegment(ds, __USER_DS);
7101 loadsegment(es, __USER_DS);
7102#endif
7103
7104 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7105 | (1 << VCPU_EXREG_RFLAGS)
7106 | (1 << VCPU_EXREG_CPL)
7107 | (1 << VCPU_EXREG_PDPTR)
7108 | (1 << VCPU_EXREG_SEGMENTS)
7109 | (1 << VCPU_EXREG_CR3));
7110 vcpu->arch.regs_dirty = 0;
7111
7112 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7113
7114 vmx->loaded_vmcs->launched = 1;
7115
7116 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7117 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7118
7119 vmx_complete_atomic_exit(vmx);
7120 vmx_recover_nmi_blocking(vmx);
7121 vmx_complete_interrupts(vmx);
7122}
7123
7124static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7125{
7126 struct vcpu_vmx *vmx = to_vmx(vcpu);
7127
7128 free_vpid(vmx);
7129 free_nested(vmx);
7130 free_loaded_vmcs(vmx->loaded_vmcs);
7131 kfree(vmx->guest_msrs);
7132 kvm_vcpu_uninit(vcpu);
7133 kmem_cache_free(kvm_vcpu_cache, vmx);
7134}
7135
7136static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7137{
7138 int err;
7139 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7140 int cpu;
7141
7142 if (!vmx)
7143 return ERR_PTR(-ENOMEM);
7144
7145 allocate_vpid(vmx);
7146
7147 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7148 if (err)
7149 goto free_vcpu;
7150
7151 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7152 err = -ENOMEM;
7153 if (!vmx->guest_msrs) {
7154 goto uninit_vcpu;
7155 }
7156
7157 vmx->loaded_vmcs = &vmx->vmcs01;
7158 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7159 if (!vmx->loaded_vmcs->vmcs)
7160 goto free_msrs;
7161 if (!vmm_exclusive)
7162 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7163 loaded_vmcs_init(vmx->loaded_vmcs);
7164 if (!vmm_exclusive)
7165 kvm_cpu_vmxoff();
7166
7167 cpu = get_cpu();
7168 vmx_vcpu_load(&vmx->vcpu, cpu);
7169 vmx->vcpu.cpu = cpu;
7170 err = vmx_vcpu_setup(vmx);
7171 vmx_vcpu_put(&vmx->vcpu);
7172 put_cpu();
7173 if (err)
7174 goto free_vmcs;
7175 if (vm_need_virtualize_apic_accesses(kvm)) {
7176 err = alloc_apic_access_page(kvm);
7177 if (err)
7178 goto free_vmcs;
7179 }
7180
7181 if (enable_ept) {
7182 if (!kvm->arch.ept_identity_map_addr)
7183 kvm->arch.ept_identity_map_addr =
7184 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7185 err = -ENOMEM;
7186 if (alloc_identity_pagetable(kvm) != 0)
7187 goto free_vmcs;
7188 if (!init_rmode_identity_map(kvm))
7189 goto free_vmcs;
7190 }
7191
7192 vmx->nested.current_vmptr = -1ull;
7193 vmx->nested.current_vmcs12 = NULL;
7194
7195 return &vmx->vcpu;
7196
7197free_vmcs:
7198 free_loaded_vmcs(vmx->loaded_vmcs);
7199free_msrs:
7200 kfree(vmx->guest_msrs);
7201uninit_vcpu:
7202 kvm_vcpu_uninit(&vmx->vcpu);
7203free_vcpu:
7204 free_vpid(vmx);
7205 kmem_cache_free(kvm_vcpu_cache, vmx);
7206 return ERR_PTR(err);
7207}
7208
7209static void __init vmx_check_processor_compat(void *rtn)
7210{
7211 struct vmcs_config vmcs_conf;
7212
7213 *(int *)rtn = 0;
7214 if (setup_vmcs_config(&vmcs_conf) < 0)
7215 *(int *)rtn = -EIO;
7216 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7217 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7218 smp_processor_id());
7219 *(int *)rtn = -EIO;
7220 }
7221}
7222
7223static int get_ept_level(void)
7224{
7225 return VMX_EPT_DEFAULT_GAW + 1;
7226}
7227
7228static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7229{
7230 u64 ret;
7231
7232
7233
7234
7235
7236
7237
7238
7239
7240
7241
7242
7243 if (is_mmio)
7244 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7245 else if (vcpu->kvm->arch.iommu_domain &&
7246 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7247 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7248 VMX_EPT_MT_EPTE_SHIFT;
7249 else
7250 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7251 | VMX_EPT_IPAT_BIT;
7252
7253 return ret;
7254}
7255
7256static int vmx_get_lpage_level(void)
7257{
7258 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7259 return PT_DIRECTORY_LEVEL;
7260 else
7261
7262 return PT_PDPE_LEVEL;
7263}
7264
7265static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7266{
7267 struct kvm_cpuid_entry2 *best;
7268 struct vcpu_vmx *vmx = to_vmx(vcpu);
7269 u32 exec_control;
7270
7271 vmx->rdtscp_enabled = false;
7272 if (vmx_rdtscp_supported()) {
7273 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7274 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7275 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7276 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7277 vmx->rdtscp_enabled = true;
7278 else {
7279 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7280 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7281 exec_control);
7282 }
7283 }
7284 }
7285
7286
7287 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7288 if (vmx_invpcid_supported() &&
7289 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7290 guest_cpuid_has_pcid(vcpu)) {
7291 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7292 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7293 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7294 exec_control);
7295 } else {
7296 if (cpu_has_secondary_exec_ctrls()) {
7297 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7298 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7299 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7300 exec_control);
7301 }
7302 if (best)
7303 best->ebx &= ~bit(X86_FEATURE_INVPCID);
7304 }
7305}
7306
7307static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7308{
7309 if (func == 1 && nested)
7310 entry->ecx |= bit(X86_FEATURE_VMX);
7311}
7312
7313
7314
7315
7316
7317
7318
7319
7320
7321
7322static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7323{
7324 struct vcpu_vmx *vmx = to_vmx(vcpu);
7325 u32 exec_control;
7326
7327 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7328 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7329 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7330 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7331 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7332 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7333 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7334 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7335 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7336 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7337 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7338 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7339 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7340 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7341 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7342 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7343 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7344 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7345 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7346 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7347 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7348 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7349 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7350 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7351 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7352 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7353 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7354 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7355 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7356 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7357 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7358 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7359 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7360 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7361 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7362 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7363
7364 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7365 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7366 vmcs12->vm_entry_intr_info_field);
7367 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7368 vmcs12->vm_entry_exception_error_code);
7369 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7370 vmcs12->vm_entry_instruction_len);
7371 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7372 vmcs12->guest_interruptibility_info);
7373 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7374 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7375 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
7376 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7377 vmcs12->guest_pending_dbg_exceptions);
7378 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7379 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7380
7381 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7382
7383 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7384 (vmcs_config.pin_based_exec_ctrl |
7385 vmcs12->pin_based_vm_exec_control));
7386
7387 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7388 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7389 vmcs12->vmx_preemption_timer_value);
7390
7391
7392
7393
7394
7395
7396
7397
7398
7399
7400
7401
7402
7403
7404
7405
7406
7407
7408
7409
7410
7411 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7412 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7413 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7414 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7415
7416 if (cpu_has_secondary_exec_ctrls()) {
7417 u32 exec_control = vmx_secondary_exec_control(vmx);
7418 if (!vmx->rdtscp_enabled)
7419 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7420
7421 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7422 if (nested_cpu_has(vmcs12,
7423 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7424 exec_control |= vmcs12->secondary_vm_exec_control;
7425
7426 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7427
7428
7429
7430
7431
7432
7433 if (vmx->nested.apic_access_page)
7434 nested_release_page(vmx->nested.apic_access_page);
7435 vmx->nested.apic_access_page =
7436 nested_get_page(vcpu, vmcs12->apic_access_addr);
7437
7438
7439
7440
7441
7442
7443 if (!vmx->nested.apic_access_page)
7444 exec_control &=
7445 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7446 else
7447 vmcs_write64(APIC_ACCESS_ADDR,
7448 page_to_phys(vmx->nested.apic_access_page));
7449 }
7450
7451 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7452 }
7453
7454
7455
7456
7457
7458
7459
7460
7461 vmx_set_constant_host_state(vmx);
7462
7463
7464
7465
7466
7467
7468
7469
7470 vmx->host_rsp = 0;
7471
7472 exec_control = vmx_exec_control(vmx);
7473 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7474 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7475 exec_control &= ~CPU_BASED_TPR_SHADOW;
7476 exec_control |= vmcs12->cpu_based_vm_exec_control;
7477
7478
7479
7480
7481 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7482 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7483 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7484
7485 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7486
7487
7488
7489
7490
7491 update_exception_bitmap(vcpu);
7492 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7493 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7494
7495
7496 vmcs_write32(VM_EXIT_CONTROLS,
7497 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7498 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7499 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7500
7501 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7502 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7503 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7504 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7505
7506
7507 set_cr4_guest_host_mask(vmx);
7508
7509 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7510 vmcs_write64(TSC_OFFSET,
7511 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7512 else
7513 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7514
7515 if (enable_vpid) {
7516
7517
7518
7519
7520
7521 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7522 vmx_flush_tlb(vcpu);
7523 }
7524
7525 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7526 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7527 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7528 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7529 else
7530 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7531
7532 vmx_set_efer(vcpu, vcpu->arch.efer);
7533
7534
7535
7536
7537
7538
7539
7540
7541
7542 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7543 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7544
7545 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7546 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7547
7548
7549 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7550 kvm_mmu_reset_context(vcpu);
7551
7552 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7553 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7554}
7555
7556
7557
7558
7559
7560static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7561{
7562 struct vmcs12 *vmcs12;
7563 struct vcpu_vmx *vmx = to_vmx(vcpu);
7564 int cpu;
7565 struct loaded_vmcs *vmcs02;
7566 bool ia32e;
7567
7568 if (!nested_vmx_check_permission(vcpu) ||
7569 !nested_vmx_check_vmcs12(vcpu))
7570 return 1;
7571
7572 skip_emulated_instruction(vcpu);
7573 vmcs12 = get_vmcs12(vcpu);
7574
7575 if (enable_shadow_vmcs)
7576 copy_shadow_to_vmcs12(vmx);
7577
7578
7579
7580
7581
7582
7583
7584
7585
7586
7587
7588 if (vmcs12->launch_state == launch) {
7589 nested_vmx_failValid(vcpu,
7590 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7591 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7592 return 1;
7593 }
7594
7595 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7596 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7597 return 1;
7598 }
7599
7600 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7601 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7602
7603 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7604 return 1;
7605 }
7606
7607 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7608 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7609
7610 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7611 return 1;
7612 }
7613
7614 if (vmcs12->vm_entry_msr_load_count > 0 ||
7615 vmcs12->vm_exit_msr_load_count > 0 ||
7616 vmcs12->vm_exit_msr_store_count > 0) {
7617 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7618 __func__);
7619 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7620 return 1;
7621 }
7622
7623 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7624 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7625 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7626 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7627 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7628 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7629 !vmx_control_verify(vmcs12->vm_exit_controls,
7630 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7631 !vmx_control_verify(vmcs12->vm_entry_controls,
7632 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7633 {
7634 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7635 return 1;
7636 }
7637
7638 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7639 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7640 nested_vmx_failValid(vcpu,
7641 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7642 return 1;
7643 }
7644
7645 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7646 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7647 nested_vmx_entry_failure(vcpu, vmcs12,
7648 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7649 return 1;
7650 }
7651 if (vmcs12->vmcs_link_pointer != -1ull) {
7652 nested_vmx_entry_failure(vcpu, vmcs12,
7653 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7654 return 1;
7655 }
7656
7657
7658
7659
7660
7661
7662
7663
7664
7665
7666 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7667 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7668 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7669 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7670 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7671 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7672 nested_vmx_entry_failure(vcpu, vmcs12,
7673 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7674 return 1;
7675 }
7676 }
7677
7678
7679
7680
7681
7682
7683
7684 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7685 ia32e = (vmcs12->vm_exit_controls &
7686 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7687 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7688 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7689 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7690 nested_vmx_entry_failure(vcpu, vmcs12,
7691 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7692 return 1;
7693 }
7694 }
7695
7696
7697
7698
7699
7700
7701 vmcs02 = nested_get_current_vmcs02(vmx);
7702 if (!vmcs02)
7703 return -ENOMEM;
7704
7705 enter_guest_mode(vcpu);
7706
7707 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7708
7709 cpu = get_cpu();
7710 vmx->loaded_vmcs = vmcs02;
7711 vmx_vcpu_put(vcpu);
7712 vmx_vcpu_load(vcpu, cpu);
7713 vcpu->cpu = cpu;
7714 put_cpu();
7715
7716 vmx_segment_cache_clear(vmx);
7717
7718 vmcs12->launch_state = 1;
7719
7720 prepare_vmcs02(vcpu, vmcs12);
7721
7722
7723
7724
7725
7726
7727
7728 return 1;
7729}
7730
7731
7732
7733
7734
7735
7736
7737
7738
7739
7740
7741
7742
7743
7744
7745
7746
7747
7748static inline unsigned long
7749vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7750{
7751 return
7752 (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7753 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7754 (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7755 vcpu->arch.cr0_guest_owned_bits));
7756}
7757
7758static inline unsigned long
7759vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7760{
7761 return
7762 (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7763 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7764 (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7765 vcpu->arch.cr4_guest_owned_bits));
7766}
7767
7768static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7769 struct vmcs12 *vmcs12)
7770{
7771 u32 idt_vectoring;
7772 unsigned int nr;
7773
7774 if (vcpu->arch.exception.pending) {
7775 nr = vcpu->arch.exception.nr;
7776 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7777
7778 if (kvm_exception_is_soft(nr)) {
7779 vmcs12->vm_exit_instruction_len =
7780 vcpu->arch.event_exit_inst_len;
7781 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7782 } else
7783 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7784
7785 if (vcpu->arch.exception.has_error_code) {
7786 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7787 vmcs12->idt_vectoring_error_code =
7788 vcpu->arch.exception.error_code;
7789 }
7790
7791 vmcs12->idt_vectoring_info_field = idt_vectoring;
7792 } else if (vcpu->arch.nmi_pending) {
7793 vmcs12->idt_vectoring_info_field =
7794 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7795 } else if (vcpu->arch.interrupt.pending) {
7796 nr = vcpu->arch.interrupt.nr;
7797 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7798
7799 if (vcpu->arch.interrupt.soft) {
7800 idt_vectoring |= INTR_TYPE_SOFT_INTR;
7801 vmcs12->vm_entry_instruction_len =
7802 vcpu->arch.event_exit_inst_len;
7803 } else
7804 idt_vectoring |= INTR_TYPE_EXT_INTR;
7805
7806 vmcs12->idt_vectoring_info_field = idt_vectoring;
7807 }
7808}
7809
7810
7811
7812
7813
7814
7815
7816
7817
7818
7819
7820
7821static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7822{
7823
7824 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7825 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7826
7827 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7828 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7829 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7830 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7831
7832 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7833 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7834 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7835 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7836 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7837 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7838 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7839 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7840 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7841 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7842 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7843 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7844 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7845 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7846 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7847 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7848 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7849 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7850 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7851 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7852 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7853 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7854 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7855 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7856 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7857 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7858 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7859 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7860 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7861 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7862 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7863 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7864 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7865 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7866 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7867 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7868
7869 vmcs12->guest_interruptibility_info =
7870 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7871 vmcs12->guest_pending_dbg_exceptions =
7872 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7873
7874 vmcs12->vm_entry_controls =
7875 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7876 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7877
7878
7879
7880 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7881 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
7882 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7883 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7884 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7885 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7886
7887
7888
7889 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
7890 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7891
7892 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7893 if ((vmcs12->vm_exit_intr_info &
7894 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7895 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7896 vmcs12->vm_exit_intr_error_code =
7897 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7898 vmcs12->idt_vectoring_info_field = 0;
7899 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7900 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7901
7902 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7903
7904
7905 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7906
7907
7908
7909
7910
7911 vmcs12_save_pending_event(vcpu, vmcs12);
7912 }
7913
7914
7915
7916
7917
7918 vcpu->arch.nmi_injected = false;
7919 kvm_clear_exception_queue(vcpu);
7920 kvm_clear_interrupt_queue(vcpu);
7921}
7922
7923
7924
7925
7926
7927
7928
7929
7930
7931
7932static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7933 struct vmcs12 *vmcs12)
7934{
7935 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7936 vcpu->arch.efer = vmcs12->host_ia32_efer;
7937 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7938 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7939 else
7940 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7941 vmx_set_efer(vcpu, vcpu->arch.efer);
7942
7943 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7944 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7945 vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
7946
7947
7948
7949
7950
7951
7952 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7953
7954
7955
7956
7957
7958 update_exception_bitmap(vcpu);
7959 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7960 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7961
7962
7963
7964
7965
7966 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7967 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7968
7969
7970 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7971 kvm_mmu_reset_context(vcpu);
7972
7973 if (enable_vpid) {
7974
7975
7976
7977
7978
7979 vmx_flush_tlb(vcpu);
7980 }
7981
7982
7983 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7984 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7985 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7986 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7987 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7988 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7989 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7990 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7991 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7992 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7993 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7994 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7995 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7996 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7997 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7998
7999 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8000 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8001 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8002 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8003 vmcs12->host_ia32_perf_global_ctrl);
8004
8005 kvm_set_dr(vcpu, 7, 0x400);
8006 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8007}
8008
8009
8010
8011
8012
8013
8014static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8015{
8016 struct vcpu_vmx *vmx = to_vmx(vcpu);
8017 int cpu;
8018 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8019
8020
8021 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8022
8023 leave_guest_mode(vcpu);
8024 prepare_vmcs12(vcpu, vmcs12);
8025
8026 cpu = get_cpu();
8027 vmx->loaded_vmcs = &vmx->vmcs01;
8028 vmx_vcpu_put(vcpu);
8029 vmx_vcpu_load(vcpu, cpu);
8030 vcpu->cpu = cpu;
8031 put_cpu();
8032
8033 vmx_segment_cache_clear(vmx);
8034
8035
8036 if (VMCS02_POOL_SIZE == 0)
8037 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8038
8039 load_vmcs12_host_state(vcpu, vmcs12);
8040
8041
8042 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8043
8044
8045 vmx->host_rsp = 0;
8046
8047
8048 if (vmx->nested.apic_access_page) {
8049 nested_release_page(vmx->nested.apic_access_page);
8050 vmx->nested.apic_access_page = 0;
8051 }
8052
8053
8054
8055
8056
8057
8058 if (unlikely(vmx->fail)) {
8059 vmx->fail = 0;
8060 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8061 } else
8062 nested_vmx_succeed(vcpu);
8063 if (enable_shadow_vmcs)
8064 vmx->nested.sync_shadow_vmcs = true;
8065}
8066
8067
8068
8069
8070
8071
8072
8073
8074static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8075 struct vmcs12 *vmcs12,
8076 u32 reason, unsigned long qualification)
8077{
8078 load_vmcs12_host_state(vcpu, vmcs12);
8079 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8080 vmcs12->exit_qualification = qualification;
8081 nested_vmx_succeed(vcpu);
8082 if (enable_shadow_vmcs)
8083 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8084}
8085
8086static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8087 struct x86_instruction_info *info,
8088 enum x86_intercept_stage stage)
8089{
8090 return X86EMUL_CONTINUE;
8091}
8092
8093static struct kvm_x86_ops vmx_x86_ops = {
8094 .cpu_has_kvm_support = cpu_has_kvm_support,
8095 .disabled_by_bios = vmx_disabled_by_bios,
8096 .hardware_setup = hardware_setup,
8097 .hardware_unsetup = hardware_unsetup,
8098 .check_processor_compatibility = vmx_check_processor_compat,
8099 .hardware_enable = hardware_enable,
8100 .hardware_disable = hardware_disable,
8101 .cpu_has_accelerated_tpr = report_flexpriority,
8102
8103 .vcpu_create = vmx_create_vcpu,
8104 .vcpu_free = vmx_free_vcpu,
8105 .vcpu_reset = vmx_vcpu_reset,
8106
8107 .prepare_guest_switch = vmx_save_host_state,
8108 .vcpu_load = vmx_vcpu_load,
8109 .vcpu_put = vmx_vcpu_put,
8110
8111 .update_db_bp_intercept = update_exception_bitmap,
8112 .get_msr = vmx_get_msr,
8113 .set_msr = vmx_set_msr,
8114 .get_segment_base = vmx_get_segment_base,
8115 .get_segment = vmx_get_segment,
8116 .set_segment = vmx_set_segment,
8117 .get_cpl = vmx_get_cpl,
8118 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8119 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8120 .decache_cr3 = vmx_decache_cr3,
8121 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8122 .set_cr0 = vmx_set_cr0,
8123 .set_cr3 = vmx_set_cr3,
8124 .set_cr4 = vmx_set_cr4,
8125 .set_efer = vmx_set_efer,
8126 .get_idt = vmx_get_idt,
8127 .set_idt = vmx_set_idt,
8128 .get_gdt = vmx_get_gdt,
8129 .set_gdt = vmx_set_gdt,
8130 .set_dr7 = vmx_set_dr7,
8131 .cache_reg = vmx_cache_reg,
8132 .get_rflags = vmx_get_rflags,
8133 .set_rflags = vmx_set_rflags,
8134 .fpu_activate = vmx_fpu_activate,
8135 .fpu_deactivate = vmx_fpu_deactivate,
8136
8137 .tlb_flush = vmx_flush_tlb,
8138
8139 .run = vmx_vcpu_run,
8140 .handle_exit = vmx_handle_exit,
8141 .skip_emulated_instruction = skip_emulated_instruction,
8142 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8143 .get_interrupt_shadow = vmx_get_interrupt_shadow,
8144 .patch_hypercall = vmx_patch_hypercall,
8145 .set_irq = vmx_inject_irq,
8146 .set_nmi = vmx_inject_nmi,
8147 .queue_exception = vmx_queue_exception,
8148 .cancel_injection = vmx_cancel_injection,
8149 .interrupt_allowed = vmx_interrupt_allowed,
8150 .nmi_allowed = vmx_nmi_allowed,
8151 .get_nmi_mask = vmx_get_nmi_mask,
8152 .set_nmi_mask = vmx_set_nmi_mask,
8153 .enable_nmi_window = enable_nmi_window,
8154 .enable_irq_window = enable_irq_window,
8155 .update_cr8_intercept = update_cr8_intercept,
8156 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8157 .vm_has_apicv = vmx_vm_has_apicv,
8158 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8159 .hwapic_irr_update = vmx_hwapic_irr_update,
8160 .hwapic_isr_update = vmx_hwapic_isr_update,
8161 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8162 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8163
8164 .set_tss_addr = vmx_set_tss_addr,
8165 .get_tdp_level = get_ept_level,
8166 .get_mt_mask = vmx_get_mt_mask,
8167
8168 .get_exit_info = vmx_get_exit_info,
8169
8170 .get_lpage_level = vmx_get_lpage_level,
8171
8172 .cpuid_update = vmx_cpuid_update,
8173
8174 .rdtscp_supported = vmx_rdtscp_supported,
8175 .invpcid_supported = vmx_invpcid_supported,
8176
8177 .set_supported_cpuid = vmx_set_supported_cpuid,
8178
8179 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8180
8181 .set_tsc_khz = vmx_set_tsc_khz,
8182 .read_tsc_offset = vmx_read_tsc_offset,
8183 .write_tsc_offset = vmx_write_tsc_offset,
8184 .adjust_tsc_offset = vmx_adjust_tsc_offset,
8185 .compute_tsc_offset = vmx_compute_tsc_offset,
8186 .read_l1_tsc = vmx_read_l1_tsc,
8187
8188 .set_tdp_cr3 = vmx_set_cr3,
8189
8190 .check_intercept = vmx_check_intercept,
8191 .handle_external_intr = vmx_handle_external_intr,
8192};
8193
8194static int __init vmx_init(void)
8195{
8196 int r, i, msr;
8197
8198 rdmsrl_safe(MSR_EFER, &host_efer);
8199
8200 for (i = 0; i < NR_VMX_MSR; ++i)
8201 kvm_define_shared_msr(i, vmx_msr_index[i]);
8202
8203 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8204 if (!vmx_io_bitmap_a)
8205 return -ENOMEM;
8206
8207 r = -ENOMEM;
8208
8209 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8210 if (!vmx_io_bitmap_b)
8211 goto out;
8212
8213 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8214 if (!vmx_msr_bitmap_legacy)
8215 goto out1;
8216
8217 vmx_msr_bitmap_legacy_x2apic =
8218 (unsigned long *)__get_free_page(GFP_KERNEL);
8219 if (!vmx_msr_bitmap_legacy_x2apic)
8220 goto out2;
8221
8222 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8223 if (!vmx_msr_bitmap_longmode)
8224 goto out3;
8225
8226 vmx_msr_bitmap_longmode_x2apic =
8227 (unsigned long *)__get_free_page(GFP_KERNEL);
8228 if (!vmx_msr_bitmap_longmode_x2apic)
8229 goto out4;
8230 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8231 if (!vmx_vmread_bitmap)
8232 goto out5;
8233
8234 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8235 if (!vmx_vmwrite_bitmap)
8236 goto out6;
8237
8238 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8239 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8240
8241 for (i = 0; i < max_shadow_read_write_fields; i++) {
8242 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8243 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8244 }
8245
8246 for (i = 0; i < max_shadow_read_only_fields; i++)
8247 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8248
8249
8250
8251
8252
8253 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8254 clear_bit(0x80, vmx_io_bitmap_a);
8255
8256 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8257
8258 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8259 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8260
8261 set_bit(0, vmx_vpid_bitmap);
8262
8263 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8264 __alignof__(struct vcpu_vmx), THIS_MODULE);
8265 if (r)
8266 goto out7;
8267
8268#ifdef CONFIG_KEXEC
8269 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8270 crash_vmclear_local_loaded_vmcss);
8271#endif
8272
8273 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8274 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8275 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8276 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8277 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8278 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8279 memcpy(vmx_msr_bitmap_legacy_x2apic,
8280 vmx_msr_bitmap_legacy, PAGE_SIZE);
8281 memcpy(vmx_msr_bitmap_longmode_x2apic,
8282 vmx_msr_bitmap_longmode, PAGE_SIZE);
8283
8284 if (enable_apicv) {
8285 for (msr = 0x800; msr <= 0x8ff; msr++)
8286 vmx_disable_intercept_msr_read_x2apic(msr);
8287
8288
8289
8290
8291 vmx_enable_intercept_msr_read_x2apic(0x802);
8292
8293 vmx_enable_intercept_msr_read_x2apic(0x839);
8294
8295 vmx_disable_intercept_msr_write_x2apic(0x808);
8296
8297 vmx_disable_intercept_msr_write_x2apic(0x80b);
8298
8299 vmx_disable_intercept_msr_write_x2apic(0x83f);
8300 }
8301
8302 if (enable_ept) {
8303 kvm_mmu_set_mask_ptes(0ull,
8304 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8305 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8306 0ull, VMX_EPT_EXECUTABLE_MASK);
8307 ept_set_mmio_spte_mask();
8308 kvm_enable_tdp();
8309 } else
8310 kvm_disable_tdp();
8311
8312 return 0;
8313
8314out7:
8315 free_page((unsigned long)vmx_vmwrite_bitmap);
8316out6:
8317 free_page((unsigned long)vmx_vmread_bitmap);
8318out5:
8319 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8320out4:
8321 free_page((unsigned long)vmx_msr_bitmap_longmode);
8322out3:
8323 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8324out2:
8325 free_page((unsigned long)vmx_msr_bitmap_legacy);
8326out1:
8327 free_page((unsigned long)vmx_io_bitmap_b);
8328out:
8329 free_page((unsigned long)vmx_io_bitmap_a);
8330 return r;
8331}
8332
8333static void __exit vmx_exit(void)
8334{
8335 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8336 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8337 free_page((unsigned long)vmx_msr_bitmap_legacy);
8338 free_page((unsigned long)vmx_msr_bitmap_longmode);
8339 free_page((unsigned long)vmx_io_bitmap_b);
8340 free_page((unsigned long)vmx_io_bitmap_a);
8341 free_page((unsigned long)vmx_vmwrite_bitmap);
8342 free_page((unsigned long)vmx_vmread_bitmap);
8343
8344#ifdef CONFIG_KEXEC
8345 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8346 synchronize_rcu();
8347#endif
8348
8349 kvm_exit();
8350}
8351
8352module_init(vmx_init)
8353module_exit(vmx_exit)
8354