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5#include <linux/delay.h>
6#include <linux/dmi.h>
7#include <linux/pci.h>
8#include <linux/init.h>
9#include <linux/vgaarb.h>
10#include <asm/pci_x86.h>
11
12static void pci_fixup_i450nx(struct pci_dev *d)
13{
14
15
16
17 int pxb, reg;
18 u8 busno, suba, subb;
19
20 dev_warn(&d->dev, "Searching for i450NX host bridges\n");
21 reg = 0xd0;
22 for(pxb = 0; pxb < 2; pxb++) {
23 pci_read_config_byte(d, reg++, &busno);
24 pci_read_config_byte(d, reg++, &suba);
25 pci_read_config_byte(d, reg++, &subb);
26 dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
27 suba, subb);
28 if (busno)
29 pci_scan_bus_with_sysdata(busno);
30 if (suba < subb)
31 pci_scan_bus_with_sysdata(suba+1);
32 }
33 pcibios_last_bus = -1;
34}
35DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
36
37static void pci_fixup_i450gx(struct pci_dev *d)
38{
39
40
41
42
43 u8 busno;
44 pci_read_config_byte(d, 0x4a, &busno);
45 dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
46 pci_scan_bus_with_sysdata(busno);
47 pcibios_last_bus = -1;
48}
49DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
50
51static void pci_fixup_umc_ide(struct pci_dev *d)
52{
53
54
55
56
57 int i;
58
59 dev_warn(&d->dev, "Fixing base address flags\n");
60 for(i = 0; i < 4; i++)
61 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
62}
63DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
64
65static void pci_fixup_ncr53c810(struct pci_dev *d)
66{
67
68
69
70
71 if (!d->class) {
72 dev_warn(&d->dev, "Fixing NCR 53C810 class code\n");
73 d->class = PCI_CLASS_STORAGE_SCSI << 8;
74 }
75}
76DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
77
78static void pci_fixup_latency(struct pci_dev *d)
79{
80
81
82
83
84 dev_dbg(&d->dev, "Setting max latency to 32\n");
85 pcibios_max_latency = 32;
86}
87DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
88DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
89
90static void pci_fixup_piix4_acpi(struct pci_dev *d)
91{
92
93
94
95 d->irq = 9;
96}
97DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
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115
116#define VIA_8363_KL133_REVISION_ID 0x81
117#define VIA_8363_KM133_REVISION_ID 0x84
118
119static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
120{
121 u8 v;
122 int where = 0x55;
123 int mask = 0x1f;
124
125 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
126
127
128
129 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
130
131 where = 0x95;
132
133 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
134 (d->revision == VIA_8363_KL133_REVISION_ID ||
135 d->revision == VIA_8363_KM133_REVISION_ID)) {
136 mask = 0x3f;
137
138 }
139
140 pci_read_config_byte(d, where, &v);
141 if (v & ~mask) {
142 dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
143 d->device, d->revision, where, v, mask, v & mask);
144 v &= mask;
145 pci_write_config_byte(d, where, v);
146 }
147}
148DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
149DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
150DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
151DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
152DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
153DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
154DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
155DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
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165
166static void pci_fixup_transparent_bridge(struct pci_dev *dev)
167{
168 if ((dev->device & 0xff00) == 0x2400)
169 dev->transparent = 1;
170}
171DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
172 PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge);
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185
186static void pci_fixup_nforce2(struct pci_dev *dev)
187{
188 u32 val;
189
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197
198 pci_read_config_dword(dev, 0x6c, &val);
199
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202
203 if ((val & 0x00FF0000) != 0x00010000) {
204 dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");
205 pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
206 }
207}
208DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
209DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
210
211
212#define MAX_PCIEROOT 6
213static int quirk_aspm_offset[MAX_PCIEROOT << 3];
214
215#define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
216
217static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
218{
219 return raw_pci_read(pci_domain_nr(bus), bus->number,
220 devfn, where, size, value);
221}
222
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225
226
227static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
228{
229 u8 offset;
230
231 offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
232
233 if ((offset) && (where == offset))
234 value = value & 0xfffffffc;
235
236 return raw_pci_write(pci_domain_nr(bus), bus->number,
237 devfn, where, size, value);
238}
239
240static struct pci_ops quirk_pcie_aspm_ops = {
241 .read = quirk_pcie_aspm_read,
242 .write = quirk_pcie_aspm_write,
243};
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251
252
253static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
254{
255 int cap_base, i;
256 struct pci_bus *pbus;
257 struct pci_dev *dev;
258
259 if ((pbus = pdev->subordinate) == NULL)
260 return;
261
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265
266
267 if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
268 (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
269 return;
270
271 if (list_empty(&pbus->devices)) {
272
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278 for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
279 quirk_aspm_offset[i] = 0;
280
281 pbus->ops = pbus->parent->ops;
282 } else {
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288
289 list_for_each_entry(dev, &pbus->devices, bus_list) {
290
291 cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP);
292 quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] = cap_base + 0x10;
293 }
294 pbus->ops = &quirk_pcie_aspm_ops;
295 }
296}
297DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk);
298DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk);
299DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk);
300DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk);
301DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk);
302DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk);
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320static void pci_fixup_video(struct pci_dev *pdev)
321{
322 struct pci_dev *bridge;
323 struct pci_bus *bus;
324 u16 config;
325
326
327 bus = pdev->bus;
328 while (bus) {
329 bridge = bus->self;
330
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335
336
337
338 if (bridge
339 && ((bridge->hdr_type == PCI_HEADER_TYPE_BRIDGE)
340 || (bridge->hdr_type == PCI_HEADER_TYPE_CARDBUS))) {
341 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
342 &config);
343 if (!(config & PCI_BRIDGE_CTL_VGA))
344 return;
345 }
346 bus = bus->parent;
347 }
348 pci_read_config_word(pdev, PCI_COMMAND, &config);
349 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
350 pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
351 dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
352 if (!vga_default_device())
353 vga_set_default_device(pdev);
354 }
355}
356DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
357 PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);
358
359
360static const struct dmi_system_id msi_k8t_dmi_table[] = {
361 {
362 .ident = "MSI-K8T-Neo2Fir",
363 .matches = {
364 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
365 DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"),
366 },
367 },
368 {}
369};
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380
381static void pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev)
382{
383 unsigned char val;
384 if (!dmi_check_system(msi_k8t_dmi_table))
385 return;
386
387 pci_read_config_byte(dev, 0x50, &val);
388 if (val & 0x40) {
389 pci_write_config_byte(dev, 0x50, val & (~0x40));
390
391
392 pci_read_config_byte(dev, 0x50, &val);
393 if (val & 0x40)
394 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
395 "can't enable onboard soundcard!\n");
396 else
397 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
398 "enabled onboard soundcard\n");
399 }
400}
401DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
402 pci_fixup_msi_k8t_onboard_sound);
403DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
404 pci_fixup_msi_k8t_onboard_sound);
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414
415static u16 toshiba_line_size;
416
417static const struct dmi_system_id toshiba_ohci1394_dmi_table[] = {
418 {
419 .ident = "Toshiba PS5 based laptop",
420 .matches = {
421 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
422 DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
423 },
424 },
425 {
426 .ident = "Toshiba PSM4 based laptop",
427 .matches = {
428 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
429 DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
430 },
431 },
432 {
433 .ident = "Toshiba A40 based laptop",
434 .matches = {
435 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
436 DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
437 },
438 },
439 { }
440};
441
442static void pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
443{
444 if (!dmi_check_system(toshiba_ohci1394_dmi_table))
445 return;
446
447 dev->current_state = PCI_D3cold;
448 pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
449}
450DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
451 pci_pre_fixup_toshiba_ohci1394);
452
453static void pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
454{
455 if (!dmi_check_system(toshiba_ohci1394_dmi_table))
456 return;
457
458
459 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
460 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
461 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
462 pci_resource_start(dev, 0));
463 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
464 pci_resource_start(dev, 1));
465}
466DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
467 pci_post_fixup_toshiba_ohci1394);
468
469
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471
472
473
474static void pci_early_fixup_cyrix_5530(struct pci_dev *dev)
475{
476 u8 r;
477
478 pci_read_config_byte(dev, 0x42, &r);
479 r &= 0xfd;
480 pci_write_config_byte(dev, 0x42, r);
481}
482DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
483 pci_early_fixup_cyrix_5530);
484DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
485 pci_early_fixup_cyrix_5530);
486
487
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490
491static void pci_siemens_interrupt_controller(struct pci_dev *dev)
492{
493 dev->resource[0].flags |= IORESOURCE_PCI_FIXED;
494}
495DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
496 pci_siemens_interrupt_controller);
497
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500
501
502static void sb600_disable_hpet_bar(struct pci_dev *dev)
503{
504 u8 val;
505
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510
511
512
513 pci_read_config_byte(dev, 0x08, &val);
514
515 if (val < 0x2F) {
516 outb(0x55, 0xCD6);
517 val = inb(0xCD7);
518
519
520 outb(0x55, 0xCD6);
521 outb(val | 0x80, 0xCD7);
522 }
523}
524DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);
525
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531
532
533
534static void twinhead_reserve_killing_zone(struct pci_dev *dev)
535{
536 if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) {
537 pr_info("Reserving memory on Twinhead H12Y\n");
538 request_mem_region(0xFFB00000, 0x100000, "twinhead");
539 }
540}
541DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone);
542