LXR linux/arch/xtensa/mm/mmu.c

   1/*
   2 * xtensa mmu stuff
   3 *
   4 * Extracted from init.c
   5 */
   6#include <linux/percpu.h>
   7#include <linux/init.h>
   8#include <linux/string.h>
   9#include <linux/slab.h>
  10#include <linux/cache.h>
  11
  12#include <asm/tlb.h>
  13#include <asm/tlbflush.h>
  14#include <asm/mmu_context.h>
  15#include <asm/page.h>
  16
  17void __init paging_init(void)
  18{
  19        memset(swapper_pg_dir, 0, PAGE_SIZE);
  20}
  21
  22/*
  23 * Flush the mmu and reset associated register to default values.
  24 */
  25void __init init_mmu(void)
  26{
  27#if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
  28        /*
  29         * Writing zeros to the instruction and data TLBCFG special
  30         * registers ensure that valid values exist in the register.
  31         *
  32         * For existing PGSZID<w> fields, zero selects the first element
  33         * of the page-size array.  For nonexistent PGSZID<w> fields,
  34         * zero is the best value to write.  Also, when changing PGSZID<w>
  35         * fields, the corresponding TLB must be flushed.
  36         */
  37        set_itlbcfg_register(0);
  38        set_dtlbcfg_register(0);
  39#endif
  40        flush_tlb_all();
  41
  42        /* Set rasid register to a known value. */
  43
  44        set_rasid_register(ASID_INSERT(ASID_USER_FIRST));
  45
  46        /* Set PTEVADDR special register to the start of the page
  47         * table, which is in kernel mappable space (ie. not
  48         * statically mapped).  This register's value is undefined on
  49         * reset.
  50         */
  51        set_ptevaddr_register(PGTABLE_START);
  52}
  53
  54struct kmem_cache *pgtable_cache __read_mostly;
  55
  56static void pgd_ctor(void *addr)
  57{
  58        pte_t *ptep = (pte_t *)addr;
  59        int i;
  60
  61        for (i = 0; i < 1024; i++, ptep++)
  62                pte_clear(NULL, 0, ptep);
  63
  64}
  65
  66void __init pgtable_cache_init(void)
  67{
  68        pgtable_cache = kmem_cache_create("pgd",
  69                        PAGE_SIZE, PAGE_SIZE,
  70                        SLAB_HWCACHE_ALIGN,
  71                        pgd_ctor);
  72}
  73