LXR linux/arch/xtensa/variants/fsf/include/variant/tie.h

   1/*
   2 * This header file describes this specific Xtensa processor's TIE extensions
   3 * that extend basic Xtensa core functionality.  It is customized to this
   4 * Xtensa processor configuration.
   5 *
   6 * This file is subject to the terms and conditions of the GNU General Public
   7 * License.  See the file "COPYING" in the main directory of this archive
   8 * for more details.
   9 *
  10 * Copyright (C) 1999-2007 Tensilica Inc.
  11 */
  12
  13#ifndef _XTENSA_CORE_TIE_H
  14#define _XTENSA_CORE_TIE_H
  15
  16#define XCHAL_CP_NUM                    0       /* number of coprocessors */
  17#define XCHAL_CP_MAX                    0       /* max CP ID + 1 (0 if none) */
  18#define XCHAL_CP_MASK                   0x00    /* bitmask of all CPs by ID */
  19#define XCHAL_CP_PORT_MASK              0x00    /* bitmask of only port CPs */
  20
  21/*  Basic parameters of each coprocessor:  */
  22#define XCHAL_CP7_NAME                  "XTIOP"
  23#define XCHAL_CP7_IDENT                 XTIOP
  24#define XCHAL_CP7_SA_SIZE               0       /* size of state save area */
  25#define XCHAL_CP7_SA_ALIGN              1       /* min alignment of save area */
  26#define XCHAL_CP_ID_XTIOP               7       /* coprocessor ID (0..7) */
  27
  28/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
  29#define XCHAL_NCP_SA_SIZE               0
  30#define XCHAL_NCP_SA_ALIGN              1
  31#define XCHAL_CP0_SA_SIZE               0
  32#define XCHAL_CP0_SA_ALIGN              1
  33#define XCHAL_CP1_SA_SIZE               0
  34#define XCHAL_CP1_SA_ALIGN              1
  35#define XCHAL_CP2_SA_SIZE               0
  36#define XCHAL_CP2_SA_ALIGN              1
  37#define XCHAL_CP3_SA_SIZE               0
  38#define XCHAL_CP3_SA_ALIGN              1
  39#define XCHAL_CP4_SA_SIZE               0
  40#define XCHAL_CP4_SA_ALIGN              1
  41#define XCHAL_CP5_SA_SIZE               0
  42#define XCHAL_CP5_SA_ALIGN              1
  43#define XCHAL_CP6_SA_SIZE               0
  44#define XCHAL_CP6_SA_ALIGN              1
  45
  46/*  Save area for non-coprocessor optional and custom (TIE) state:  */
  47#define XCHAL_NCP_SA_SIZE               0
  48#define XCHAL_NCP_SA_ALIGN              1
  49
  50/*  Total save area for optional and custom state (NCP + CPn):  */
  51#define XCHAL_TOTAL_SA_SIZE             0       /* with 16-byte align padding */
  52#define XCHAL_TOTAL_SA_ALIGN            1       /* actual minimum alignment */
  53
  54#define XCHAL_NCP_SA_NUM        0
  55#define XCHAL_NCP_SA_LIST(s)
  56#define XCHAL_CP0_SA_NUM        0
  57#define XCHAL_CP0_SA_LIST(s)
  58#define XCHAL_CP1_SA_NUM        0
  59#define XCHAL_CP1_SA_LIST(s)
  60#define XCHAL_CP2_SA_NUM        0
  61#define XCHAL_CP2_SA_LIST(s)
  62#define XCHAL_CP3_SA_NUM        0
  63#define XCHAL_CP3_SA_LIST(s)
  64#define XCHAL_CP4_SA_NUM        0
  65#define XCHAL_CP4_SA_LIST(s)
  66#define XCHAL_CP5_SA_NUM        0
  67#define XCHAL_CP5_SA_LIST(s)
  68#define XCHAL_CP6_SA_NUM        0
  69#define XCHAL_CP6_SA_LIST(s)
  70#define XCHAL_CP7_SA_NUM        0
  71#define XCHAL_CP7_SA_LIST(s)
  72
  73/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
  74#define XCHAL_OP0_FORMAT_LENGTHS        3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
  75
  76#endif /*_XTENSA_CORE_TIE_H*/
  77
  78