1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <scsi/scsi_host.h>
26#include <linux/libata.h>
27
28#define DRV_NAME "pata_hpt37x"
29#define DRV_VERSION "0.6.23"
30
31struct hpt_clock {
32 u8 xfer_speed;
33 u32 timing;
34};
35
36struct hpt_chip {
37 const char *name;
38 unsigned int base;
39 struct hpt_clock const *clocks[4];
40};
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64static struct hpt_clock hpt37x_timings_33[] = {
65 { XFER_UDMA_6, 0x12446231 },
66 { XFER_UDMA_5, 0x12446231 },
67 { XFER_UDMA_4, 0x12446231 },
68 { XFER_UDMA_3, 0x126c6231 },
69 { XFER_UDMA_2, 0x12486231 },
70 { XFER_UDMA_1, 0x124c6233 },
71 { XFER_UDMA_0, 0x12506297 },
72
73 { XFER_MW_DMA_2, 0x22406c31 },
74 { XFER_MW_DMA_1, 0x22406c33 },
75 { XFER_MW_DMA_0, 0x22406c97 },
76
77 { XFER_PIO_4, 0x06414e31 },
78 { XFER_PIO_3, 0x06414e42 },
79 { XFER_PIO_2, 0x06414e53 },
80 { XFER_PIO_1, 0x06814e93 },
81 { XFER_PIO_0, 0x06814ea7 }
82};
83
84static struct hpt_clock hpt37x_timings_50[] = {
85 { XFER_UDMA_6, 0x12848242 },
86 { XFER_UDMA_5, 0x12848242 },
87 { XFER_UDMA_4, 0x12ac8242 },
88 { XFER_UDMA_3, 0x128c8242 },
89 { XFER_UDMA_2, 0x120c8242 },
90 { XFER_UDMA_1, 0x12148254 },
91 { XFER_UDMA_0, 0x121882ea },
92
93 { XFER_MW_DMA_2, 0x22808242 },
94 { XFER_MW_DMA_1, 0x22808254 },
95 { XFER_MW_DMA_0, 0x228082ea },
96
97 { XFER_PIO_4, 0x0a81f442 },
98 { XFER_PIO_3, 0x0a81f443 },
99 { XFER_PIO_2, 0x0a81f454 },
100 { XFER_PIO_1, 0x0ac1f465 },
101 { XFER_PIO_0, 0x0ac1f48a }
102};
103
104static struct hpt_clock hpt37x_timings_66[] = {
105 { XFER_UDMA_6, 0x1c869c62 },
106 { XFER_UDMA_5, 0x1cae9c62 },
107 { XFER_UDMA_4, 0x1c8a9c62 },
108 { XFER_UDMA_3, 0x1c8e9c62 },
109 { XFER_UDMA_2, 0x1c929c62 },
110 { XFER_UDMA_1, 0x1c9a9c62 },
111 { XFER_UDMA_0, 0x1c829c62 },
112
113 { XFER_MW_DMA_2, 0x2c829c62 },
114 { XFER_MW_DMA_1, 0x2c829c66 },
115 { XFER_MW_DMA_0, 0x2c829d2e },
116
117 { XFER_PIO_4, 0x0c829c62 },
118 { XFER_PIO_3, 0x0c829c84 },
119 { XFER_PIO_2, 0x0c829ca6 },
120 { XFER_PIO_1, 0x0d029d26 },
121 { XFER_PIO_0, 0x0d029d5e }
122};
123
124
125static const struct hpt_chip hpt370 = {
126 "HPT370",
127 48,
128 {
129 hpt37x_timings_33,
130 NULL,
131 NULL,
132 NULL
133 }
134};
135
136static const struct hpt_chip hpt370a = {
137 "HPT370A",
138 48,
139 {
140 hpt37x_timings_33,
141 NULL,
142 hpt37x_timings_50,
143 NULL
144 }
145};
146
147static const struct hpt_chip hpt372 = {
148 "HPT372",
149 55,
150 {
151 hpt37x_timings_33,
152 NULL,
153 hpt37x_timings_50,
154 hpt37x_timings_66
155 }
156};
157
158static const struct hpt_chip hpt302 = {
159 "HPT302",
160 66,
161 {
162 hpt37x_timings_33,
163 NULL,
164 hpt37x_timings_50,
165 hpt37x_timings_66
166 }
167};
168
169static const struct hpt_chip hpt371 = {
170 "HPT371",
171 66,
172 {
173 hpt37x_timings_33,
174 NULL,
175 hpt37x_timings_50,
176 hpt37x_timings_66
177 }
178};
179
180static const struct hpt_chip hpt372a = {
181 "HPT372A",
182 66,
183 {
184 hpt37x_timings_33,
185 NULL,
186 hpt37x_timings_50,
187 hpt37x_timings_66
188 }
189};
190
191static const struct hpt_chip hpt374 = {
192 "HPT374",
193 48,
194 {
195 hpt37x_timings_33,
196 NULL,
197 NULL,
198 NULL
199 }
200};
201
202
203
204
205
206
207
208
209
210
211static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
212{
213 struct hpt_clock *clocks = ap->host->private_data;
214
215 while (clocks->xfer_speed) {
216 if (clocks->xfer_speed == speed)
217 return clocks->timing;
218 clocks++;
219 }
220 BUG();
221 return 0xffffffffU;
222}
223
224static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
225 const char * const list[])
226{
227 unsigned char model_num[ATA_ID_PROD_LEN + 1];
228 int i = 0;
229
230 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
231
232 while (list[i] != NULL) {
233 if (!strcmp(list[i], model_num)) {
234 pr_warn("%s is not supported for %s\n",
235 modestr, list[i]);
236 return 1;
237 }
238 i++;
239 }
240 return 0;
241}
242
243static const char * const bad_ata33[] = {
244 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
245 "Maxtor 90845U3", "Maxtor 90650U2",
246 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
247 "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
248 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
249 "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
250 "Maxtor 90510D4",
251 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
252 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
253 "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
254 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
255 "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
256 NULL
257};
258
259static const char * const bad_ata100_5[] = {
260 "IBM-DTLA-307075",
261 "IBM-DTLA-307060",
262 "IBM-DTLA-307045",
263 "IBM-DTLA-307030",
264 "IBM-DTLA-307020",
265 "IBM-DTLA-307015",
266 "IBM-DTLA-305040",
267 "IBM-DTLA-305030",
268 "IBM-DTLA-305020",
269 "IC35L010AVER07-0",
270 "IC35L020AVER07-0",
271 "IC35L030AVER07-0",
272 "IC35L040AVER07-0",
273 "IC35L060AVER07-0",
274 "WDC AC310200R",
275 NULL
276};
277
278
279
280
281
282
283
284
285static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
286{
287 if (adev->class == ATA_DEV_ATA) {
288 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
289 mask &= ~ATA_MASK_UDMA;
290 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
291 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
292 }
293 return mask;
294}
295
296
297
298
299
300
301
302
303static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
304{
305 if (adev->class == ATA_DEV_ATA) {
306 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
307 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
308 }
309 return mask;
310}
311
312
313
314
315
316
317
318
319
320static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask)
321{
322 if (ata_id_is_sata(adev->id))
323 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
324
325 return mask;
326}
327
328
329
330
331
332
333
334
335static int hpt37x_cable_detect(struct ata_port *ap)
336{
337 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
338 u8 scr2, ata66;
339
340 pci_read_config_byte(pdev, 0x5B, &scr2);
341 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
342
343 udelay(10);
344
345
346 pci_read_config_byte(pdev, 0x5A, &ata66);
347
348 pci_write_config_byte(pdev, 0x5B, scr2);
349
350 if (ata66 & (2 >> ap->port_no))
351 return ATA_CBL_PATA40;
352 else
353 return ATA_CBL_PATA80;
354}
355
356
357
358
359
360
361
362
363static int hpt374_fn1_cable_detect(struct ata_port *ap)
364{
365 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
366 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
367 u16 mcr3;
368 u8 ata66;
369
370
371 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
372
373 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
374 pci_read_config_byte(pdev, 0x5A, &ata66);
375
376 pci_write_config_word(pdev, mcrbase + 2, mcr3);
377
378 if (ata66 & (2 >> ap->port_no))
379 return ATA_CBL_PATA40;
380 else
381 return ATA_CBL_PATA80;
382}
383
384
385
386
387
388
389
390
391
392static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
393{
394 struct ata_port *ap = link->ap;
395 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
396 static const struct pci_bits hpt37x_enable_bits[] = {
397 { 0x50, 1, 0x04, 0x04 },
398 { 0x54, 1, 0x04, 0x04 }
399 };
400
401 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
402 return -ENOENT;
403
404
405 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
406 udelay(100);
407
408 return ata_sff_prereset(link, deadline);
409}
410
411static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev,
412 u8 mode)
413{
414 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
415 u32 addr1, addr2;
416 u32 reg, timing, mask;
417 u8 fast;
418
419 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
420 addr2 = 0x51 + 4 * ap->port_no;
421
422
423 pci_read_config_byte(pdev, addr2, &fast);
424 fast &= ~0x02;
425 fast |= 0x01;
426 pci_write_config_byte(pdev, addr2, fast);
427
428
429 if (mode < XFER_MW_DMA_0)
430 mask = 0xcfc3ffff;
431 else if (mode < XFER_UDMA_0)
432 mask = 0x31c001ff;
433 else
434 mask = 0x303c0000;
435
436 timing = hpt37x_find_mode(ap, mode);
437
438 pci_read_config_dword(pdev, addr1, ®);
439 reg = (reg & ~mask) | (timing & mask);
440 pci_write_config_dword(pdev, addr1, reg);
441}
442
443
444
445
446
447
448
449
450static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
451{
452 hpt370_set_mode(ap, adev, adev->pio_mode);
453}
454
455
456
457
458
459
460
461
462
463static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
464{
465 hpt370_set_mode(ap, adev, adev->dma_mode);
466}
467
468
469
470
471
472
473
474
475static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
476{
477 struct ata_port *ap = qc->ap;
478 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
479 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
480 u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
481 u8 dma_cmd;
482
483 if (dma_stat & ATA_DMA_ACTIVE) {
484 udelay(20);
485 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
486 }
487 if (dma_stat & ATA_DMA_ACTIVE) {
488
489 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
490 udelay(10);
491
492 dma_cmd = ioread8(bmdma + ATA_DMA_CMD);
493 iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD);
494
495 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
496 iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR,
497 bmdma + ATA_DMA_STATUS);
498
499 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
500 udelay(10);
501 }
502 ata_bmdma_stop(qc);
503}
504
505static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev,
506 u8 mode)
507{
508 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
509 u32 addr1, addr2;
510 u32 reg, timing, mask;
511 u8 fast;
512
513 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
514 addr2 = 0x51 + 4 * ap->port_no;
515
516
517 pci_read_config_byte(pdev, addr2, &fast);
518 fast &= ~0x07;
519 pci_write_config_byte(pdev, addr2, fast);
520
521
522 if (mode < XFER_MW_DMA_0)
523 mask = 0xcfc3ffff;
524 else if (mode < XFER_UDMA_0)
525 mask = 0x31c001ff;
526 else
527 mask = 0x303c0000;
528
529 timing = hpt37x_find_mode(ap, mode);
530
531 pci_read_config_dword(pdev, addr1, ®);
532 reg = (reg & ~mask) | (timing & mask);
533 pci_write_config_dword(pdev, addr1, reg);
534}
535
536
537
538
539
540
541
542
543
544static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
545{
546 hpt372_set_mode(ap, adev, adev->pio_mode);
547}
548
549
550
551
552
553
554
555
556
557static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
558{
559 hpt372_set_mode(ap, adev, adev->dma_mode);
560}
561
562
563
564
565
566
567
568
569static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
570{
571 struct ata_port *ap = qc->ap;
572 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
573 int mscreg = 0x50 + 4 * ap->port_no;
574 u8 bwsr_stat, msc_stat;
575
576 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
577 pci_read_config_byte(pdev, mscreg, &msc_stat);
578 if (bwsr_stat & (1 << ap->port_no))
579 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
580 ata_bmdma_stop(qc);
581}
582
583
584static struct scsi_host_template hpt37x_sht = {
585 ATA_BMDMA_SHT(DRV_NAME),
586};
587
588
589
590
591
592static struct ata_port_operations hpt370_port_ops = {
593 .inherits = &ata_bmdma_port_ops,
594
595 .bmdma_stop = hpt370_bmdma_stop,
596
597 .mode_filter = hpt370_filter,
598 .cable_detect = hpt37x_cable_detect,
599 .set_piomode = hpt370_set_piomode,
600 .set_dmamode = hpt370_set_dmamode,
601 .prereset = hpt37x_pre_reset,
602};
603
604
605
606
607
608static struct ata_port_operations hpt370a_port_ops = {
609 .inherits = &hpt370_port_ops,
610 .mode_filter = hpt370a_filter,
611};
612
613
614
615
616
617
618static struct ata_port_operations hpt302_port_ops = {
619 .inherits = &ata_bmdma_port_ops,
620
621 .bmdma_stop = hpt37x_bmdma_stop,
622
623 .cable_detect = hpt37x_cable_detect,
624 .set_piomode = hpt372_set_piomode,
625 .set_dmamode = hpt372_set_dmamode,
626 .prereset = hpt37x_pre_reset,
627};
628
629
630
631
632
633
634static struct ata_port_operations hpt372_port_ops = {
635 .inherits = &hpt302_port_ops,
636 .mode_filter = hpt372_filter,
637};
638
639
640
641
642
643
644static struct ata_port_operations hpt374_fn1_port_ops = {
645 .inherits = &hpt372_port_ops,
646 .cable_detect = hpt374_fn1_cable_detect,
647};
648
649
650
651
652
653
654
655
656
657
658static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
659{
660 unsigned int f = (base * freq) / 192;
661 if (f < 40)
662 return 0;
663 if (f < 45)
664 return 1;
665 if (f < 55)
666 return 2;
667 return 3;
668}
669
670
671
672
673
674
675
676
677
678static int hpt37x_calibrate_dpll(struct pci_dev *dev)
679{
680 u8 reg5b;
681 u32 reg5c;
682 int tries;
683
684 for (tries = 0; tries < 0x5000; tries++) {
685 udelay(50);
686 pci_read_config_byte(dev, 0x5b, ®5b);
687 if (reg5b & 0x80) {
688
689 for (tries = 0; tries < 0x1000; tries++) {
690 pci_read_config_byte(dev, 0x5b, ®5b);
691
692 if ((reg5b & 0x80) == 0)
693 return 0;
694 }
695
696 pci_read_config_dword(dev, 0x5c, ®5c);
697 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
698 return 1;
699 }
700 }
701
702 return 0;
703}
704
705static u32 hpt374_read_freq(struct pci_dev *pdev)
706{
707 u32 freq;
708 unsigned long io_base = pci_resource_start(pdev, 4);
709
710 if (PCI_FUNC(pdev->devfn) & 1) {
711 struct pci_dev *pdev_0;
712
713 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
714
715 if (pdev_0 == NULL)
716 return 0;
717 io_base = pci_resource_start(pdev_0, 4);
718 freq = inl(io_base + 0x90);
719 pci_dev_put(pdev_0);
720 } else
721 freq = inl(io_base + 0x90);
722 return freq;
723}
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
758{
759
760 static const struct ata_port_info info_hpt370 = {
761 .flags = ATA_FLAG_SLAVE_POSS,
762 .pio_mask = ATA_PIO4,
763 .mwdma_mask = ATA_MWDMA2,
764 .udma_mask = ATA_UDMA5,
765 .port_ops = &hpt370_port_ops
766 };
767
768 static const struct ata_port_info info_hpt370a = {
769 .flags = ATA_FLAG_SLAVE_POSS,
770 .pio_mask = ATA_PIO4,
771 .mwdma_mask = ATA_MWDMA2,
772 .udma_mask = ATA_UDMA5,
773 .port_ops = &hpt370a_port_ops
774 };
775
776 static const struct ata_port_info info_hpt370_33 = {
777 .flags = ATA_FLAG_SLAVE_POSS,
778 .pio_mask = ATA_PIO4,
779 .mwdma_mask = ATA_MWDMA2,
780 .udma_mask = ATA_UDMA4,
781 .port_ops = &hpt370_port_ops
782 };
783
784 static const struct ata_port_info info_hpt370a_33 = {
785 .flags = ATA_FLAG_SLAVE_POSS,
786 .pio_mask = ATA_PIO4,
787 .mwdma_mask = ATA_MWDMA2,
788 .udma_mask = ATA_UDMA4,
789 .port_ops = &hpt370a_port_ops
790 };
791
792 static const struct ata_port_info info_hpt372 = {
793 .flags = ATA_FLAG_SLAVE_POSS,
794 .pio_mask = ATA_PIO4,
795 .mwdma_mask = ATA_MWDMA2,
796 .udma_mask = ATA_UDMA6,
797 .port_ops = &hpt372_port_ops
798 };
799
800 static const struct ata_port_info info_hpt302 = {
801 .flags = ATA_FLAG_SLAVE_POSS,
802 .pio_mask = ATA_PIO4,
803 .mwdma_mask = ATA_MWDMA2,
804 .udma_mask = ATA_UDMA6,
805 .port_ops = &hpt302_port_ops
806 };
807
808 static const struct ata_port_info info_hpt374_fn0 = {
809 .flags = ATA_FLAG_SLAVE_POSS,
810 .pio_mask = ATA_PIO4,
811 .mwdma_mask = ATA_MWDMA2,
812 .udma_mask = ATA_UDMA5,
813 .port_ops = &hpt372_port_ops
814 };
815 static const struct ata_port_info info_hpt374_fn1 = {
816 .flags = ATA_FLAG_SLAVE_POSS,
817 .pio_mask = ATA_PIO4,
818 .mwdma_mask = ATA_MWDMA2,
819 .udma_mask = ATA_UDMA5,
820 .port_ops = &hpt374_fn1_port_ops
821 };
822
823 static const int MHz[4] = { 33, 40, 50, 66 };
824 void *private_data = NULL;
825 const struct ata_port_info *ppi[] = { NULL, NULL };
826 u8 rev = dev->revision;
827 u8 irqmask;
828 u8 mcr1;
829 u32 freq;
830 int prefer_dpll = 1;
831
832 unsigned long iobase = pci_resource_start(dev, 4);
833
834 const struct hpt_chip *chip_table;
835 int clock_slot;
836 int rc;
837
838 rc = pcim_enable_device(dev);
839 if (rc)
840 return rc;
841
842 switch (dev->device) {
843 case PCI_DEVICE_ID_TTI_HPT366:
844
845
846 if (rev < 3)
847 return -ENODEV;
848
849 if (rev == 6)
850 return -ENODEV;
851
852 switch (rev) {
853 case 3:
854 ppi[0] = &info_hpt370;
855 chip_table = &hpt370;
856 prefer_dpll = 0;
857 break;
858 case 4:
859 ppi[0] = &info_hpt370a;
860 chip_table = &hpt370a;
861 prefer_dpll = 0;
862 break;
863 case 5:
864 ppi[0] = &info_hpt372;
865 chip_table = &hpt372;
866 break;
867 default:
868 pr_err("Unknown HPT366 subtype, please report (%d)\n",
869 rev);
870 return -ENODEV;
871 }
872 break;
873 case PCI_DEVICE_ID_TTI_HPT372:
874
875 if (rev >= 2)
876 return -ENODEV;
877 ppi[0] = &info_hpt372;
878 chip_table = &hpt372a;
879 break;
880 case PCI_DEVICE_ID_TTI_HPT302:
881
882 if (rev > 1)
883 return -ENODEV;
884 ppi[0] = &info_hpt302;
885
886 chip_table = &hpt302;
887 break;
888 case PCI_DEVICE_ID_TTI_HPT371:
889 if (rev > 1)
890 return -ENODEV;
891 ppi[0] = &info_hpt302;
892 chip_table = &hpt371;
893
894
895
896
897 pci_read_config_byte(dev, 0x50, &mcr1);
898 mcr1 &= ~0x04;
899 pci_write_config_byte(dev, 0x50, mcr1);
900 break;
901 case PCI_DEVICE_ID_TTI_HPT374:
902 chip_table = &hpt374;
903 if (!(PCI_FUNC(dev->devfn) & 1))
904 *ppi = &info_hpt374_fn0;
905 else
906 *ppi = &info_hpt374_fn1;
907 break;
908 default:
909 pr_err("PCI table is bogus, please report (%d)\n", dev->device);
910 return -ENODEV;
911 }
912
913
914 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
915 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
916 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
917 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
918
919 pci_read_config_byte(dev, 0x5A, &irqmask);
920 irqmask &= ~0x10;
921 pci_write_config_byte(dev, 0x5a, irqmask);
922
923
924
925
926
927
928
929
930 pci_write_config_byte(dev, 0x5b, 0x23);
931
932
933
934
935
936 if (chip_table == &hpt372a)
937 outb(0x0e, iobase + 0x9c);
938
939
940
941
942
943
944
945 if (chip_table == &hpt374) {
946 freq = hpt374_read_freq(dev);
947 if (freq == 0)
948 return -ENODEV;
949 } else
950 freq = inl(iobase + 0x90);
951
952 if ((freq >> 12) != 0xABCDE) {
953 int i;
954 u8 sr;
955 u32 total = 0;
956
957 pr_warn("BIOS has not set timing clocks\n");
958
959
960 for (i = 0; i < 128; i++) {
961 pci_read_config_byte(dev, 0x78, &sr);
962 total += sr & 0x1FF;
963 udelay(15);
964 }
965 freq = total / 128;
966 }
967 freq &= 0x1FF;
968
969
970
971
972
973
974 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
975 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
976
977
978
979
980
981
982 unsigned int f_low, f_high;
983 int dpll, adjust;
984
985
986 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
987
988 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
989 f_high = f_low + 2;
990 if (clock_slot > 1)
991 f_high += 2;
992
993
994 pci_write_config_byte(dev, 0x5b, 0x21);
995 pci_write_config_dword(dev, 0x5C,
996 (f_high << 16) | f_low | 0x100);
997
998 for (adjust = 0; adjust < 8; adjust++) {
999 if (hpt37x_calibrate_dpll(dev))
1000 break;
1001
1002
1003
1004
1005 if (adjust & 1)
1006 f_low -= adjust >> 1;
1007 else
1008 f_high += adjust >> 1;
1009 pci_write_config_dword(dev, 0x5C,
1010 (f_high << 16) | f_low | 0x100);
1011 }
1012 if (adjust == 8) {
1013 pr_err("DPLL did not stabilize!\n");
1014 return -ENODEV;
1015 }
1016 if (dpll == 3)
1017 private_data = (void *)hpt37x_timings_66;
1018 else
1019 private_data = (void *)hpt37x_timings_50;
1020
1021 pr_info("bus clock %dMHz, using %dMHz DPLL\n",
1022 MHz[clock_slot], MHz[dpll]);
1023 } else {
1024 private_data = (void *)chip_table->clocks[clock_slot];
1025
1026
1027
1028
1029
1030
1031 if (clock_slot < 2 && ppi[0] == &info_hpt370)
1032 ppi[0] = &info_hpt370_33;
1033 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
1034 ppi[0] = &info_hpt370a_33;
1035
1036 pr_info("%s using %dMHz bus clock\n",
1037 chip_table->name, MHz[clock_slot]);
1038 }
1039
1040
1041 return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0);
1042}
1043
1044static const struct pci_device_id hpt37x[] = {
1045 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1046 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1047 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1048 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1049 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1050
1051 { },
1052};
1053
1054static struct pci_driver hpt37x_pci_driver = {
1055 .name = DRV_NAME,
1056 .id_table = hpt37x,
1057 .probe = hpt37x_init_one,
1058 .remove = ata_pci_remove_one
1059};
1060
1061module_pci_driver(hpt37x_pci_driver);
1062
1063MODULE_AUTHOR("Alan Cox");
1064MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1065MODULE_LICENSE("GPL");
1066MODULE_DEVICE_TABLE(pci, hpt37x);
1067MODULE_VERSION(DRV_VERSION);
1068