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31#define TALITOS_TIMEOUT 100000
32#define TALITOS_MAX_DATA_LEN 65535
33
34#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
35#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
36#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
37
38
39struct talitos_ptr {
40 __be16 len;
41 u8 j_extent;
42 u8 eptr;
43 __be32 ptr;
44};
45
46static const struct talitos_ptr zero_entry = {
47 .len = 0,
48 .j_extent = 0,
49 .eptr = 0,
50 .ptr = 0
51};
52
53
54struct talitos_desc {
55 __be32 hdr;
56 __be32 hdr_lo;
57 struct talitos_ptr ptr[7];
58};
59
60
61
62
63
64
65
66
67struct talitos_request {
68 struct talitos_desc *desc;
69 dma_addr_t dma_desc;
70 void (*callback) (struct device *dev, struct talitos_desc *desc,
71 void *context, int error);
72 void *context;
73};
74
75
76struct talitos_channel {
77 void __iomem *reg;
78
79
80 struct talitos_request *fifo;
81
82
83 atomic_t submit_count ____cacheline_aligned;
84
85
86 spinlock_t head_lock ____cacheline_aligned;
87
88 int head;
89
90
91 spinlock_t tail_lock ____cacheline_aligned;
92
93 int tail;
94};
95
96struct talitos_private {
97 struct device *dev;
98 struct platform_device *ofdev;
99 void __iomem *reg;
100 int irq[2];
101
102
103 spinlock_t reg_lock ____cacheline_aligned;
104
105
106 unsigned int num_channels;
107 unsigned int chfifo_len;
108 unsigned int exec_units;
109 unsigned int desc_types;
110
111
112 unsigned long features;
113
114
115
116
117
118
119 unsigned int fifo_len;
120
121 struct talitos_channel *chan;
122
123
124 atomic_t last_chan ____cacheline_aligned;
125
126
127 struct tasklet_struct done_task[2];
128
129
130 struct list_head alg_list;
131
132
133 struct hwrng rng;
134};
135
136extern int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
137 void (*callback)(struct device *dev,
138 struct talitos_desc *desc,
139 void *context, int error),
140 void *context);
141
142
143#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
144#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
145#define TALITOS_FTR_SHA224_HWINIT 0x00000004
146#define TALITOS_FTR_HMAC_OK 0x00000008
147
148
149
150
151
152
153#define TALITOS_MCR 0x1030
154#define TALITOS_MCR_RCA0 (1 << 15)
155#define TALITOS_MCR_RCA1 (1 << 14)
156#define TALITOS_MCR_RCA2 (1 << 13)
157#define TALITOS_MCR_RCA3 (1 << 12)
158#define TALITOS_MCR_SWR 0x1
159#define TALITOS_MCR_LO 0x1034
160#define TALITOS_IMR 0x1008
161#define TALITOS_IMR_INIT 0x100ff
162#define TALITOS_IMR_DONE 0x00055
163#define TALITOS_IMR_LO 0x100C
164#define TALITOS_IMR_LO_INIT 0x20000
165#define TALITOS_ISR 0x1010
166#define TALITOS_ISR_4CHERR 0xaa
167#define TALITOS_ISR_4CHDONE 0x55
168#define TALITOS_ISR_CH_0_2_ERR 0x22
169#define TALITOS_ISR_CH_0_2_DONE 0x11
170#define TALITOS_ISR_CH_1_3_ERR 0x88
171#define TALITOS_ISR_CH_1_3_DONE 0x44
172#define TALITOS_ISR_LO 0x1014
173#define TALITOS_ICR 0x1018
174#define TALITOS_ICR_LO 0x101C
175
176
177#define TALITOS_CH_BASE_OFFSET 0x1000
178#define TALITOS_CH_STRIDE 0x100
179
180
181#define TALITOS_CCCR 0x8
182#define TALITOS_CCCR_CONT 0x2
183#define TALITOS_CCCR_RESET 0x1
184#define TALITOS_CCCR_LO 0xc
185#define TALITOS_CCCR_LO_IWSE 0x80
186#define TALITOS_CCCR_LO_EAE 0x20
187#define TALITOS_CCCR_LO_CDWE 0x10
188#define TALITOS_CCCR_LO_NT 0x4
189#define TALITOS_CCCR_LO_CDIE 0x2
190
191
192#define TALITOS_CCPSR 0x10
193#define TALITOS_CCPSR_LO 0x14
194#define TALITOS_CCPSR_LO_DOF 0x8000
195#define TALITOS_CCPSR_LO_SOF 0x4000
196#define TALITOS_CCPSR_LO_MDTE 0x2000
197#define TALITOS_CCPSR_LO_SGDLZ 0x1000
198#define TALITOS_CCPSR_LO_FPZ 0x0800
199#define TALITOS_CCPSR_LO_IDH 0x0400
200#define TALITOS_CCPSR_LO_IEU 0x0200
201#define TALITOS_CCPSR_LO_EU 0x0100
202#define TALITOS_CCPSR_LO_GB 0x0080
203#define TALITOS_CCPSR_LO_GRL 0x0040
204#define TALITOS_CCPSR_LO_SB 0x0020
205#define TALITOS_CCPSR_LO_SRL 0x0010
206
207
208#define TALITOS_FF 0x48
209#define TALITOS_FF_LO 0x4c
210
211
212#define TALITOS_CDPR 0x40
213#define TALITOS_CDPR_LO 0x44
214
215
216#define TALITOS_DESCBUF 0x80
217#define TALITOS_DESCBUF_LO 0x84
218
219
220#define TALITOS_GATHER 0xc0
221#define TALITOS_GATHER_LO 0xc4
222
223
224#define TALITOS_SCATTER 0xe0
225#define TALITOS_SCATTER_LO 0xe4
226
227
228#define TALITOS_DEUISR 0x2030
229#define TALITOS_DEUISR_LO 0x2034
230#define TALITOS_AESUISR 0x4030
231#define TALITOS_AESUISR_LO 0x4034
232#define TALITOS_MDEUISR 0x6030
233#define TALITOS_MDEUISR_LO 0x6034
234#define TALITOS_MDEUICR 0x6038
235#define TALITOS_MDEUICR_LO 0x603c
236#define TALITOS_MDEUICR_LO_ICE 0x4000
237#define TALITOS_AFEUISR 0x8030
238#define TALITOS_AFEUISR_LO 0x8034
239#define TALITOS_RNGUISR 0xa030
240#define TALITOS_RNGUISR_LO 0xa034
241#define TALITOS_RNGUSR 0xa028
242#define TALITOS_RNGUSR_LO 0xa02c
243#define TALITOS_RNGUSR_LO_RD 0x1
244#define TALITOS_RNGUSR_LO_OFL 0xff0000
245#define TALITOS_RNGUDSR 0xa010
246#define TALITOS_RNGUDSR_LO 0xa014
247#define TALITOS_RNGU_FIFO 0xa800
248#define TALITOS_RNGU_FIFO_LO 0xa804
249#define TALITOS_RNGURCR 0xa018
250#define TALITOS_RNGURCR_LO 0xa01c
251#define TALITOS_RNGURCR_LO_SR 0x1
252#define TALITOS_PKEUISR 0xc030
253#define TALITOS_PKEUISR_LO 0xc034
254#define TALITOS_KEUISR 0xe030
255#define TALITOS_KEUISR_LO 0xe034
256#define TALITOS_CRCUISR 0xf030
257#define TALITOS_CRCUISR_LO 0xf034
258
259#define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28
260#define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48
261
262
263
264
265
266
267#define DESC_HDR_DONE cpu_to_be32(0xff000000)
268#define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
269#define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
270#define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
271
272
273#define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
274#define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
275#define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
276#define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
277#define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
278#define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
279#define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
280#define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
281#define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
282#define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
283
284
285#define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
286#define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
287#define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
288#define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
289#define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
290#define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
291#define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
292#define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
293#define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
294#define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
295#define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
296#define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
297#define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
298#define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
299#define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
300 DESC_HDR_MODE0_MDEU_HMAC)
301#define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
302 DESC_HDR_MODE0_MDEU_HMAC)
303#define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \
304 DESC_HDR_MODE0_MDEU_HMAC)
305
306
307#define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
308#define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
309#define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
310#define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
311
312
313#define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
314#define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
315#define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
316#define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
317#define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
318#define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
319#define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
320#define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
321#define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
322#define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
323#define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
324 DESC_HDR_MODE1_MDEU_HMAC)
325#define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
326 DESC_HDR_MODE1_MDEU_HMAC)
327#define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
328 DESC_HDR_MODE1_MDEU_HMAC)
329#define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \
330 DESC_HDR_MODE1_MDEU_HMAC)
331#define DESC_HDR_MODE1_MDEUB_SHA384_HMAC (DESC_HDR_MODE1_MDEUB_SHA384 | \
332 DESC_HDR_MODE1_MDEU_HMAC)
333#define DESC_HDR_MODE1_MDEUB_SHA512_HMAC (DESC_HDR_MODE1_MDEUB_SHA512 | \
334 DESC_HDR_MODE1_MDEU_HMAC)
335
336
337#define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
338
339
340#define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
341
342
343#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
344#define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
345#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
346#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
347
348
349#define DESC_PTR_LNKTBL_JUMP 0x80
350#define DESC_PTR_LNKTBL_RETURN 0x02
351#define DESC_PTR_LNKTBL_NEXT 0x01
352