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30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34
35#include "i915_reg.h"
36#include "intel_bios.h"
37#include "intel_ringbuffer.h"
38#include <linux/io-mapping.h>
39#include <linux/i2c.h>
40#include <linux/i2c-algo-bit.h>
41#include <drm/intel-gtt.h>
42#include <linux/backlight.h>
43#include <linux/intel-iommu.h>
44#include <linux/kref.h>
45#include <linux/pm_qos.h>
46
47
48
49
50#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
51
52#define DRIVER_NAME "i915"
53#define DRIVER_DESC "Intel Graphics"
54#define DRIVER_DATE "20080730"
55
56enum pipe {
57 PIPE_A = 0,
58 PIPE_B,
59 PIPE_C,
60 I915_MAX_PIPES
61};
62#define pipe_name(p) ((p) + 'A')
63
64enum transcoder {
65 TRANSCODER_A = 0,
66 TRANSCODER_B,
67 TRANSCODER_C,
68 TRANSCODER_EDP = 0xF,
69};
70#define transcoder_name(t) ((t) + 'A')
71
72enum plane {
73 PLANE_A = 0,
74 PLANE_B,
75 PLANE_C,
76};
77#define plane_name(p) ((p) + 'A')
78
79enum port {
80 PORT_A = 0,
81 PORT_B,
82 PORT_C,
83 PORT_D,
84 PORT_E,
85 I915_MAX_PORTS
86};
87#define port_name(p) ((p) + 'A')
88
89enum hpd_pin {
90 HPD_NONE = 0,
91 HPD_PORT_A = HPD_NONE,
92 HPD_TV = HPD_NONE,
93 HPD_CRT,
94 HPD_SDVO_B,
95 HPD_SDVO_C,
96 HPD_PORT_B,
97 HPD_PORT_C,
98 HPD_PORT_D,
99 HPD_NUM_PINS
100};
101
102#define I915_GEM_GPU_DOMAINS \
103 (I915_GEM_DOMAIN_RENDER | \
104 I915_GEM_DOMAIN_SAMPLER | \
105 I915_GEM_DOMAIN_COMMAND | \
106 I915_GEM_DOMAIN_INSTRUCTION | \
107 I915_GEM_DOMAIN_VERTEX)
108
109#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
110
111#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
112 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
113 if ((intel_encoder)->base.crtc == (__crtc))
114
115struct intel_pch_pll {
116 int refcount;
117 int active;
118 bool on;
119 int pll_reg;
120 int fp0_reg;
121 int fp1_reg;
122};
123#define I915_NUM_PLLS 2
124
125
126struct intel_link_m_n {
127 uint32_t tu;
128 uint32_t gmch_m;
129 uint32_t gmch_n;
130 uint32_t link_m;
131 uint32_t link_n;
132};
133
134void intel_link_compute_m_n(int bpp, int nlanes,
135 int pixel_clock, int link_clock,
136 struct intel_link_m_n *m_n);
137
138struct intel_ddi_plls {
139 int spll_refcount;
140 int wrpll1_refcount;
141 int wrpll2_refcount;
142};
143
144
145
146
147
148
149
150
151
152
153
154#define DRIVER_MAJOR 1
155#define DRIVER_MINOR 6
156#define DRIVER_PATCHLEVEL 0
157
158#define WATCH_COHERENCY 0
159#define WATCH_LISTS 0
160#define WATCH_GTT 0
161
162#define I915_GEM_PHYS_CURSOR_0 1
163#define I915_GEM_PHYS_CURSOR_1 2
164#define I915_GEM_PHYS_OVERLAY_REGS 3
165#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
166
167struct drm_i915_gem_phys_object {
168 int id;
169 struct page **page_list;
170 drm_dma_handle_t *handle;
171 struct drm_i915_gem_object *cur_obj;
172};
173
174struct opregion_header;
175struct opregion_acpi;
176struct opregion_swsci;
177struct opregion_asle;
178struct drm_i915_private;
179
180struct intel_opregion {
181 struct opregion_header __iomem *header;
182 struct opregion_acpi __iomem *acpi;
183 struct opregion_swsci __iomem *swsci;
184 struct opregion_asle __iomem *asle;
185 void __iomem *vbt;
186 u32 __iomem *lid_state;
187};
188#define OPREGION_SIZE (8*1024)
189
190struct intel_overlay;
191struct intel_overlay_error_state;
192
193struct drm_i915_master_private {
194 drm_local_map_t *sarea;
195 struct _drm_i915_sarea *sarea_priv;
196};
197#define I915_FENCE_REG_NONE -1
198#define I915_MAX_NUM_FENCES 32
199
200#define I915_MAX_NUM_FENCE_BITS 6
201
202struct drm_i915_fence_reg {
203 struct list_head lru_list;
204 struct drm_i915_gem_object *obj;
205 int pin_count;
206};
207
208struct sdvo_device_mapping {
209 u8 initialized;
210 u8 dvo_port;
211 u8 slave_addr;
212 u8 dvo_wiring;
213 u8 i2c_pin;
214 u8 ddc_pin;
215};
216
217struct intel_display_error_state;
218
219struct drm_i915_error_state {
220 struct kref ref;
221 u32 eir;
222 u32 pgtbl_er;
223 u32 ier;
224 u32 ccid;
225 u32 derrmr;
226 u32 forcewake;
227 bool waiting[I915_NUM_RINGS];
228 u32 pipestat[I915_MAX_PIPES];
229 u32 tail[I915_NUM_RINGS];
230 u32 head[I915_NUM_RINGS];
231 u32 ctl[I915_NUM_RINGS];
232 u32 ipeir[I915_NUM_RINGS];
233 u32 ipehr[I915_NUM_RINGS];
234 u32 instdone[I915_NUM_RINGS];
235 u32 acthd[I915_NUM_RINGS];
236 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
237 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
238 u32 rc_psmi[I915_NUM_RINGS];
239
240 u32 cpu_ring_head[I915_NUM_RINGS];
241 u32 cpu_ring_tail[I915_NUM_RINGS];
242 u32 error;
243 u32 err_int;
244 u32 instpm[I915_NUM_RINGS];
245 u32 instps[I915_NUM_RINGS];
246 u32 extra_instdone[I915_NUM_INSTDONE_REG];
247 u32 seqno[I915_NUM_RINGS];
248 u64 bbaddr;
249 u32 fault_reg[I915_NUM_RINGS];
250 u32 done_reg;
251 u32 faddr[I915_NUM_RINGS];
252 u64 fence[I915_MAX_NUM_FENCES];
253 struct timeval time;
254 struct drm_i915_error_ring {
255 struct drm_i915_error_object {
256 int page_count;
257 u32 gtt_offset;
258 u32 *pages[0];
259 } *ringbuffer, *batchbuffer, *ctx;
260 struct drm_i915_error_request {
261 long jiffies;
262 u32 seqno;
263 u32 tail;
264 } *requests;
265 int num_requests;
266 } ring[I915_NUM_RINGS];
267 struct drm_i915_error_buffer {
268 u32 size;
269 u32 name;
270 u32 rseqno, wseqno;
271 u32 gtt_offset;
272 u32 read_domains;
273 u32 write_domain;
274 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
275 s32 pinned:2;
276 u32 tiling:2;
277 u32 dirty:1;
278 u32 purgeable:1;
279 s32 ring:4;
280 u32 cache_level:2;
281 } *active_bo, *pinned_bo;
282 u32 active_bo_count, pinned_bo_count;
283 struct intel_overlay_error_state *overlay;
284 struct intel_display_error_state *display;
285};
286
287struct intel_crtc_config;
288struct intel_crtc;
289
290struct drm_i915_display_funcs {
291 bool (*fbc_enabled)(struct drm_device *dev);
292 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
293 void (*disable_fbc)(struct drm_device *dev);
294 int (*get_display_clock_speed)(struct drm_device *dev);
295 int (*get_fifo_size)(struct drm_device *dev, int plane);
296 void (*update_wm)(struct drm_device *dev);
297 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
298 uint32_t sprite_width, int pixel_size);
299 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
300 struct drm_display_mode *mode);
301 void (*modeset_global_resources)(struct drm_device *dev);
302
303
304 bool (*get_pipe_config)(struct intel_crtc *,
305 struct intel_crtc_config *);
306 int (*crtc_mode_set)(struct drm_crtc *crtc,
307 int x, int y,
308 struct drm_framebuffer *old_fb);
309 void (*crtc_enable)(struct drm_crtc *crtc);
310 void (*crtc_disable)(struct drm_crtc *crtc);
311 void (*off)(struct drm_crtc *crtc);
312 void (*write_eld)(struct drm_connector *connector,
313 struct drm_crtc *crtc);
314 void (*fdi_link_train)(struct drm_crtc *crtc);
315 void (*init_clock_gating)(struct drm_device *dev);
316 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
317 struct drm_framebuffer *fb,
318 struct drm_i915_gem_object *obj);
319 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
320 int x, int y);
321 void (*hpd_irq_setup)(struct drm_device *dev);
322
323
324
325
326
327};
328
329struct drm_i915_gt_funcs {
330 void (*force_wake_get)(struct drm_i915_private *dev_priv);
331 void (*force_wake_put)(struct drm_i915_private *dev_priv);
332};
333
334#define DEV_INFO_FLAGS \
335 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
336 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
337 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
338 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
339 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
340 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
341 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
342 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
343 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
344 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
345 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
346 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
347 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
348 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
349 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
350 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
351 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
352 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
353 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
354 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
355 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
356 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
357 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
358 DEV_INFO_FLAG(has_llc)
359
360struct intel_device_info {
361 u32 display_mmio_offset;
362 u8 num_pipes:3;
363 u8 gen;
364 u8 is_mobile:1;
365 u8 is_i85x:1;
366 u8 is_i915g:1;
367 u8 is_i945gm:1;
368 u8 is_g33:1;
369 u8 need_gfx_hws:1;
370 u8 is_g4x:1;
371 u8 is_pineview:1;
372 u8 is_broadwater:1;
373 u8 is_crestline:1;
374 u8 is_ivybridge:1;
375 u8 is_valleyview:1;
376 u8 has_force_wake:1;
377 u8 is_haswell:1;
378 u8 has_fbc:1;
379 u8 has_pipe_cxsr:1;
380 u8 has_hotplug:1;
381 u8 cursor_needs_physical:1;
382 u8 has_overlay:1;
383 u8 overlay_needs_physical:1;
384 u8 supports_tv:1;
385 u8 has_bsd_ring:1;
386 u8 has_blt_ring:1;
387 u8 has_llc:1;
388};
389
390enum i915_cache_level {
391 I915_CACHE_NONE = 0,
392 I915_CACHE_LLC,
393 I915_CACHE_LLC_MLC,
394};
395
396
397
398
399
400
401
402
403struct i915_gtt {
404 unsigned long start;
405 size_t total;
406 size_t stolen_size;
407
408 unsigned long mappable_end;
409 struct io_mapping *mappable;
410 phys_addr_t mappable_base;
411
412
413 void __iomem *gsm;
414
415 bool do_idle_maps;
416 dma_addr_t scratch_page_dma;
417 struct page *scratch_page;
418
419
420 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
421 size_t *stolen, phys_addr_t *mappable_base,
422 unsigned long *mappable_end);
423 void (*gtt_remove)(struct drm_device *dev);
424 void (*gtt_clear_range)(struct drm_device *dev,
425 unsigned int first_entry,
426 unsigned int num_entries);
427 void (*gtt_insert_entries)(struct drm_device *dev,
428 struct sg_table *st,
429 unsigned int pg_start,
430 enum i915_cache_level cache_level);
431};
432#define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
433
434#define I915_PPGTT_PD_ENTRIES 512
435#define I915_PPGTT_PT_ENTRIES 1024
436struct i915_hw_ppgtt {
437 struct drm_device *dev;
438 unsigned num_pd_entries;
439 struct page **pt_pages;
440 uint32_t pd_offset;
441 dma_addr_t *pt_dma_addr;
442 dma_addr_t scratch_page_dma_addr;
443
444
445 void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
446 unsigned int first_entry,
447 unsigned int num_entries);
448 void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
449 struct sg_table *st,
450 unsigned int pg_start,
451 enum i915_cache_level cache_level);
452 int (*enable)(struct drm_device *dev);
453 void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
454};
455
456
457
458#define DEFAULT_CONTEXT_ID 0
459struct i915_hw_context {
460 int id;
461 bool is_initialized;
462 struct drm_i915_file_private *file_priv;
463 struct intel_ring_buffer *ring;
464 struct drm_i915_gem_object *obj;
465};
466
467enum no_fbc_reason {
468 FBC_NO_OUTPUT,
469 FBC_STOLEN_TOO_SMALL,
470 FBC_UNSUPPORTED_MODE,
471 FBC_MODE_TOO_LARGE,
472 FBC_BAD_PLANE,
473 FBC_NOT_TILED,
474 FBC_MULTIPLE_PIPES,
475 FBC_MODULE_PARAM,
476};
477
478enum intel_pch {
479 PCH_NONE = 0,
480 PCH_IBX,
481 PCH_CPT,
482 PCH_LPT,
483 PCH_NOP,
484};
485
486enum intel_sbi_destination {
487 SBI_ICLK,
488 SBI_MPHY,
489};
490
491#define QUIRK_PIPEA_FORCE (1<<0)
492#define QUIRK_LVDS_SSC_DISABLE (1<<1)
493#define QUIRK_INVERT_BRIGHTNESS (1<<2)
494
495struct intel_fbdev;
496struct intel_fbc_work;
497
498struct intel_gmbus {
499 struct i2c_adapter adapter;
500 u32 force_bit;
501 u32 reg0;
502 u32 gpio_reg;
503 struct i2c_algo_bit_data bit_algo;
504 struct drm_i915_private *dev_priv;
505};
506
507struct i915_suspend_saved_registers {
508 u8 saveLBB;
509 u32 saveDSPACNTR;
510 u32 saveDSPBCNTR;
511 u32 saveDSPARB;
512 u32 savePIPEACONF;
513 u32 savePIPEBCONF;
514 u32 savePIPEASRC;
515 u32 savePIPEBSRC;
516 u32 saveFPA0;
517 u32 saveFPA1;
518 u32 saveDPLL_A;
519 u32 saveDPLL_A_MD;
520 u32 saveHTOTAL_A;
521 u32 saveHBLANK_A;
522 u32 saveHSYNC_A;
523 u32 saveVTOTAL_A;
524 u32 saveVBLANK_A;
525 u32 saveVSYNC_A;
526 u32 saveBCLRPAT_A;
527 u32 saveTRANSACONF;
528 u32 saveTRANS_HTOTAL_A;
529 u32 saveTRANS_HBLANK_A;
530 u32 saveTRANS_HSYNC_A;
531 u32 saveTRANS_VTOTAL_A;
532 u32 saveTRANS_VBLANK_A;
533 u32 saveTRANS_VSYNC_A;
534 u32 savePIPEASTAT;
535 u32 saveDSPASTRIDE;
536 u32 saveDSPASIZE;
537 u32 saveDSPAPOS;
538 u32 saveDSPAADDR;
539 u32 saveDSPASURF;
540 u32 saveDSPATILEOFF;
541 u32 savePFIT_PGM_RATIOS;
542 u32 saveBLC_HIST_CTL;
543 u32 saveBLC_PWM_CTL;
544 u32 saveBLC_PWM_CTL2;
545 u32 saveBLC_CPU_PWM_CTL;
546 u32 saveBLC_CPU_PWM_CTL2;
547 u32 saveFPB0;
548 u32 saveFPB1;
549 u32 saveDPLL_B;
550 u32 saveDPLL_B_MD;
551 u32 saveHTOTAL_B;
552 u32 saveHBLANK_B;
553 u32 saveHSYNC_B;
554 u32 saveVTOTAL_B;
555 u32 saveVBLANK_B;
556 u32 saveVSYNC_B;
557 u32 saveBCLRPAT_B;
558 u32 saveTRANSBCONF;
559 u32 saveTRANS_HTOTAL_B;
560 u32 saveTRANS_HBLANK_B;
561 u32 saveTRANS_HSYNC_B;
562 u32 saveTRANS_VTOTAL_B;
563 u32 saveTRANS_VBLANK_B;
564 u32 saveTRANS_VSYNC_B;
565 u32 savePIPEBSTAT;
566 u32 saveDSPBSTRIDE;
567 u32 saveDSPBSIZE;
568 u32 saveDSPBPOS;
569 u32 saveDSPBADDR;
570 u32 saveDSPBSURF;
571 u32 saveDSPBTILEOFF;
572 u32 saveVGA0;
573 u32 saveVGA1;
574 u32 saveVGA_PD;
575 u32 saveVGACNTRL;
576 u32 saveADPA;
577 u32 saveLVDS;
578 u32 savePP_ON_DELAYS;
579 u32 savePP_OFF_DELAYS;
580 u32 saveDVOA;
581 u32 saveDVOB;
582 u32 saveDVOC;
583 u32 savePP_ON;
584 u32 savePP_OFF;
585 u32 savePP_CONTROL;
586 u32 savePP_DIVISOR;
587 u32 savePFIT_CONTROL;
588 u32 save_palette_a[256];
589 u32 save_palette_b[256];
590 u32 saveDPFC_CB_BASE;
591 u32 saveFBC_CFB_BASE;
592 u32 saveFBC_LL_BASE;
593 u32 saveFBC_CONTROL;
594 u32 saveFBC_CONTROL2;
595 u32 saveIER;
596 u32 saveIIR;
597 u32 saveIMR;
598 u32 saveDEIER;
599 u32 saveDEIMR;
600 u32 saveGTIER;
601 u32 saveGTIMR;
602 u32 saveFDI_RXA_IMR;
603 u32 saveFDI_RXB_IMR;
604 u32 saveCACHE_MODE_0;
605 u32 saveMI_ARB_STATE;
606 u32 saveSWF0[16];
607 u32 saveSWF1[16];
608 u32 saveSWF2[3];
609 u8 saveMSR;
610 u8 saveSR[8];
611 u8 saveGR[25];
612 u8 saveAR_INDEX;
613 u8 saveAR[21];
614 u8 saveDACMASK;
615 u8 saveCR[37];
616 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
617 u32 saveCURACNTR;
618 u32 saveCURAPOS;
619 u32 saveCURABASE;
620 u32 saveCURBCNTR;
621 u32 saveCURBPOS;
622 u32 saveCURBBASE;
623 u32 saveCURSIZE;
624 u32 saveDP_B;
625 u32 saveDP_C;
626 u32 saveDP_D;
627 u32 savePIPEA_GMCH_DATA_M;
628 u32 savePIPEB_GMCH_DATA_M;
629 u32 savePIPEA_GMCH_DATA_N;
630 u32 savePIPEB_GMCH_DATA_N;
631 u32 savePIPEA_DP_LINK_M;
632 u32 savePIPEB_DP_LINK_M;
633 u32 savePIPEA_DP_LINK_N;
634 u32 savePIPEB_DP_LINK_N;
635 u32 saveFDI_RXA_CTL;
636 u32 saveFDI_TXA_CTL;
637 u32 saveFDI_RXB_CTL;
638 u32 saveFDI_TXB_CTL;
639 u32 savePFA_CTL_1;
640 u32 savePFB_CTL_1;
641 u32 savePFA_WIN_SZ;
642 u32 savePFB_WIN_SZ;
643 u32 savePFA_WIN_POS;
644 u32 savePFB_WIN_POS;
645 u32 savePCH_DREF_CONTROL;
646 u32 saveDISP_ARB_CTL;
647 u32 savePIPEA_DATA_M1;
648 u32 savePIPEA_DATA_N1;
649 u32 savePIPEA_LINK_M1;
650 u32 savePIPEA_LINK_N1;
651 u32 savePIPEB_DATA_M1;
652 u32 savePIPEB_DATA_N1;
653 u32 savePIPEB_LINK_M1;
654 u32 savePIPEB_LINK_N1;
655 u32 saveMCHBAR_RENDER_STANDBY;
656 u32 savePCH_PORT_HOTPLUG;
657};
658
659struct intel_gen6_power_mgmt {
660 struct work_struct work;
661 u32 pm_iir;
662
663
664 spinlock_t lock;
665
666
667
668 u8 cur_delay;
669 u8 min_delay;
670 u8 max_delay;
671 u8 hw_max;
672
673 struct delayed_work delayed_resume_work;
674
675
676
677
678
679 struct mutex hw_lock;
680};
681
682
683extern spinlock_t mchdev_lock;
684
685struct intel_ilk_power_mgmt {
686 u8 cur_delay;
687 u8 min_delay;
688 u8 max_delay;
689 u8 fmax;
690 u8 fstart;
691
692 u64 last_count1;
693 unsigned long last_time1;
694 unsigned long chipset_power;
695 u64 last_count2;
696 struct timespec last_time2;
697 unsigned long gfx_power;
698 u8 corr;
699
700 int c_m;
701 int r_t;
702
703 struct drm_i915_gem_object *pwrctx;
704 struct drm_i915_gem_object *renderctx;
705};
706
707struct i915_dri1_state {
708 unsigned allow_batchbuffer : 1;
709 u32 __iomem *gfx_hws_cpu_addr;
710
711 unsigned int cpp;
712 int back_offset;
713 int front_offset;
714 int current_page;
715 int page_flipping;
716
717 uint32_t counter;
718};
719
720struct intel_l3_parity {
721 u32 *remap_info;
722 struct work_struct error_work;
723};
724
725struct i915_gem_mm {
726
727 struct drm_mm stolen;
728
729 struct drm_mm gtt_space;
730
731
732 struct list_head bound_list;
733
734
735
736
737
738 struct list_head unbound_list;
739
740
741 unsigned long stolen_base;
742
743 int gtt_mtrr;
744
745
746 struct i915_hw_ppgtt *aliasing_ppgtt;
747
748 struct shrinker inactive_shrinker;
749 bool shrinker_no_lock_stealing;
750
751
752
753
754
755
756
757
758
759
760 struct list_head active_list;
761
762
763
764
765
766
767
768
769
770
771
772 struct list_head inactive_list;
773
774
775 struct list_head fence_list;
776
777
778
779
780
781
782
783
784 struct delayed_work retire_work;
785
786
787
788
789
790 bool interruptible;
791
792
793
794
795
796
797
798
799
800 int suspended;
801
802
803 uint32_t bit_6_swizzle_x;
804
805 uint32_t bit_6_swizzle_y;
806
807
808 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
809
810
811 size_t object_memory;
812 u32 object_count;
813};
814
815struct i915_gpu_error {
816
817#define DRM_I915_HANGCHECK_PERIOD 1500
818#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
819 struct timer_list hangcheck_timer;
820 int hangcheck_count;
821 uint32_t last_acthd[I915_NUM_RINGS];
822 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
823
824
825 spinlock_t lock;
826
827 struct drm_i915_error_state *first_error;
828 struct work_struct work;
829
830 unsigned long last_reset;
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850 atomic_t reset_counter;
851
852
853
854
855
856
857
858
859#define I915_RESET_IN_PROGRESS_FLAG 1
860#define I915_WEDGED 0xffffffff
861
862
863
864
865
866 wait_queue_head_t reset_queue;
867
868
869 unsigned int stop_rings;
870};
871
872enum modeset_restore {
873 MODESET_ON_LID_OPEN,
874 MODESET_DONE,
875 MODESET_SUSPENDED,
876};
877
878typedef struct drm_i915_private {
879 struct drm_device *dev;
880 struct kmem_cache *slab;
881
882 const struct intel_device_info *info;
883
884 int relative_constants_mode;
885
886 void __iomem *regs;
887
888 struct drm_i915_gt_funcs gt;
889
890
891 unsigned gt_fifo_count;
892
893 unsigned forcewake_count;
894
895 spinlock_t gt_lock;
896
897 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
898
899
900
901
902 struct mutex gmbus_mutex;
903
904
905
906
907 uint32_t gpio_mmio_base;
908
909 wait_queue_head_t gmbus_wait_queue;
910
911 struct pci_dev *bridge_dev;
912 struct intel_ring_buffer ring[I915_NUM_RINGS];
913 uint32_t last_seqno, next_seqno;
914
915 drm_dma_handle_t *status_page_dmah;
916 struct resource mch_res;
917
918 atomic_t irq_received;
919
920
921 spinlock_t irq_lock;
922
923
924 struct pm_qos_request pm_qos;
925
926
927 struct mutex dpio_lock;
928
929
930 u32 irq_mask;
931 u32 gt_irq_mask;
932
933 struct work_struct hotplug_work;
934 bool enable_hotplug_processing;
935 struct {
936 unsigned long hpd_last_jiffies;
937 int hpd_cnt;
938 enum {
939 HPD_ENABLED = 0,
940 HPD_DISABLED = 1,
941 HPD_MARK_DISABLED = 2
942 } hpd_mark;
943 } hpd_stats[HPD_NUM_PINS];
944 struct timer_list hotplug_reenable_timer;
945
946 int num_pch_pll;
947 int num_plane;
948
949 unsigned long cfb_size;
950 unsigned int cfb_fb;
951 enum plane cfb_plane;
952 int cfb_y;
953 struct intel_fbc_work *fbc_work;
954
955 struct intel_opregion opregion;
956
957
958 struct intel_overlay *overlay;
959 unsigned int sprite_scaling_enabled;
960
961
962 struct {
963 int level;
964 bool enabled;
965 struct backlight_device *device;
966 } backlight;
967
968
969 struct drm_display_mode *lfp_lvds_vbt_mode;
970 struct drm_display_mode *sdvo_lvds_vbt_mode;
971
972
973 unsigned int int_tv_support:1;
974 unsigned int lvds_dither:1;
975 unsigned int lvds_vbt:1;
976 unsigned int int_crt_support:1;
977 unsigned int lvds_use_ssc:1;
978 unsigned int display_clock_mode:1;
979 unsigned int fdi_rx_polarity_inverted:1;
980 int lvds_ssc_freq;
981 unsigned int bios_lvds_val;
982 struct {
983 int rate;
984 int lanes;
985 int preemphasis;
986 int vswing;
987
988 bool initialized;
989 bool support;
990 int bpp;
991 struct edp_power_seq pps;
992 } edp;
993 bool no_aux_handshake;
994
995 int crt_ddc_pin;
996 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES];
997 int fence_reg_start;
998 int num_fence_regs;
999
1000 unsigned int fsb_freq, mem_freq, is_ddr3;
1001
1002 struct workqueue_struct *wq;
1003
1004
1005 struct drm_i915_display_funcs display;
1006
1007
1008 enum intel_pch pch_type;
1009 unsigned short pch_id;
1010
1011 unsigned long quirks;
1012
1013 enum modeset_restore modeset_restore;
1014 struct mutex modeset_restore_lock;
1015
1016 struct i915_gtt gtt;
1017
1018 struct i915_gem_mm mm;
1019
1020
1021
1022 struct sdvo_device_mapping sdvo_mappings[2];
1023
1024 unsigned int lvds_border_bits;
1025
1026 u32 pch_pf_pos, pch_pf_size;
1027
1028 struct drm_crtc *plane_to_crtc_mapping[3];
1029 struct drm_crtc *pipe_to_crtc_mapping[3];
1030 wait_queue_head_t pending_flip_queue;
1031
1032 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
1033 struct intel_ddi_plls ddi_plls;
1034
1035
1036 bool render_reclock_avail;
1037 bool lvds_downclock_avail;
1038
1039 int lvds_downclock;
1040 u16 orig_clock;
1041 int child_dev_num;
1042 struct child_device_config *child_dev;
1043
1044 bool mchbar_need_disable;
1045
1046 struct intel_l3_parity l3_parity;
1047
1048
1049 struct intel_gen6_power_mgmt rps;
1050
1051
1052
1053 struct intel_ilk_power_mgmt ips;
1054
1055 enum no_fbc_reason no_fbc_reason;
1056
1057 struct drm_mm_node *compressed_fb;
1058 struct drm_mm_node *compressed_llb;
1059
1060 struct i915_gpu_error gpu_error;
1061
1062
1063 struct intel_fbdev *fbdev;
1064
1065
1066
1067
1068
1069 struct work_struct console_resume_work;
1070
1071 struct drm_property *broadcast_rgb_property;
1072 struct drm_property *force_audio_property;
1073
1074 bool hw_contexts_disabled;
1075 uint32_t hw_context_size;
1076
1077 u32 fdi_rx_config;
1078
1079 struct i915_suspend_saved_registers regfile;
1080
1081
1082
1083 struct i915_dri1_state dri1;
1084} drm_i915_private_t;
1085
1086
1087#define for_each_ring(ring__, dev_priv__, i__) \
1088 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1089 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1090
1091enum hdmi_force_audio {
1092 HDMI_AUDIO_OFF_DVI = -2,
1093 HDMI_AUDIO_OFF,
1094 HDMI_AUDIO_AUTO,
1095 HDMI_AUDIO_ON,
1096};
1097
1098#define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1099
1100struct drm_i915_gem_object_ops {
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114 int (*get_pages)(struct drm_i915_gem_object *);
1115 void (*put_pages)(struct drm_i915_gem_object *);
1116};
1117
1118struct drm_i915_gem_object {
1119 struct drm_gem_object base;
1120
1121 const struct drm_i915_gem_object_ops *ops;
1122
1123
1124 struct drm_mm_node *gtt_space;
1125
1126 struct drm_mm_node *stolen;
1127 struct list_head gtt_list;
1128
1129
1130 struct list_head ring_list;
1131 struct list_head mm_list;
1132
1133 struct list_head exec_list;
1134
1135
1136
1137
1138
1139
1140 unsigned int active:1;
1141
1142
1143
1144
1145
1146 unsigned int dirty:1;
1147
1148
1149
1150
1151
1152
1153 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1154
1155
1156
1157
1158 unsigned int madv:2;
1159
1160
1161
1162
1163 unsigned int tiling_mode:2;
1164
1165
1166
1167
1168
1169
1170
1171 unsigned int fence_dirty:1;
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182 unsigned int pin_count:4;
1183#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1184
1185
1186
1187
1188
1189 unsigned int map_and_fenceable:1;
1190
1191
1192
1193
1194
1195
1196 unsigned int fault_mappable:1;
1197 unsigned int pin_mappable:1;
1198
1199
1200
1201
1202 unsigned int pending_fenced_gpu_access:1;
1203 unsigned int fenced_gpu_access:1;
1204
1205 unsigned int cache_level:2;
1206
1207 unsigned int has_aliasing_ppgtt_mapping:1;
1208 unsigned int has_global_gtt_mapping:1;
1209 unsigned int has_dma_mapping:1;
1210
1211 struct sg_table *pages;
1212 int pages_pin_count;
1213
1214
1215 void *dma_buf_vmapping;
1216 int vmapping_count;
1217
1218
1219
1220
1221 struct hlist_node exec_node;
1222 unsigned long exec_handle;
1223 struct drm_i915_gem_exec_object2 *exec_entry;
1224
1225
1226
1227
1228
1229
1230 uint32_t gtt_offset;
1231
1232 struct intel_ring_buffer *ring;
1233
1234
1235 uint32_t last_read_seqno;
1236 uint32_t last_write_seqno;
1237
1238 uint32_t last_fenced_seqno;
1239
1240
1241 uint32_t stride;
1242
1243
1244 unsigned long *bit_17;
1245
1246
1247 uint32_t user_pin_count;
1248 struct drm_file *pin_filp;
1249
1250
1251 struct drm_i915_gem_phys_object *phys_obj;
1252};
1253#define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1254
1255#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267struct drm_i915_gem_request {
1268
1269 struct intel_ring_buffer *ring;
1270
1271
1272 uint32_t seqno;
1273
1274
1275 u32 tail;
1276
1277
1278 unsigned long emitted_jiffies;
1279
1280
1281 struct list_head list;
1282
1283 struct drm_i915_file_private *file_priv;
1284
1285 struct list_head client_list;
1286};
1287
1288struct drm_i915_file_private {
1289 struct {
1290 spinlock_t lock;
1291 struct list_head request_list;
1292 } mm;
1293 struct idr context_idr;
1294};
1295
1296#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1297
1298#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1299#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1300#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1301#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1302#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1303#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1304#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1305#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1306#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1307#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1308#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1309#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1310#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1311#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1312#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1313#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1314#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1315#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1316#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1317#define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1318 (dev)->pci_device == 0x0152 || \
1319 (dev)->pci_device == 0x015a)
1320#define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1321 (dev)->pci_device == 0x0106 || \
1322 (dev)->pci_device == 0x010A)
1323#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1324#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1325#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1326#define IS_ULT(dev) (IS_HASWELL(dev) && \
1327 ((dev)->pci_device & 0xFF00) == 0x0A00)
1328
1329
1330
1331
1332
1333
1334
1335#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1336#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1337#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1338#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1339#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1340#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1341
1342#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1343#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1344#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1345#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1346
1347#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1348#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1349
1350#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1351#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1352
1353
1354#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1355
1356
1357
1358
1359#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1360 IS_I915GM(dev)))
1361#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1362#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1363#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1364#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1365#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1366#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1367
1368#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1369
1370#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1371#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1372#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1373
1374#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1375
1376#define HAS_DDI(dev) (IS_HASWELL(dev))
1377#define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1378
1379#define INTEL_PCH_DEVICE_ID_MASK 0xff00
1380#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1381#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1382#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1383#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1384#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1385
1386#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1387#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1388#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1389#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1390#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1391#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1392
1393#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1394
1395#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1396
1397#define GT_FREQUENCY_MULTIPLIER 50
1398
1399#include "i915_trace.h"
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418#define INTEL_RC6_ENABLE (1<<0)
1419#define INTEL_RC6p_ENABLE (1<<1)
1420#define INTEL_RC6pp_ENABLE (1<<2)
1421
1422extern struct drm_ioctl_desc i915_ioctls[];
1423extern int i915_max_ioctl;
1424extern unsigned int i915_fbpercrtc __always_unused;
1425extern int i915_panel_ignore_lid __read_mostly;
1426extern unsigned int i915_powersave __read_mostly;
1427extern int i915_semaphores __read_mostly;
1428extern unsigned int i915_lvds_downclock __read_mostly;
1429extern int i915_lvds_channel_mode __read_mostly;
1430extern int i915_panel_use_ssc __read_mostly;
1431extern int i915_vbt_sdvo_panel_type __read_mostly;
1432extern int i915_enable_rc6 __read_mostly;
1433extern int i915_enable_fbc __read_mostly;
1434extern bool i915_enable_hangcheck __read_mostly;
1435extern int i915_enable_ppgtt __read_mostly;
1436extern unsigned int i915_preliminary_hw_support __read_mostly;
1437extern int i915_disable_power_well __read_mostly;
1438
1439extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1440extern int i915_resume(struct drm_device *dev);
1441extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1442extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1443
1444
1445void i915_update_dri1_breadcrumb(struct drm_device *dev);
1446extern void i915_kernel_lost_context(struct drm_device * dev);
1447extern int i915_driver_load(struct drm_device *, unsigned long flags);
1448extern int i915_driver_unload(struct drm_device *);
1449extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1450extern void i915_driver_lastclose(struct drm_device * dev);
1451extern void i915_driver_preclose(struct drm_device *dev,
1452 struct drm_file *file_priv);
1453extern void i915_driver_postclose(struct drm_device *dev,
1454 struct drm_file *file_priv);
1455extern int i915_driver_device_is_agp(struct drm_device * dev);
1456#ifdef CONFIG_COMPAT
1457extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1458 unsigned long arg);
1459#endif
1460extern int i915_emit_box(struct drm_device *dev,
1461 struct drm_clip_rect *box,
1462 int DR1, int DR4);
1463extern int intel_gpu_reset(struct drm_device *dev);
1464extern int i915_reset(struct drm_device *dev);
1465extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1466extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1467extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1468extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1469
1470extern void intel_console_resume(struct work_struct *work);
1471
1472
1473void i915_hangcheck_elapsed(unsigned long data);
1474void i915_handle_error(struct drm_device *dev, bool wedged);
1475
1476extern void intel_irq_init(struct drm_device *dev);
1477extern void intel_hpd_init(struct drm_device *dev);
1478extern void intel_gt_init(struct drm_device *dev);
1479extern void intel_gt_reset(struct drm_device *dev);
1480
1481void i915_error_state_free(struct kref *error_ref);
1482
1483void
1484i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1485
1486void
1487i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1488
1489void intel_enable_asle(struct drm_device *dev);
1490
1491#ifdef CONFIG_DEBUG_FS
1492extern void i915_destroy_error_state(struct drm_device *dev);
1493#else
1494#define i915_destroy_error_state(x)
1495#endif
1496
1497
1498
1499int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1500 struct drm_file *file_priv);
1501int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1502 struct drm_file *file_priv);
1503int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1504 struct drm_file *file_priv);
1505int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1506 struct drm_file *file_priv);
1507int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1508 struct drm_file *file_priv);
1509int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1510 struct drm_file *file_priv);
1511int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1512 struct drm_file *file_priv);
1513int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1514 struct drm_file *file_priv);
1515int i915_gem_execbuffer(struct drm_device *dev, void *data,
1516 struct drm_file *file_priv);
1517int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1518 struct drm_file *file_priv);
1519int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1520 struct drm_file *file_priv);
1521int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1522 struct drm_file *file_priv);
1523int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1524 struct drm_file *file_priv);
1525int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1526 struct drm_file *file);
1527int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1528 struct drm_file *file);
1529int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1530 struct drm_file *file_priv);
1531int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1532 struct drm_file *file_priv);
1533int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1534 struct drm_file *file_priv);
1535int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1536 struct drm_file *file_priv);
1537int i915_gem_set_tiling(struct drm_device *dev, void *data,
1538 struct drm_file *file_priv);
1539int i915_gem_get_tiling(struct drm_device *dev, void *data,
1540 struct drm_file *file_priv);
1541int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1542 struct drm_file *file_priv);
1543int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1544 struct drm_file *file_priv);
1545void i915_gem_load(struct drm_device *dev);
1546void *i915_gem_object_alloc(struct drm_device *dev);
1547void i915_gem_object_free(struct drm_i915_gem_object *obj);
1548int i915_gem_init_object(struct drm_gem_object *obj);
1549void i915_gem_object_init(struct drm_i915_gem_object *obj,
1550 const struct drm_i915_gem_object_ops *ops);
1551struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1552 size_t size);
1553void i915_gem_free_object(struct drm_gem_object *obj);
1554
1555int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1556 uint32_t alignment,
1557 bool map_and_fenceable,
1558 bool nonblocking);
1559void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1560int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1561int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1562void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1563void i915_gem_lastclose(struct drm_device *dev);
1564
1565int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1566static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1567{
1568 struct sg_page_iter sg_iter;
1569
1570 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1571 return sg_page_iter_page(&sg_iter);
1572
1573 return NULL;
1574}
1575static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1576{
1577 BUG_ON(obj->pages == NULL);
1578 obj->pages_pin_count++;
1579}
1580static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1581{
1582 BUG_ON(obj->pages_pin_count == 0);
1583 obj->pages_pin_count--;
1584}
1585
1586int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1587int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1588 struct intel_ring_buffer *to);
1589void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1590 struct intel_ring_buffer *ring);
1591
1592int i915_gem_dumb_create(struct drm_file *file_priv,
1593 struct drm_device *dev,
1594 struct drm_mode_create_dumb *args);
1595int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1596 uint32_t handle, uint64_t *offset);
1597int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1598 uint32_t handle);
1599
1600
1601
1602static inline bool
1603i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1604{
1605 return (int32_t)(seq1 - seq2) >= 0;
1606}
1607
1608int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1609int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1610int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1611int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1612
1613static inline bool
1614i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1615{
1616 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1617 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1618 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1619 return true;
1620 } else
1621 return false;
1622}
1623
1624static inline void
1625i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1626{
1627 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1628 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1629 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1630 }
1631}
1632
1633void i915_gem_retire_requests(struct drm_device *dev);
1634void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1635int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
1636 bool interruptible);
1637static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1638{
1639 return unlikely(atomic_read(&error->reset_counter)
1640 & I915_RESET_IN_PROGRESS_FLAG);
1641}
1642
1643static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1644{
1645 return atomic_read(&error->reset_counter) == I915_WEDGED;
1646}
1647
1648void i915_gem_reset(struct drm_device *dev);
1649void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1650int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1651 uint32_t read_domains,
1652 uint32_t write_domain);
1653int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1654int __must_check i915_gem_init(struct drm_device *dev);
1655int __must_check i915_gem_init_hw(struct drm_device *dev);
1656void i915_gem_l3_remap(struct drm_device *dev);
1657void i915_gem_init_swizzling(struct drm_device *dev);
1658void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1659int __must_check i915_gpu_idle(struct drm_device *dev);
1660int __must_check i915_gem_idle(struct drm_device *dev);
1661int i915_add_request(struct intel_ring_buffer *ring,
1662 struct drm_file *file,
1663 u32 *seqno);
1664int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1665 uint32_t seqno);
1666int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1667int __must_check
1668i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1669 bool write);
1670int __must_check
1671i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1672int __must_check
1673i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1674 u32 alignment,
1675 struct intel_ring_buffer *pipelined);
1676int i915_gem_attach_phys_object(struct drm_device *dev,
1677 struct drm_i915_gem_object *obj,
1678 int id,
1679 int align);
1680void i915_gem_detach_phys_object(struct drm_device *dev,
1681 struct drm_i915_gem_object *obj);
1682void i915_gem_free_all_phys_object(struct drm_device *dev);
1683void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1684
1685uint32_t
1686i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1687uint32_t
1688i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1689 int tiling_mode, bool fenced);
1690
1691int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1692 enum i915_cache_level cache_level);
1693
1694struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1695 struct dma_buf *dma_buf);
1696
1697struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1698 struct drm_gem_object *gem_obj, int flags);
1699
1700void i915_gem_restore_fences(struct drm_device *dev);
1701
1702
1703void i915_gem_context_init(struct drm_device *dev);
1704void i915_gem_context_fini(struct drm_device *dev);
1705void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1706int i915_switch_context(struct intel_ring_buffer *ring,
1707 struct drm_file *file, int to_id);
1708int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1709 struct drm_file *file);
1710int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1711 struct drm_file *file);
1712
1713
1714void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1715void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1716 struct drm_i915_gem_object *obj,
1717 enum i915_cache_level cache_level);
1718void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1719 struct drm_i915_gem_object *obj);
1720
1721void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1722int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1723void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1724 enum i915_cache_level cache_level);
1725void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1726void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1727void i915_gem_init_global_gtt(struct drm_device *dev);
1728void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1729 unsigned long mappable_end, unsigned long end);
1730int i915_gem_gtt_init(struct drm_device *dev);
1731static inline void i915_gem_chipset_flush(struct drm_device *dev)
1732{
1733 if (INTEL_INFO(dev)->gen < 6)
1734 intel_gtt_chipset_flush();
1735}
1736
1737
1738
1739int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1740 unsigned alignment,
1741 unsigned cache_level,
1742 bool mappable,
1743 bool nonblock);
1744int i915_gem_evict_everything(struct drm_device *dev);
1745
1746
1747int i915_gem_init_stolen(struct drm_device *dev);
1748int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1749void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1750void i915_gem_cleanup_stolen(struct drm_device *dev);
1751struct drm_i915_gem_object *
1752i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1753struct drm_i915_gem_object *
1754i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1755 u32 stolen_offset,
1756 u32 gtt_offset,
1757 u32 size);
1758void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1759
1760
1761inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1762{
1763 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1764
1765 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1766 obj->tiling_mode != I915_TILING_NONE;
1767}
1768
1769void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1770void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1771void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1772
1773
1774void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1775 const char *where, uint32_t mark);
1776#if WATCH_LISTS
1777int i915_verify_lists(struct drm_device *dev);
1778#else
1779#define i915_verify_lists(dev) 0
1780#endif
1781void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1782 int handle);
1783void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1784 const char *where, uint32_t mark);
1785
1786
1787int i915_debugfs_init(struct drm_minor *minor);
1788void i915_debugfs_cleanup(struct drm_minor *minor);
1789
1790
1791extern int i915_save_state(struct drm_device *dev);
1792extern int i915_restore_state(struct drm_device *dev);
1793
1794
1795void i915_save_display_reg(struct drm_device *dev);
1796void i915_restore_display_reg(struct drm_device *dev);
1797
1798
1799void i915_setup_sysfs(struct drm_device *dev_priv);
1800void i915_teardown_sysfs(struct drm_device *dev_priv);
1801
1802
1803extern int intel_setup_gmbus(struct drm_device *dev);
1804extern void intel_teardown_gmbus(struct drm_device *dev);
1805extern inline bool intel_gmbus_is_port_valid(unsigned port)
1806{
1807 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1808}
1809
1810extern struct i2c_adapter *intel_gmbus_get_adapter(
1811 struct drm_i915_private *dev_priv, unsigned port);
1812extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1813extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1814extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1815{
1816 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1817}
1818extern void intel_i2c_reset(struct drm_device *dev);
1819
1820
1821extern int intel_opregion_setup(struct drm_device *dev);
1822#ifdef CONFIG_ACPI
1823extern void intel_opregion_init(struct drm_device *dev);
1824extern void intel_opregion_fini(struct drm_device *dev);
1825extern void intel_opregion_asle_intr(struct drm_device *dev);
1826extern void intel_opregion_gse_intr(struct drm_device *dev);
1827extern void intel_opregion_enable_asle(struct drm_device *dev);
1828#else
1829static inline void intel_opregion_init(struct drm_device *dev) { return; }
1830static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1831static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1832static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1833static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1834#endif
1835
1836
1837#ifdef CONFIG_ACPI
1838extern void intel_register_dsm_handler(void);
1839extern void intel_unregister_dsm_handler(void);
1840#else
1841static inline void intel_register_dsm_handler(void) { return; }
1842static inline void intel_unregister_dsm_handler(void) { return; }
1843#endif
1844
1845
1846extern void intel_modeset_init_hw(struct drm_device *dev);
1847extern void intel_modeset_init(struct drm_device *dev);
1848extern void intel_modeset_gem_init(struct drm_device *dev);
1849extern void intel_modeset_cleanup(struct drm_device *dev);
1850extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1851extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1852 bool force_restore);
1853extern void i915_redisable_vga(struct drm_device *dev);
1854extern bool intel_fbc_enabled(struct drm_device *dev);
1855extern void intel_disable_fbc(struct drm_device *dev);
1856extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1857extern void intel_init_pch_refclk(struct drm_device *dev);
1858extern void gen6_set_rps(struct drm_device *dev, u8 val);
1859extern void intel_detect_pch(struct drm_device *dev);
1860extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1861extern int intel_enable_rc6(const struct drm_device *dev);
1862
1863extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1864int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1865 struct drm_file *file);
1866
1867
1868#ifdef CONFIG_DEBUG_FS
1869extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1870extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1871
1872extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1873extern void intel_display_print_error_state(struct seq_file *m,
1874 struct drm_device *dev,
1875 struct intel_display_error_state *error);
1876#endif
1877
1878
1879
1880
1881
1882void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1883void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1884int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1885
1886int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1887int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1888int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
1889int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
1890
1891#define __i915_read(x, y) \
1892 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1893
1894__i915_read(8, b)
1895__i915_read(16, w)
1896__i915_read(32, l)
1897__i915_read(64, q)
1898#undef __i915_read
1899
1900#define __i915_write(x, y) \
1901 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1902
1903__i915_write(8, b)
1904__i915_write(16, w)
1905__i915_write(32, l)
1906__i915_write(64, q)
1907#undef __i915_write
1908
1909#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1910#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1911
1912#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1913#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1914#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1915#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1916
1917#define I915_READ(reg) i915_read32(dev_priv, (reg))
1918#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1919#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1920#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1921
1922#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1923#define I915_READ64(reg) i915_read64(dev_priv, (reg))
1924
1925#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1926#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1927
1928
1929#define INTEL_BROADCAST_RGB_AUTO 0
1930#define INTEL_BROADCAST_RGB_FULL 1
1931#define INTEL_BROADCAST_RGB_LIMITED 2
1932
1933static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
1934{
1935 if (HAS_PCH_SPLIT(dev))
1936 return CPU_VGACNTRL;
1937 else if (IS_VALLEYVIEW(dev))
1938 return VLV_VGACNTRL;
1939 else
1940 return VGACNTRL;
1941}
1942
1943static inline void __user *to_user_ptr(u64 address)
1944{
1945 return (void __user *)(uintptr_t)address;
1946}
1947
1948static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
1949{
1950 unsigned long j = msecs_to_jiffies(m);
1951
1952 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
1953}
1954
1955static inline unsigned long
1956timespec_to_jiffies_timeout(const struct timespec *value)
1957{
1958 unsigned long j = timespec_to_jiffies(value);
1959
1960 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
1961}
1962
1963#endif
1964