1#ifndef _INTEL_RINGBUFFER_H_
2#define _INTEL_RINGBUFFER_H_
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13#define I915_RING_FREE_SPACE 64
14
15struct intel_hw_status_page {
16 u32 *page_addr;
17 unsigned int gfx_addr;
18 struct drm_i915_gem_object *obj;
19};
20
21#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
22#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
23
24#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
25#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
26
27#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
28#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
29
30#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
31#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
32
33#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
34#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
35
36#define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
37#define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
38#define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
39
40struct intel_ring_buffer {
41 const char *name;
42 enum intel_ring_id {
43 RCS = 0x0,
44 VCS,
45 BCS,
46 } id;
47#define I915_NUM_RINGS 3
48 u32 mmio_base;
49 void __iomem *virtual_start;
50 struct drm_device *dev;
51 struct drm_i915_gem_object *obj;
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53 u32 head;
54 u32 tail;
55 int space;
56 int size;
57 int effective_size;
58 struct intel_hw_status_page status_page;
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68 u32 last_retired_head;
69
70 u32 irq_refcount;
71 u32 irq_enable_mask;
72 u32 trace_irq_seqno;
73 u32 sync_seqno[I915_NUM_RINGS-1];
74 bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
75 void (*irq_put)(struct intel_ring_buffer *ring);
76
77 int (*init)(struct intel_ring_buffer *ring);
78
79 void (*write_tail)(struct intel_ring_buffer *ring,
80 u32 value);
81 int __must_check (*flush)(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
83 u32 flush_domains);
84 int (*add_request)(struct intel_ring_buffer *ring);
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91 u32 (*get_seqno)(struct intel_ring_buffer *ring,
92 bool lazy_coherency);
93 void (*set_seqno)(struct intel_ring_buffer *ring,
94 u32 seqno);
95 int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
96 u32 offset, u32 length,
97 unsigned flags);
98#define I915_DISPATCH_SECURE 0x1
99#define I915_DISPATCH_PINNED 0x2
100 void (*cleanup)(struct intel_ring_buffer *ring);
101 int (*sync_to)(struct intel_ring_buffer *ring,
102 struct intel_ring_buffer *to,
103 u32 seqno);
104
105 u32 semaphore_register[3];
106 u32 signal_mbox[2];
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117 struct list_head active_list;
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123 struct list_head request_list;
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128 u32 outstanding_lazy_request;
129 bool gpu_caches_dirty;
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131 wait_queue_head_t irq_queue;
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136 bool itlb_before_ctx_switch;
137 struct i915_hw_context *default_context;
138 struct drm_i915_gem_object *last_context_obj;
139
140 void *private;
141};
142
143static inline bool
144intel_ring_initialized(struct intel_ring_buffer *ring)
145{
146 return ring->obj != NULL;
147}
148
149static inline unsigned
150intel_ring_flag(struct intel_ring_buffer *ring)
151{
152 return 1 << ring->id;
153}
154
155static inline u32
156intel_ring_sync_index(struct intel_ring_buffer *ring,
157 struct intel_ring_buffer *other)
158{
159 int idx;
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167 idx = (other - ring) - 1;
168 if (idx < 0)
169 idx += I915_NUM_RINGS;
170
171 return idx;
172}
173
174static inline u32
175intel_read_status_page(struct intel_ring_buffer *ring,
176 int reg)
177{
178
179 barrier();
180 return ring->status_page.page_addr[reg];
181}
182
183static inline void
184intel_write_status_page(struct intel_ring_buffer *ring,
185 int reg, u32 value)
186{
187 ring->status_page.page_addr[reg] = value;
188}
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205#define I915_GEM_HWS_INDEX 0x20
206#define I915_GEM_HWS_SCRATCH_INDEX 0x30
207#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
208
209void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
210
211int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
212static inline void intel_ring_emit(struct intel_ring_buffer *ring,
213 u32 data)
214{
215 iowrite32(data, ring->virtual_start + ring->tail);
216 ring->tail += 4;
217}
218void intel_ring_advance(struct intel_ring_buffer *ring);
219int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
220void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno);
221int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
222int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
223
224int intel_init_render_ring_buffer(struct drm_device *dev);
225int intel_init_bsd_ring_buffer(struct drm_device *dev);
226int intel_init_blt_ring_buffer(struct drm_device *dev);
227
228u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
229void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
230
231static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
232{
233 return ring->tail;
234}
235
236static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
237{
238 BUG_ON(ring->outstanding_lazy_request == 0);
239 return ring->outstanding_lazy_request;
240}
241
242static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
243{
244 if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
245 ring->trace_irq_seqno = seqno;
246}
247
248
249int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
250
251#endif
252