LXR linux/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24
  25#include <subdev/mc.h>
  26
  27struct nv04_mc_priv {
  28        struct nouveau_mc base;
  29};
  30
  31const struct nouveau_mc_intr
  32nv04_mc_intr[] = {
  33        { 0x00000001, NVDEV_ENGINE_MPEG },      /* NV17- MPEG/ME */
  34        { 0x00000100, NVDEV_ENGINE_FIFO },
  35        { 0x00001000, NVDEV_ENGINE_GR },
  36        { 0x00020000, NVDEV_ENGINE_VP },        /* NV40- */
  37        { 0x00100000, NVDEV_SUBDEV_TIMER },
  38        { 0x01000000, NVDEV_ENGINE_DISP },      /* NV04- PCRTC0 */
  39        { 0x02000000, NVDEV_ENGINE_DISP },      /* NV11- PCRTC1 */
  40        { 0x10000000, NVDEV_SUBDEV_BUS },
  41        { 0x80000000, NVDEV_ENGINE_SW },
  42        {}
  43};
  44
  45static int
  46nv04_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
  47             struct nouveau_oclass *oclass, void *data, u32 size,
  48             struct nouveau_object **pobject)
  49{
  50        struct nv04_mc_priv *priv;
  51        int ret;
  52
  53        ret = nouveau_mc_create(parent, engine, oclass, &priv);
  54        *pobject = nv_object(priv);
  55        if (ret)
  56                return ret;
  57
  58        priv->base.intr_map = nv04_mc_intr;
  59        return 0;
  60}
  61
  62int
  63nv04_mc_init(struct nouveau_object *object)
  64{
  65        struct nv04_mc_priv *priv = (void *)object;
  66
  67        nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */
  68        nv_wr32(priv, 0x001850, 0x00000001); /* disable rom access */
  69
  70        return nouveau_mc_init(&priv->base);
  71}
  72
  73struct nouveau_oclass
  74nv04_mc_oclass = {
  75        .handle = NV_SUBDEV(MC, 0x04),
  76        .ofuncs = &(struct nouveau_ofuncs) {
  77                .ctor = nv04_mc_ctor,
  78                .dtor = _nouveau_mc_dtor,
  79                .init = nv04_mc_init,
  80                .fini = _nouveau_mc_fini,
  81        },
  82};
  83