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28#include <drm/drmP.h>
29#include "radeon_reg.h"
30#include "radeon.h"
31#include "atom.h"
32
33#include <linux/vga_switcheroo.h>
34#include <linux/slab.h>
35#include <linux/acpi.h>
36
37
38
39
40
41
42
43
44
45
46static bool igp_read_bios_from_vram(struct radeon_device *rdev)
47{
48 uint8_t __iomem *bios;
49 resource_size_t vram_base;
50 resource_size_t size = 256 * 1024;
51
52 if (!(rdev->flags & RADEON_IS_IGP))
53 if (!radeon_card_posted(rdev))
54 return false;
55
56 rdev->bios = NULL;
57 vram_base = pci_resource_start(rdev->pdev, 0);
58 bios = ioremap(vram_base, size);
59 if (!bios) {
60 return false;
61 }
62
63 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
64 iounmap(bios);
65 return false;
66 }
67 rdev->bios = kmalloc(size, GFP_KERNEL);
68 if (rdev->bios == NULL) {
69 iounmap(bios);
70 return false;
71 }
72 memcpy_fromio(rdev->bios, bios, size);
73 iounmap(bios);
74 return true;
75}
76
77static bool radeon_read_bios(struct radeon_device *rdev)
78{
79 uint8_t __iomem *bios;
80 size_t size;
81
82 rdev->bios = NULL;
83
84 bios = pci_map_rom(rdev->pdev, &size);
85 if (!bios) {
86 return false;
87 }
88
89 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
90 pci_unmap_rom(rdev->pdev, bios);
91 return false;
92 }
93 rdev->bios = kmemdup(bios, size, GFP_KERNEL);
94 if (rdev->bios == NULL) {
95 pci_unmap_rom(rdev->pdev, bios);
96 return false;
97 }
98 pci_unmap_rom(rdev->pdev, bios);
99 return true;
100}
101
102static bool radeon_read_platform_bios(struct radeon_device *rdev)
103{
104 uint8_t __iomem *bios;
105 size_t size;
106
107 rdev->bios = NULL;
108
109 bios = pci_platform_rom(rdev->pdev, &size);
110 if (!bios) {
111 return false;
112 }
113
114 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
115 return false;
116 }
117 rdev->bios = kmemdup(bios, size, GFP_KERNEL);
118 if (rdev->bios == NULL) {
119 return false;
120 }
121
122 return true;
123}
124
125#ifdef CONFIG_ACPI
126
127
128
129
130#define ATRM_BIOS_PAGE 4096
131
132
133
134
135
136
137
138
139
140
141
142
143static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
144 int offset, int len)
145{
146 acpi_status status;
147 union acpi_object atrm_arg_elements[2], *obj;
148 struct acpi_object_list atrm_arg;
149 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
150
151 atrm_arg.count = 2;
152 atrm_arg.pointer = &atrm_arg_elements[0];
153
154 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
155 atrm_arg_elements[0].integer.value = offset;
156
157 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
158 atrm_arg_elements[1].integer.value = len;
159
160 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
161 if (ACPI_FAILURE(status)) {
162 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
163 return -ENODEV;
164 }
165
166 obj = (union acpi_object *)buffer.pointer;
167 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
168 len = obj->buffer.length;
169 kfree(buffer.pointer);
170 return len;
171}
172
173static bool radeon_atrm_get_bios(struct radeon_device *rdev)
174{
175 int ret;
176 int size = 256 * 1024;
177 int i;
178 struct pci_dev *pdev = NULL;
179 acpi_handle dhandle, atrm_handle;
180 acpi_status status;
181 bool found = false;
182
183
184 if (rdev->flags & RADEON_IS_IGP)
185 return false;
186
187 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
188 dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
189 if (!dhandle)
190 continue;
191
192 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
193 if (!ACPI_FAILURE(status)) {
194 found = true;
195 break;
196 }
197 }
198
199 if (!found)
200 return false;
201
202 rdev->bios = kmalloc(size, GFP_KERNEL);
203 if (!rdev->bios) {
204 DRM_ERROR("Unable to allocate bios\n");
205 return false;
206 }
207
208 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
209 ret = radeon_atrm_call(atrm_handle,
210 rdev->bios,
211 (i * ATRM_BIOS_PAGE),
212 ATRM_BIOS_PAGE);
213 if (ret < ATRM_BIOS_PAGE)
214 break;
215 }
216
217 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
218 kfree(rdev->bios);
219 return false;
220 }
221 return true;
222}
223#else
224static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
225{
226 return false;
227}
228#endif
229
230static bool ni_read_disabled_bios(struct radeon_device *rdev)
231{
232 u32 bus_cntl;
233 u32 d1vga_control;
234 u32 d2vga_control;
235 u32 vga_render_control;
236 u32 rom_cntl;
237 bool r;
238
239 bus_cntl = RREG32(R600_BUS_CNTL);
240 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
241 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
242 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
243 rom_cntl = RREG32(R600_ROM_CNTL);
244
245
246 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
247 if (!ASIC_IS_NODCE(rdev)) {
248
249 WREG32(AVIVO_D1VGA_CONTROL,
250 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
251 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
252 WREG32(AVIVO_D2VGA_CONTROL,
253 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
254 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
255 WREG32(AVIVO_VGA_RENDER_CONTROL,
256 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
257 }
258 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
259
260 r = radeon_read_bios(rdev);
261
262
263 WREG32(R600_BUS_CNTL, bus_cntl);
264 if (!ASIC_IS_NODCE(rdev)) {
265 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
266 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
267 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
268 }
269 WREG32(R600_ROM_CNTL, rom_cntl);
270 return r;
271}
272
273static bool r700_read_disabled_bios(struct radeon_device *rdev)
274{
275 uint32_t viph_control;
276 uint32_t bus_cntl;
277 uint32_t d1vga_control;
278 uint32_t d2vga_control;
279 uint32_t vga_render_control;
280 uint32_t rom_cntl;
281 uint32_t cg_spll_func_cntl = 0;
282 uint32_t cg_spll_status;
283 bool r;
284
285 viph_control = RREG32(RADEON_VIPH_CONTROL);
286 bus_cntl = RREG32(R600_BUS_CNTL);
287 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
288 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
289 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
290 rom_cntl = RREG32(R600_ROM_CNTL);
291
292
293 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
294
295 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
296
297 WREG32(AVIVO_D1VGA_CONTROL,
298 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
299 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
300 WREG32(AVIVO_D2VGA_CONTROL,
301 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
302 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
303 WREG32(AVIVO_VGA_RENDER_CONTROL,
304 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
305
306 if (rdev->family == CHIP_RV730) {
307 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
308
309
310 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
311 R600_SPLL_BYPASS_EN));
312
313
314 cg_spll_status = 0;
315 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
316 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
317
318 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
319 } else
320 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
321
322 r = radeon_read_bios(rdev);
323
324
325 if (rdev->family == CHIP_RV730) {
326 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
327
328
329 cg_spll_status = 0;
330 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
331 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
332 }
333 WREG32(RADEON_VIPH_CONTROL, viph_control);
334 WREG32(R600_BUS_CNTL, bus_cntl);
335 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
336 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
337 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
338 WREG32(R600_ROM_CNTL, rom_cntl);
339 return r;
340}
341
342static bool r600_read_disabled_bios(struct radeon_device *rdev)
343{
344 uint32_t viph_control;
345 uint32_t bus_cntl;
346 uint32_t d1vga_control;
347 uint32_t d2vga_control;
348 uint32_t vga_render_control;
349 uint32_t rom_cntl;
350 uint32_t general_pwrmgt;
351 uint32_t low_vid_lower_gpio_cntl;
352 uint32_t medium_vid_lower_gpio_cntl;
353 uint32_t high_vid_lower_gpio_cntl;
354 uint32_t ctxsw_vid_lower_gpio_cntl;
355 uint32_t lower_gpio_enable;
356 bool r;
357
358 viph_control = RREG32(RADEON_VIPH_CONTROL);
359 bus_cntl = RREG32(R600_BUS_CNTL);
360 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
361 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
362 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
363 rom_cntl = RREG32(R600_ROM_CNTL);
364 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
365 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
366 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
367 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
368 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
369 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
370
371
372 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
373
374 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
375
376 WREG32(AVIVO_D1VGA_CONTROL,
377 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
378 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
379 WREG32(AVIVO_D2VGA_CONTROL,
380 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
381 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
382 WREG32(AVIVO_VGA_RENDER_CONTROL,
383 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
384
385 WREG32(R600_ROM_CNTL,
386 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
387 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
388 R600_SCK_OVERWRITE));
389
390 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
391 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
392 (low_vid_lower_gpio_cntl & ~0x400));
393 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
394 (medium_vid_lower_gpio_cntl & ~0x400));
395 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
396 (high_vid_lower_gpio_cntl & ~0x400));
397 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
398 (ctxsw_vid_lower_gpio_cntl & ~0x400));
399 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
400
401 r = radeon_read_bios(rdev);
402
403
404 WREG32(RADEON_VIPH_CONTROL, viph_control);
405 WREG32(R600_BUS_CNTL, bus_cntl);
406 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
407 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
408 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
409 WREG32(R600_ROM_CNTL, rom_cntl);
410 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
411 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
412 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
413 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
414 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
415 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
416 return r;
417}
418
419static bool avivo_read_disabled_bios(struct radeon_device *rdev)
420{
421 uint32_t seprom_cntl1;
422 uint32_t viph_control;
423 uint32_t bus_cntl;
424 uint32_t d1vga_control;
425 uint32_t d2vga_control;
426 uint32_t vga_render_control;
427 uint32_t gpiopad_a;
428 uint32_t gpiopad_en;
429 uint32_t gpiopad_mask;
430 bool r;
431
432 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
433 viph_control = RREG32(RADEON_VIPH_CONTROL);
434 bus_cntl = RREG32(RV370_BUS_CNTL);
435 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
436 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
437 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
438 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
439 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
440 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
441
442 WREG32(RADEON_SEPROM_CNTL1,
443 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
444 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
445 WREG32(RADEON_GPIOPAD_A, 0);
446 WREG32(RADEON_GPIOPAD_EN, 0);
447 WREG32(RADEON_GPIOPAD_MASK, 0);
448
449
450 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
451
452
453 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
454
455
456 WREG32(AVIVO_D1VGA_CONTROL,
457 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
458 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
459 WREG32(AVIVO_D2VGA_CONTROL,
460 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
461 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
462 WREG32(AVIVO_VGA_RENDER_CONTROL,
463 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
464
465 r = radeon_read_bios(rdev);
466
467
468 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
469 WREG32(RADEON_VIPH_CONTROL, viph_control);
470 WREG32(RV370_BUS_CNTL, bus_cntl);
471 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
472 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
473 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
474 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
475 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
476 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
477 return r;
478}
479
480static bool legacy_read_disabled_bios(struct radeon_device *rdev)
481{
482 uint32_t seprom_cntl1;
483 uint32_t viph_control;
484 uint32_t bus_cntl;
485 uint32_t crtc_gen_cntl;
486 uint32_t crtc2_gen_cntl;
487 uint32_t crtc_ext_cntl;
488 uint32_t fp2_gen_cntl;
489 bool r;
490
491 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
492 viph_control = RREG32(RADEON_VIPH_CONTROL);
493 if (rdev->flags & RADEON_IS_PCIE)
494 bus_cntl = RREG32(RV370_BUS_CNTL);
495 else
496 bus_cntl = RREG32(RADEON_BUS_CNTL);
497 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
498 crtc2_gen_cntl = 0;
499 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
500 fp2_gen_cntl = 0;
501
502 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
503 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
504 }
505
506 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
507 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
508 }
509
510 WREG32(RADEON_SEPROM_CNTL1,
511 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
512 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
513
514
515 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
516
517
518 if (rdev->flags & RADEON_IS_PCIE)
519 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
520 else
521 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
522
523
524 WREG32(RADEON_CRTC_GEN_CNTL,
525 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
526 (RADEON_CRTC_DISP_REQ_EN_B |
527 RADEON_CRTC_EXT_DISP_EN)));
528 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
529 WREG32(RADEON_CRTC2_GEN_CNTL,
530 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
531 RADEON_CRTC2_DISP_REQ_EN_B));
532 }
533
534 WREG32(RADEON_CRTC_EXT_CNTL,
535 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
536 (RADEON_CRTC_SYNC_TRISTAT |
537 RADEON_CRTC_DISPLAY_DIS)));
538
539 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
540 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
541 }
542
543 r = radeon_read_bios(rdev);
544
545
546 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
547 WREG32(RADEON_VIPH_CONTROL, viph_control);
548 if (rdev->flags & RADEON_IS_PCIE)
549 WREG32(RV370_BUS_CNTL, bus_cntl);
550 else
551 WREG32(RADEON_BUS_CNTL, bus_cntl);
552 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
553 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
554 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
555 }
556 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
557 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
558 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
559 }
560 return r;
561}
562
563static bool radeon_read_disabled_bios(struct radeon_device *rdev)
564{
565 if (rdev->flags & RADEON_IS_IGP)
566 return igp_read_bios_from_vram(rdev);
567 else if (rdev->family >= CHIP_BARTS)
568 return ni_read_disabled_bios(rdev);
569 else if (rdev->family >= CHIP_RV770)
570 return r700_read_disabled_bios(rdev);
571 else if (rdev->family >= CHIP_R600)
572 return r600_read_disabled_bios(rdev);
573 else if (rdev->family >= CHIP_RS600)
574 return avivo_read_disabled_bios(rdev);
575 else
576 return legacy_read_disabled_bios(rdev);
577}
578
579#ifdef CONFIG_ACPI
580static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
581{
582 bool ret = false;
583 struct acpi_table_header *hdr;
584 acpi_size tbl_size;
585 UEFI_ACPI_VFCT *vfct;
586 GOP_VBIOS_CONTENT *vbios;
587 VFCT_IMAGE_HEADER *vhdr;
588
589 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
590 return false;
591 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
592 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
593 goto out_unmap;
594 }
595
596 vfct = (UEFI_ACPI_VFCT *)hdr;
597 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
598 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
599 goto out_unmap;
600 }
601
602 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
603 vhdr = &vbios->VbiosHeader;
604 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
605 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
606 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
607
608 if (vhdr->PCIBus != rdev->pdev->bus->number ||
609 vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
610 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) ||
611 vhdr->VendorID != rdev->pdev->vendor ||
612 vhdr->DeviceID != rdev->pdev->device) {
613 DRM_INFO("ACPI VFCT table is not for this card\n");
614 goto out_unmap;
615 };
616
617 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
618 DRM_ERROR("ACPI VFCT image truncated\n");
619 goto out_unmap;
620 }
621
622 rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
623 ret = !!rdev->bios;
624
625out_unmap:
626 return ret;
627}
628#else
629static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
630{
631 return false;
632}
633#endif
634
635bool radeon_get_bios(struct radeon_device *rdev)
636{
637 bool r;
638 uint16_t tmp;
639
640 r = radeon_atrm_get_bios(rdev);
641 if (r == false)
642 r = radeon_acpi_vfct_bios(rdev);
643 if (r == false)
644 r = igp_read_bios_from_vram(rdev);
645 if (r == false)
646 r = radeon_read_bios(rdev);
647 if (r == false) {
648 r = radeon_read_disabled_bios(rdev);
649 }
650 if (r == false) {
651 r = radeon_read_platform_bios(rdev);
652 }
653 if (r == false || rdev->bios == NULL) {
654 DRM_ERROR("Unable to locate a BIOS ROM\n");
655 rdev->bios = NULL;
656 return false;
657 }
658 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
659 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
660 goto free_bios;
661 }
662
663 tmp = RBIOS16(0x18);
664 if (RBIOS8(tmp + 0x14) != 0x0) {
665 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
666 goto free_bios;
667 }
668
669 rdev->bios_header_start = RBIOS16(0x48);
670 if (!rdev->bios_header_start) {
671 goto free_bios;
672 }
673 tmp = rdev->bios_header_start + 4;
674 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
675 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
676 rdev->is_atom_bios = true;
677 } else {
678 rdev->is_atom_bios = false;
679 }
680
681 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
682 return true;
683free_bios:
684 kfree(rdev->bios);
685 rdev->bios = NULL;
686 return false;
687}
688
