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26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
29#include <drm/drm_fixed.h>
30#include "radeon.h"
31#include "atom.h"
32
33static void radeon_overscan_setup(struct drm_crtc *crtc,
34 struct drm_display_mode *mode)
35{
36 struct drm_device *dev = crtc->dev;
37 struct radeon_device *rdev = dev->dev_private;
38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
39
40 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
41 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
42 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
43}
44
45static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
46 struct drm_display_mode *mode)
47{
48 struct drm_device *dev = crtc->dev;
49 struct radeon_device *rdev = dev->dev_private;
50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
51 int xres = mode->hdisplay;
52 int yres = mode->vdisplay;
53 bool hscale = true, vscale = true;
54 int hsync_wid;
55 int vsync_wid;
56 int hsync_start;
57 int blank_width;
58 u32 scale, inc, crtc_more_cntl;
59 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
60 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
61 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
62 struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
63
64 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
65 (RADEON_VERT_STRETCH_RESERVED |
66 RADEON_VERT_AUTO_RATIO_INC);
67 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
68 (RADEON_HORZ_FP_LOOP_STRETCH |
69 RADEON_HORZ_AUTO_RATIO_INC);
70
71 crtc_more_cntl = 0;
72 if ((rdev->family == CHIP_RS100) ||
73 (rdev->family == CHIP_RS200)) {
74
75
76 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
77 }
78
79
80 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
81 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
82
83 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
84 if (!hsync_wid)
85 hsync_wid = 1;
86 hsync_start = mode->crtc_hsync_start - 8;
87
88 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
89 | ((hsync_wid & 0x3f) << 16)
90 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
91 ? RADEON_CRTC_H_SYNC_POL
92 : 0));
93
94 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
95 | ((mode->crtc_vdisplay - 1) << 16));
96
97 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
98 if (!vsync_wid)
99 vsync_wid = 1;
100
101 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
102 | ((vsync_wid & 0x1f) << 16)
103 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
104 ? RADEON_CRTC_V_SYNC_POL
105 : 0));
106
107 fp_horz_vert_active = 0;
108
109 if (native_mode->hdisplay == 0 ||
110 native_mode->vdisplay == 0) {
111 hscale = false;
112 vscale = false;
113 } else {
114 if (xres > native_mode->hdisplay)
115 xres = native_mode->hdisplay;
116 if (yres > native_mode->vdisplay)
117 yres = native_mode->vdisplay;
118
119 if (xres == native_mode->hdisplay)
120 hscale = false;
121 if (yres == native_mode->vdisplay)
122 vscale = false;
123 }
124
125 switch (radeon_crtc->rmx_type) {
126 case RMX_FULL:
127 case RMX_ASPECT:
128 if (!hscale)
129 fp_horz_stretch |= ((xres/8-1) << 16);
130 else {
131 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
132 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
133 / native_mode->hdisplay + 1;
134 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
135 RADEON_HORZ_STRETCH_BLEND |
136 RADEON_HORZ_STRETCH_ENABLE |
137 ((native_mode->hdisplay/8-1) << 16));
138 }
139
140 if (!vscale)
141 fp_vert_stretch |= ((yres-1) << 12);
142 else {
143 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
144 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
145 / native_mode->vdisplay + 1;
146 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
147 RADEON_VERT_STRETCH_ENABLE |
148 RADEON_VERT_STRETCH_BLEND |
149 ((native_mode->vdisplay-1) << 12));
150 }
151 break;
152 case RMX_CENTER:
153 fp_horz_stretch |= ((xres/8-1) << 16);
154 fp_vert_stretch |= ((yres-1) << 12);
155
156 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
157 RADEON_CRTC_AUTO_VERT_CENTER_EN);
158
159 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
160 if (blank_width > 110)
161 blank_width = 110;
162
163 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
164 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
165
166 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
167 if (!hsync_wid)
168 hsync_wid = 1;
169
170 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
171 | ((hsync_wid & 0x3f) << 16)
172 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
173 ? RADEON_CRTC_H_SYNC_POL
174 : 0));
175
176 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
177 | ((mode->crtc_vdisplay - 1) << 16));
178
179 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
180 if (!vsync_wid)
181 vsync_wid = 1;
182
183 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
184 | ((vsync_wid & 0x1f) << 16)
185 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
186 ? RADEON_CRTC_V_SYNC_POL
187 : 0)));
188
189 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
190 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
191 break;
192 case RMX_OFF:
193 default:
194 fp_horz_stretch |= ((xres/8-1) << 16);
195 fp_vert_stretch |= ((yres-1) << 12);
196 break;
197 }
198
199 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
200 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
201 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
202 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
203 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
204 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
205 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
206 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
207}
208
209static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
210{
211 struct radeon_device *rdev = dev->dev_private;
212 int i = 0;
213
214
215
216
217
218 for (i = 0;
219 (i < 10000 &&
220 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
221 i++);
222}
223
224static void radeon_pll_write_update(struct drm_device *dev)
225{
226 struct radeon_device *rdev = dev->dev_private;
227
228 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
229
230 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
231 RADEON_PPLL_ATOMIC_UPDATE_W,
232 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
233}
234
235static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
236{
237 struct radeon_device *rdev = dev->dev_private;
238 int i = 0;
239
240
241
242
243
244
245 for (i = 0;
246 (i < 10000 &&
247 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
248 i++);
249}
250
251static void radeon_pll2_write_update(struct drm_device *dev)
252{
253 struct radeon_device *rdev = dev->dev_private;
254
255 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
256
257 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
258 RADEON_P2PLL_ATOMIC_UPDATE_W,
259 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
260}
261
262static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
263 uint16_t fb_div)
264{
265 unsigned int vcoFreq;
266
267 if (!ref_div)
268 return 1;
269
270 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
271
272
273
274
275
276 if (vcoFreq >= 30000)
277
278
279
280 return 7;
281 else if (vcoFreq >= 18000)
282
283
284
285 return 4;
286 else
287
288
289
290 return 1;
291}
292
293static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
294{
295 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
296 struct drm_device *dev = crtc->dev;
297 struct radeon_device *rdev = dev->dev_private;
298 uint32_t crtc_ext_cntl = 0;
299 uint32_t mask;
300
301 if (radeon_crtc->crtc_id)
302 mask = (RADEON_CRTC2_DISP_DIS |
303 RADEON_CRTC2_VSYNC_DIS |
304 RADEON_CRTC2_HSYNC_DIS |
305 RADEON_CRTC2_DISP_REQ_EN_B);
306 else
307 mask = (RADEON_CRTC_DISPLAY_DIS |
308 RADEON_CRTC_VSYNC_DIS |
309 RADEON_CRTC_HSYNC_DIS);
310
311
312
313
314
315
316
317
318 if (rdev->flags & RADEON_SINGLE_CRTC)
319 crtc_ext_cntl = RADEON_CRTC_CRT_ON;
320
321 switch (mode) {
322 case DRM_MODE_DPMS_ON:
323 radeon_crtc->enabled = true;
324
325 radeon_pm_compute_clocks(rdev);
326 if (radeon_crtc->crtc_id)
327 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
328 else {
329 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
330 RADEON_CRTC_DISP_REQ_EN_B));
331 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
332 }
333 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
334 radeon_crtc_load_lut(crtc);
335 break;
336 case DRM_MODE_DPMS_STANDBY:
337 case DRM_MODE_DPMS_SUSPEND:
338 case DRM_MODE_DPMS_OFF:
339 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
340 if (radeon_crtc->crtc_id)
341 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
342 else {
343 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
344 RADEON_CRTC_DISP_REQ_EN_B));
345 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
346 }
347 radeon_crtc->enabled = false;
348
349 radeon_pm_compute_clocks(rdev);
350 break;
351 }
352}
353
354int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
355 struct drm_framebuffer *old_fb)
356{
357 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
358}
359
360int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
361 struct drm_framebuffer *fb,
362 int x, int y, enum mode_set_atomic state)
363{
364 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
365}
366
367int radeon_crtc_do_set_base(struct drm_crtc *crtc,
368 struct drm_framebuffer *fb,
369 int x, int y, int atomic)
370{
371 struct drm_device *dev = crtc->dev;
372 struct radeon_device *rdev = dev->dev_private;
373 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
374 struct radeon_framebuffer *radeon_fb;
375 struct drm_framebuffer *target_fb;
376 struct drm_gem_object *obj;
377 struct radeon_bo *rbo;
378 uint64_t base;
379 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
380 uint32_t crtc_pitch, pitch_pixels;
381 uint32_t tiling_flags;
382 int format;
383 uint32_t gen_cntl_reg, gen_cntl_val;
384 int r;
385
386 DRM_DEBUG_KMS("\n");
387
388 if (!atomic && !crtc->fb) {
389 DRM_DEBUG_KMS("No FB bound\n");
390 return 0;
391 }
392
393 if (atomic) {
394 radeon_fb = to_radeon_framebuffer(fb);
395 target_fb = fb;
396 }
397 else {
398 radeon_fb = to_radeon_framebuffer(crtc->fb);
399 target_fb = crtc->fb;
400 }
401
402 switch (target_fb->bits_per_pixel) {
403 case 8:
404 format = 2;
405 break;
406 case 15:
407 format = 3;
408 break;
409 case 16:
410 format = 4;
411 break;
412 case 24:
413 format = 5;
414 break;
415 case 32:
416 format = 6;
417 break;
418 default:
419 return false;
420 }
421
422
423 obj = radeon_fb->obj;
424 rbo = gem_to_radeon_bo(obj);
425 r = radeon_bo_reserve(rbo, false);
426 if (unlikely(r != 0))
427 return r;
428
429 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
430 &base);
431 if (unlikely(r != 0)) {
432 radeon_bo_unreserve(rbo);
433 return -EINVAL;
434 }
435 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
436 radeon_bo_unreserve(rbo);
437 if (tiling_flags & RADEON_TILING_MICRO)
438 DRM_ERROR("trying to scanout microtiled buffer\n");
439
440
441
442 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
443
444 base -= radeon_crtc->legacy_display_base_addr;
445
446 crtc_offset_cntl = 0;
447
448 pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
449 crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) +
450 ((target_fb->bits_per_pixel * 8) - 1)) /
451 (target_fb->bits_per_pixel * 8));
452 crtc_pitch |= crtc_pitch << 16;
453
454 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
455 if (tiling_flags & RADEON_TILING_MACRO) {
456 if (ASIC_IS_R300(rdev))
457 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
458 R300_CRTC_MICRO_TILE_BUFFER_DIS |
459 R300_CRTC_MACRO_TILE_EN);
460 else
461 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
462 } else {
463 if (ASIC_IS_R300(rdev))
464 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
465 R300_CRTC_MICRO_TILE_BUFFER_DIS |
466 R300_CRTC_MACRO_TILE_EN);
467 else
468 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
469 }
470
471 if (tiling_flags & RADEON_TILING_MACRO) {
472 if (ASIC_IS_R300(rdev)) {
473 crtc_tile_x0_y0 = x | (y << 16);
474 base &= ~0x7ff;
475 } else {
476 int byteshift = target_fb->bits_per_pixel >> 4;
477 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
478 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
479 crtc_offset_cntl |= (y % 16);
480 }
481 } else {
482 int offset = y * pitch_pixels + x;
483 switch (target_fb->bits_per_pixel) {
484 case 8:
485 offset *= 1;
486 break;
487 case 15:
488 case 16:
489 offset *= 2;
490 break;
491 case 24:
492 offset *= 3;
493 break;
494 case 32:
495 offset *= 4;
496 break;
497 default:
498 return false;
499 }
500 base += offset;
501 }
502
503 base &= ~7;
504
505 if (radeon_crtc->crtc_id == 1)
506 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
507 else
508 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
509
510 gen_cntl_val = RREG32(gen_cntl_reg);
511 gen_cntl_val &= ~(0xf << 8);
512 gen_cntl_val |= (format << 8);
513 gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
514 WREG32(gen_cntl_reg, gen_cntl_val);
515
516 crtc_offset = (u32)base;
517
518 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
519
520 if (ASIC_IS_R300(rdev)) {
521 if (radeon_crtc->crtc_id)
522 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
523 else
524 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
525 }
526 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
527 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
528 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
529
530 if (!atomic && fb && fb != crtc->fb) {
531 radeon_fb = to_radeon_framebuffer(fb);
532 rbo = gem_to_radeon_bo(radeon_fb->obj);
533 r = radeon_bo_reserve(rbo, false);
534 if (unlikely(r != 0))
535 return r;
536 radeon_bo_unpin(rbo);
537 radeon_bo_unreserve(rbo);
538 }
539
540
541 radeon_bandwidth_update(rdev);
542
543 return 0;
544}
545
546static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
547{
548 struct drm_device *dev = crtc->dev;
549 struct radeon_device *rdev = dev->dev_private;
550 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
551 struct drm_encoder *encoder;
552 int format;
553 int hsync_start;
554 int hsync_wid;
555 int vsync_wid;
556 uint32_t crtc_h_total_disp;
557 uint32_t crtc_h_sync_strt_wid;
558 uint32_t crtc_v_total_disp;
559 uint32_t crtc_v_sync_strt_wid;
560 bool is_tv = false;
561
562 DRM_DEBUG_KMS("\n");
563 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
564 if (encoder->crtc == crtc) {
565 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
566 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
567 is_tv = true;
568 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
569 break;
570 }
571 }
572 }
573
574 switch (crtc->fb->bits_per_pixel) {
575 case 8:
576 format = 2;
577 break;
578 case 15:
579 format = 3;
580 break;
581 case 16:
582 format = 4;
583 break;
584 case 24:
585 format = 5;
586 break;
587 case 32:
588 format = 6;
589 break;
590 default:
591 return false;
592 }
593
594 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
595 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
596
597 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
598 if (!hsync_wid)
599 hsync_wid = 1;
600 hsync_start = mode->crtc_hsync_start - 8;
601
602 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
603 | ((hsync_wid & 0x3f) << 16)
604 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
605 ? RADEON_CRTC_H_SYNC_POL
606 : 0));
607
608
609 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
610 | ((mode->crtc_vdisplay - 1) << 16));
611
612 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
613 if (!vsync_wid)
614 vsync_wid = 1;
615
616 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
617 | ((vsync_wid & 0x1f) << 16)
618 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
619 ? RADEON_CRTC_V_SYNC_POL
620 : 0));
621
622 if (radeon_crtc->crtc_id) {
623 uint32_t crtc2_gen_cntl;
624 uint32_t disp2_merge_cntl;
625
626
627 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
628 crtc2_gen_cntl |= ((format << 8)
629 | RADEON_CRTC2_VSYNC_DIS
630 | RADEON_CRTC2_HSYNC_DIS
631 | RADEON_CRTC2_DISP_DIS
632 | RADEON_CRTC2_DISP_REQ_EN_B
633 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
634 ? RADEON_CRTC2_DBL_SCAN_EN
635 : 0)
636 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
637 ? RADEON_CRTC2_CSYNC_EN
638 : 0)
639 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
640 ? RADEON_CRTC2_INTERLACE_EN
641 : 0));
642
643
644 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
645 crtc2_gen_cntl |= RADEON_CRTC2_EN;
646
647 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
648 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
649
650 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
651 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
652
653 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
654 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
655 } else {
656 uint32_t crtc_gen_cntl;
657 uint32_t crtc_ext_cntl;
658 uint32_t disp_merge_cntl;
659
660 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
661 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
662 | (format << 8)
663 | RADEON_CRTC_DISP_REQ_EN_B
664 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
665 ? RADEON_CRTC_DBL_SCAN_EN
666 : 0)
667 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
668 ? RADEON_CRTC_CSYNC_EN
669 : 0)
670 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
671 ? RADEON_CRTC_INTERLACE_EN
672 : 0));
673
674
675 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
676 crtc_gen_cntl |= RADEON_CRTC_EN;
677
678 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
679 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
680 RADEON_CRTC_VSYNC_DIS |
681 RADEON_CRTC_HSYNC_DIS |
682 RADEON_CRTC_DISPLAY_DIS);
683
684 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
685 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
686
687 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
688 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
689 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
690 }
691
692 if (is_tv)
693 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
694 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
695 &crtc_v_sync_strt_wid);
696
697 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
698 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
699 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
700 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
701
702 return true;
703}
704
705static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
706{
707 struct drm_device *dev = crtc->dev;
708 struct radeon_device *rdev = dev->dev_private;
709 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
710 struct drm_encoder *encoder;
711 uint32_t feedback_div = 0;
712 uint32_t frac_fb_div = 0;
713 uint32_t reference_div = 0;
714 uint32_t post_divider = 0;
715 uint32_t freq = 0;
716 uint8_t pll_gain;
717 bool use_bios_divs = false;
718
719 uint32_t pll_ref_div = 0;
720 uint32_t pll_fb_post_div = 0;
721 uint32_t htotal_cntl = 0;
722 bool is_tv = false;
723 struct radeon_pll *pll;
724
725 struct {
726 int divider;
727 int bitvalue;
728 } *post_div, post_divs[] = {
729
730
731
732
733
734 { 1, 0 },
735 { 2, 1 },
736 { 4, 2 },
737 { 8, 3 },
738 { 3, 4 },
739 { 16, 5 },
740 { 6, 6 },
741 { 12, 7 },
742 { 0, 0 }
743 };
744
745 if (radeon_crtc->crtc_id)
746 pll = &rdev->clock.p2pll;
747 else
748 pll = &rdev->clock.p1pll;
749
750 pll->flags = RADEON_PLL_LEGACY;
751
752 if (mode->clock > 200000)
753 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
754 else
755 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
756
757 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
758 if (encoder->crtc == crtc) {
759 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
760
761 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
762 is_tv = true;
763 break;
764 }
765
766 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
767 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
768 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
769 if (!rdev->is_atom_bios) {
770 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
771 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
772 if (lvds) {
773 if (lvds->use_bios_dividers) {
774 pll_ref_div = lvds->panel_ref_divider;
775 pll_fb_post_div = (lvds->panel_fb_divider |
776 (lvds->panel_post_divider << 16));
777 htotal_cntl = 0;
778 use_bios_divs = true;
779 }
780 }
781 }
782 pll->flags |= RADEON_PLL_USE_REF_DIV;
783 }
784 }
785 }
786
787 DRM_DEBUG_KMS("\n");
788
789 if (!use_bios_divs) {
790 radeon_compute_pll_legacy(pll, mode->clock,
791 &freq, &feedback_div, &frac_fb_div,
792 &reference_div, &post_divider);
793
794 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
795 if (post_div->divider == post_divider)
796 break;
797 }
798
799 if (!post_div->divider)
800 post_div = &post_divs[0];
801
802 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
803 (unsigned)freq,
804 feedback_div,
805 reference_div,
806 post_divider);
807
808 pll_ref_div = reference_div;
809#if defined(__powerpc__) && (0)
810
811 if (info->MacModel == RADEON_MAC_IBOOK)
812 pll_fb_post_div = 0x000600ad;
813 else
814#endif
815 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
816
817 htotal_cntl = mode->htotal & 0x7;
818
819 }
820
821 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
822 pll_ref_div & 0x3ff,
823 pll_fb_post_div & 0x7ff);
824
825 if (radeon_crtc->crtc_id) {
826 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
827 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
828 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
829
830 if (is_tv) {
831 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
832 &pll_ref_div, &pll_fb_post_div,
833 &pixclks_cntl);
834 }
835
836 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
837 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
838 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
839
840 WREG32_PLL_P(RADEON_P2PLL_CNTL,
841 RADEON_P2PLL_RESET
842 | RADEON_P2PLL_ATOMIC_UPDATE_EN
843 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
844 ~(RADEON_P2PLL_RESET
845 | RADEON_P2PLL_ATOMIC_UPDATE_EN
846 | RADEON_P2PLL_PVG_MASK));
847
848 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
849 pll_ref_div,
850 ~RADEON_P2PLL_REF_DIV_MASK);
851
852 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
853 pll_fb_post_div,
854 ~RADEON_P2PLL_FB0_DIV_MASK);
855
856 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
857 pll_fb_post_div,
858 ~RADEON_P2PLL_POST0_DIV_MASK);
859
860 radeon_pll2_write_update(dev);
861 radeon_pll2_wait_for_read_update_complete(dev);
862
863 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
864
865 WREG32_PLL_P(RADEON_P2PLL_CNTL,
866 0,
867 ~(RADEON_P2PLL_RESET
868 | RADEON_P2PLL_SLEEP
869 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
870
871 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
872 (unsigned)pll_ref_div,
873 (unsigned)pll_fb_post_div,
874 (unsigned)htotal_cntl,
875 RREG32_PLL(RADEON_P2PLL_CNTL));
876 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
877 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
878 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
879 (unsigned)((pll_fb_post_div &
880 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
881
882 mdelay(50);
883
884 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
885 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
886 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
887
888 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
889 } else {
890 uint32_t pixclks_cntl;
891
892
893 if (is_tv) {
894 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
895 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
896 &pll_fb_post_div, &pixclks_cntl);
897 }
898
899 if (rdev->flags & RADEON_IS_MOBILITY) {
900
901
902
903
904
905
906 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
907 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
908 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
909 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
910 RADEON_PLL_DIV_SEL,
911 ~(RADEON_PLL_DIV_SEL));
912 r100_pll_errata_after_index(rdev);
913 return;
914 }
915 }
916
917 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
918 RADEON_VCLK_SRC_SEL_CPUCLK,
919 ~(RADEON_VCLK_SRC_SEL_MASK));
920 WREG32_PLL_P(RADEON_PPLL_CNTL,
921 RADEON_PPLL_RESET
922 | RADEON_PPLL_ATOMIC_UPDATE_EN
923 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
924 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
925 ~(RADEON_PPLL_RESET
926 | RADEON_PPLL_ATOMIC_UPDATE_EN
927 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
928 | RADEON_PPLL_PVG_MASK));
929
930 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
931 RADEON_PLL_DIV_SEL,
932 ~(RADEON_PLL_DIV_SEL));
933 r100_pll_errata_after_index(rdev);
934
935 if (ASIC_IS_R300(rdev) ||
936 (rdev->family == CHIP_RS300) ||
937 (rdev->family == CHIP_RS400) ||
938 (rdev->family == CHIP_RS480)) {
939 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
940
941
942
943 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
944 pll_ref_div,
945 0);
946 } else {
947
948 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
949 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
950 ~R300_PPLL_REF_DIV_ACC_MASK);
951 }
952 } else
953 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
954 pll_ref_div,
955 ~RADEON_PPLL_REF_DIV_MASK);
956
957 WREG32_PLL_P(RADEON_PPLL_DIV_3,
958 pll_fb_post_div,
959 ~RADEON_PPLL_FB3_DIV_MASK);
960
961 WREG32_PLL_P(RADEON_PPLL_DIV_3,
962 pll_fb_post_div,
963 ~RADEON_PPLL_POST3_DIV_MASK);
964
965 radeon_pll_write_update(dev);
966 radeon_pll_wait_for_read_update_complete(dev);
967
968 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
969
970 WREG32_PLL_P(RADEON_PPLL_CNTL,
971 0,
972 ~(RADEON_PPLL_RESET
973 | RADEON_PPLL_SLEEP
974 | RADEON_PPLL_ATOMIC_UPDATE_EN
975 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
976
977 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
978 pll_ref_div,
979 pll_fb_post_div,
980 (unsigned)htotal_cntl,
981 RREG32_PLL(RADEON_PPLL_CNTL));
982 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
983 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
984 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
985 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
986
987 mdelay(50);
988
989 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
990 RADEON_VCLK_SRC_SEL_PPLLCLK,
991 ~(RADEON_VCLK_SRC_SEL_MASK));
992
993 if (is_tv)
994 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
995 }
996}
997
998static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
999 const struct drm_display_mode *mode,
1000 struct drm_display_mode *adjusted_mode)
1001{
1002 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1003 return false;
1004 return true;
1005}
1006
1007static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1008 struct drm_display_mode *mode,
1009 struct drm_display_mode *adjusted_mode,
1010 int x, int y, struct drm_framebuffer *old_fb)
1011{
1012 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1013
1014
1015 radeon_crtc_set_base(crtc, x, y, old_fb);
1016 radeon_set_crtc_timing(crtc, adjusted_mode);
1017 radeon_set_pll(crtc, adjusted_mode);
1018 radeon_overscan_setup(crtc, adjusted_mode);
1019 if (radeon_crtc->crtc_id == 0) {
1020 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1021 } else {
1022 if (radeon_crtc->rmx_type != RMX_OFF) {
1023
1024
1025
1026 DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1027 }
1028 }
1029 return 0;
1030}
1031
1032static void radeon_crtc_prepare(struct drm_crtc *crtc)
1033{
1034 struct drm_device *dev = crtc->dev;
1035 struct drm_crtc *crtci;
1036
1037
1038
1039
1040
1041 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1042 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1043}
1044
1045static void radeon_crtc_commit(struct drm_crtc *crtc)
1046{
1047 struct drm_device *dev = crtc->dev;
1048 struct drm_crtc *crtci;
1049
1050
1051
1052
1053 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1054 if (crtci->enabled)
1055 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1056 }
1057}
1058
1059static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1060 .dpms = radeon_crtc_dpms,
1061 .mode_fixup = radeon_crtc_mode_fixup,
1062 .mode_set = radeon_crtc_mode_set,
1063 .mode_set_base = radeon_crtc_set_base,
1064 .mode_set_base_atomic = radeon_crtc_set_base_atomic,
1065 .prepare = radeon_crtc_prepare,
1066 .commit = radeon_crtc_commit,
1067 .load_lut = radeon_crtc_load_lut,
1068};
1069
1070
1071void radeon_legacy_init_crtc(struct drm_device *dev,
1072 struct radeon_crtc *radeon_crtc)
1073{
1074 if (radeon_crtc->crtc_id == 1)
1075 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1076 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1077}
1078
