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38#include <drm/drmP.h>
39#include "radeon.h"
40#include "radeon_asic.h"
41#include "atom.h"
42#include "rs600d.h"
43
44#include "rs600_reg_safe.h"
45
46static void rs600_gpu_init(struct radeon_device *rdev);
47int rs600_mc_wait_for_idle(struct radeon_device *rdev);
48
49static const u32 crtc_offsets[2] =
50{
51 0,
52 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
53};
54
55static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
56{
57 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
58 return true;
59 else
60 return false;
61}
62
63static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
64{
65 u32 pos1, pos2;
66
67 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
68 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
69
70 if (pos1 != pos2)
71 return true;
72 else
73 return false;
74}
75
76
77
78
79
80
81
82
83
84void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
85{
86 unsigned i = 0;
87
88 if (crtc >= rdev->num_crtc)
89 return;
90
91 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
92 return;
93
94
95
96
97 while (avivo_is_in_vblank(rdev, crtc)) {
98 if (i++ % 100 == 0) {
99 if (!avivo_is_counter_moving(rdev, crtc))
100 break;
101 }
102 }
103
104 while (!avivo_is_in_vblank(rdev, crtc)) {
105 if (i++ % 100 == 0) {
106 if (!avivo_is_counter_moving(rdev, crtc))
107 break;
108 }
109 }
110}
111
112void rs600_pre_page_flip(struct radeon_device *rdev, int crtc)
113{
114
115 radeon_irq_kms_pflip_irq_get(rdev, crtc);
116}
117
118void rs600_post_page_flip(struct radeon_device *rdev, int crtc)
119{
120
121 radeon_irq_kms_pflip_irq_put(rdev, crtc);
122}
123
124u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
125{
126 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
127 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
128 int i;
129
130
131 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
132 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
133
134
135 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
136 (u32)crtc_base);
137 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
138 (u32)crtc_base);
139
140
141 for (i = 0; i < rdev->usec_timeout; i++) {
142 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
143 break;
144 udelay(1);
145 }
146 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
147
148
149 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
150 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
151
152
153 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
154}
155
156void rs600_pm_misc(struct radeon_device *rdev)
157{
158 int requested_index = rdev->pm.requested_power_state_index;
159 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
160 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
161 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
162 u32 hdp_dyn_cntl, dyn_backbias_cntl;
163
164 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
165 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
166 tmp = RREG32(voltage->gpio.reg);
167 if (voltage->active_high)
168 tmp |= voltage->gpio.mask;
169 else
170 tmp &= ~(voltage->gpio.mask);
171 WREG32(voltage->gpio.reg, tmp);
172 if (voltage->delay)
173 udelay(voltage->delay);
174 } else {
175 tmp = RREG32(voltage->gpio.reg);
176 if (voltage->active_high)
177 tmp &= ~voltage->gpio.mask;
178 else
179 tmp |= voltage->gpio.mask;
180 WREG32(voltage->gpio.reg, tmp);
181 if (voltage->delay)
182 udelay(voltage->delay);
183 }
184 } else if (voltage->type == VOLTAGE_VDDC)
185 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
186
187 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
188 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
189 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
190 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
191 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
192 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
193 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
194 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
195 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
196 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
197 }
198 } else {
199 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
200 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
201 }
202 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
203
204 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
205 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
206 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
207 if (voltage->delay) {
208 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
209 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
210 } else
211 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
212 } else
213 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
214 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
215
216 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
217 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
218 hdp_dyn_cntl &= ~HDP_FORCEON;
219 else
220 hdp_dyn_cntl |= HDP_FORCEON;
221 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
222#if 0
223
224 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
225 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
226 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
227 else
228 mc_host_dyn_cntl |= MC_HOST_FORCEON;
229 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
230#endif
231 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
232 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
233 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
234 else
235 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
236 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
237
238
239 if ((rdev->flags & RADEON_IS_PCIE) &&
240 !(rdev->flags & RADEON_IS_IGP) &&
241 rdev->asic->pm.set_pcie_lanes &&
242 (ps->pcie_lanes !=
243 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
244 radeon_set_pcie_lanes(rdev,
245 ps->pcie_lanes);
246 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
247 }
248}
249
250void rs600_pm_prepare(struct radeon_device *rdev)
251{
252 struct drm_device *ddev = rdev->ddev;
253 struct drm_crtc *crtc;
254 struct radeon_crtc *radeon_crtc;
255 u32 tmp;
256
257
258 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
259 radeon_crtc = to_radeon_crtc(crtc);
260 if (radeon_crtc->enabled) {
261 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
262 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
263 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
264 }
265 }
266}
267
268void rs600_pm_finish(struct radeon_device *rdev)
269{
270 struct drm_device *ddev = rdev->ddev;
271 struct drm_crtc *crtc;
272 struct radeon_crtc *radeon_crtc;
273 u32 tmp;
274
275
276 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
277 radeon_crtc = to_radeon_crtc(crtc);
278 if (radeon_crtc->enabled) {
279 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
280 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
281 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
282 }
283 }
284}
285
286
287bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
288{
289 u32 tmp;
290 bool connected = false;
291
292 switch (hpd) {
293 case RADEON_HPD_1:
294 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
295 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
296 connected = true;
297 break;
298 case RADEON_HPD_2:
299 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
300 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
301 connected = true;
302 break;
303 default:
304 break;
305 }
306 return connected;
307}
308
309void rs600_hpd_set_polarity(struct radeon_device *rdev,
310 enum radeon_hpd_id hpd)
311{
312 u32 tmp;
313 bool connected = rs600_hpd_sense(rdev, hpd);
314
315 switch (hpd) {
316 case RADEON_HPD_1:
317 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
318 if (connected)
319 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
320 else
321 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
322 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
323 break;
324 case RADEON_HPD_2:
325 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
326 if (connected)
327 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
328 else
329 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
330 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
331 break;
332 default:
333 break;
334 }
335}
336
337void rs600_hpd_init(struct radeon_device *rdev)
338{
339 struct drm_device *dev = rdev->ddev;
340 struct drm_connector *connector;
341 unsigned enable = 0;
342
343 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
344 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
345 switch (radeon_connector->hpd.hpd) {
346 case RADEON_HPD_1:
347 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
348 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
349 break;
350 case RADEON_HPD_2:
351 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
352 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
353 break;
354 default:
355 break;
356 }
357 enable |= 1 << radeon_connector->hpd.hpd;
358 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
359 }
360 radeon_irq_kms_enable_hpd(rdev, enable);
361}
362
363void rs600_hpd_fini(struct radeon_device *rdev)
364{
365 struct drm_device *dev = rdev->ddev;
366 struct drm_connector *connector;
367 unsigned disable = 0;
368
369 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
370 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
371 switch (radeon_connector->hpd.hpd) {
372 case RADEON_HPD_1:
373 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
374 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
375 break;
376 case RADEON_HPD_2:
377 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
378 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
379 break;
380 default:
381 break;
382 }
383 disable |= 1 << radeon_connector->hpd.hpd;
384 }
385 radeon_irq_kms_disable_hpd(rdev, disable);
386}
387
388int rs600_asic_reset(struct radeon_device *rdev)
389{
390 struct rv515_mc_save save;
391 u32 status, tmp;
392 int ret = 0;
393
394 status = RREG32(R_000E40_RBBM_STATUS);
395 if (!G_000E40_GUI_ACTIVE(status)) {
396 return 0;
397 }
398
399 rv515_mc_stop(rdev, &save);
400 status = RREG32(R_000E40_RBBM_STATUS);
401 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
402
403 WREG32(RADEON_CP_CSQ_CNTL, 0);
404 tmp = RREG32(RADEON_CP_RB_CNTL);
405 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
406 WREG32(RADEON_CP_RB_RPTR_WR, 0);
407 WREG32(RADEON_CP_RB_WPTR, 0);
408 WREG32(RADEON_CP_RB_CNTL, tmp);
409 pci_save_state(rdev->pdev);
410
411 pci_clear_master(rdev->pdev);
412 mdelay(1);
413
414 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
415 S_0000F0_SOFT_RESET_GA(1));
416 RREG32(R_0000F0_RBBM_SOFT_RESET);
417 mdelay(500);
418 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
419 mdelay(1);
420 status = RREG32(R_000E40_RBBM_STATUS);
421 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
422
423 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
424 RREG32(R_0000F0_RBBM_SOFT_RESET);
425 mdelay(500);
426 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
427 mdelay(1);
428 status = RREG32(R_000E40_RBBM_STATUS);
429 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
430
431 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
432 RREG32(R_0000F0_RBBM_SOFT_RESET);
433 mdelay(500);
434 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
435 mdelay(1);
436 status = RREG32(R_000E40_RBBM_STATUS);
437 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
438
439 pci_restore_state(rdev->pdev);
440
441 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
442 dev_err(rdev->dev, "failed to reset GPU\n");
443 ret = -1;
444 } else
445 dev_info(rdev->dev, "GPU reset succeed\n");
446 rv515_mc_resume(rdev, &save);
447 return ret;
448}
449
450
451
452
453void rs600_gart_tlb_flush(struct radeon_device *rdev)
454{
455 uint32_t tmp;
456
457 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
458 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
459 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
460
461 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
462 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
463 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
464
465 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
466 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
467 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
468 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
469}
470
471static int rs600_gart_init(struct radeon_device *rdev)
472{
473 int r;
474
475 if (rdev->gart.robj) {
476 WARN(1, "RS600 GART already initialized\n");
477 return 0;
478 }
479
480 r = radeon_gart_init(rdev);
481 if (r) {
482 return r;
483 }
484 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
485 return radeon_gart_table_vram_alloc(rdev);
486}
487
488static int rs600_gart_enable(struct radeon_device *rdev)
489{
490 u32 tmp;
491 int r, i;
492
493 if (rdev->gart.robj == NULL) {
494 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
495 return -EINVAL;
496 }
497 r = radeon_gart_table_vram_pin(rdev);
498 if (r)
499 return r;
500 radeon_gart_restore(rdev);
501
502 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
503 WREG32(RADEON_BUS_CNTL, tmp);
504
505 WREG32_MC(R_000100_MC_PT0_CNTL,
506 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
507 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
508
509 for (i = 0; i < 19; i++) {
510 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
511 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
512 S_00016C_SYSTEM_ACCESS_MODE_MASK(
513 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
514 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
515 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
516 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
517 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
518 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
519 }
520
521 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
522 S_000102_ENABLE_PAGE_TABLE(1) |
523 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
524
525
526 for (i = 1; i < 8; i++)
527 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
528
529
530 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
531 rdev->gart.table_addr);
532 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
533 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
534 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
535
536
537 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
538 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
539
540
541 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
542 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
543 tmp = RREG32_MC(R_000009_MC_CNTL1);
544 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
545 rs600_gart_tlb_flush(rdev);
546 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
547 (unsigned)(rdev->mc.gtt_size >> 20),
548 (unsigned long long)rdev->gart.table_addr);
549 rdev->gart.ready = true;
550 return 0;
551}
552
553static void rs600_gart_disable(struct radeon_device *rdev)
554{
555 u32 tmp;
556
557
558 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
559 tmp = RREG32_MC(R_000009_MC_CNTL1);
560 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
561 radeon_gart_table_vram_unpin(rdev);
562}
563
564static void rs600_gart_fini(struct radeon_device *rdev)
565{
566 radeon_gart_fini(rdev);
567 rs600_gart_disable(rdev);
568 radeon_gart_table_vram_free(rdev);
569}
570
571#define R600_PTE_VALID (1 << 0)
572#define R600_PTE_SYSTEM (1 << 1)
573#define R600_PTE_SNOOPED (1 << 2)
574#define R600_PTE_READABLE (1 << 5)
575#define R600_PTE_WRITEABLE (1 << 6)
576
577int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
578{
579 void __iomem *ptr = (void *)rdev->gart.ptr;
580
581 if (i < 0 || i > rdev->gart.num_gpu_pages) {
582 return -EINVAL;
583 }
584 addr = addr & 0xFFFFFFFFFFFFF000ULL;
585 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
586 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
587 writeq(addr, ptr + (i * 8));
588 return 0;
589}
590
591int rs600_irq_set(struct radeon_device *rdev)
592{
593 uint32_t tmp = 0;
594 uint32_t mode_int = 0;
595 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
596 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
597 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
598 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
599 u32 hdmi0;
600 if (ASIC_IS_DCE2(rdev))
601 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
602 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
603 else
604 hdmi0 = 0;
605
606 if (!rdev->irq.installed) {
607 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
608 WREG32(R_000040_GEN_INT_CNTL, 0);
609 return -EINVAL;
610 }
611 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
612 tmp |= S_000040_SW_INT_EN(1);
613 }
614 if (rdev->irq.crtc_vblank_int[0] ||
615 atomic_read(&rdev->irq.pflip[0])) {
616 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
617 }
618 if (rdev->irq.crtc_vblank_int[1] ||
619 atomic_read(&rdev->irq.pflip[1])) {
620 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
621 }
622 if (rdev->irq.hpd[0]) {
623 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
624 }
625 if (rdev->irq.hpd[1]) {
626 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
627 }
628 if (rdev->irq.afmt[0]) {
629 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
630 }
631 WREG32(R_000040_GEN_INT_CNTL, tmp);
632 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
633 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
634 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
635 if (ASIC_IS_DCE2(rdev))
636 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
637 return 0;
638}
639
640static inline u32 rs600_irq_ack(struct radeon_device *rdev)
641{
642 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
643 uint32_t irq_mask = S_000044_SW_INT(1);
644 u32 tmp;
645
646 if (G_000044_DISPLAY_INT_STAT(irqs)) {
647 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
648 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
649 WREG32(R_006534_D1MODE_VBLANK_STATUS,
650 S_006534_D1MODE_VBLANK_ACK(1));
651 }
652 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
653 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
654 S_006D34_D2MODE_VBLANK_ACK(1));
655 }
656 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
657 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
658 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
659 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
660 }
661 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
662 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
663 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
664 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
665 }
666 } else {
667 rdev->irq.stat_regs.r500.disp_int = 0;
668 }
669
670 if (ASIC_IS_DCE2(rdev)) {
671 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
672 S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
673 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
674 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
675 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
676 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
677 }
678 } else
679 rdev->irq.stat_regs.r500.hdmi0_status = 0;
680
681 if (irqs) {
682 WREG32(R_000044_GEN_INT_STATUS, irqs);
683 }
684 return irqs & irq_mask;
685}
686
687void rs600_irq_disable(struct radeon_device *rdev)
688{
689 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
690 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
691 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
692 WREG32(R_000040_GEN_INT_CNTL, 0);
693 WREG32(R_006540_DxMODE_INT_MASK, 0);
694
695 mdelay(1);
696 rs600_irq_ack(rdev);
697}
698
699int rs600_irq_process(struct radeon_device *rdev)
700{
701 u32 status, msi_rearm;
702 bool queue_hotplug = false;
703 bool queue_hdmi = false;
704
705 status = rs600_irq_ack(rdev);
706 if (!status &&
707 !rdev->irq.stat_regs.r500.disp_int &&
708 !rdev->irq.stat_regs.r500.hdmi0_status) {
709 return IRQ_NONE;
710 }
711 while (status ||
712 rdev->irq.stat_regs.r500.disp_int ||
713 rdev->irq.stat_regs.r500.hdmi0_status) {
714
715 if (G_000044_SW_INT(status)) {
716 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
717 }
718
719 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
720 if (rdev->irq.crtc_vblank_int[0]) {
721 drm_handle_vblank(rdev->ddev, 0);
722 rdev->pm.vblank_sync = true;
723 wake_up(&rdev->irq.vblank_queue);
724 }
725 if (atomic_read(&rdev->irq.pflip[0]))
726 radeon_crtc_handle_flip(rdev, 0);
727 }
728 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
729 if (rdev->irq.crtc_vblank_int[1]) {
730 drm_handle_vblank(rdev->ddev, 1);
731 rdev->pm.vblank_sync = true;
732 wake_up(&rdev->irq.vblank_queue);
733 }
734 if (atomic_read(&rdev->irq.pflip[1]))
735 radeon_crtc_handle_flip(rdev, 1);
736 }
737 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
738 queue_hotplug = true;
739 DRM_DEBUG("HPD1\n");
740 }
741 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
742 queue_hotplug = true;
743 DRM_DEBUG("HPD2\n");
744 }
745 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
746 queue_hdmi = true;
747 DRM_DEBUG("HDMI0\n");
748 }
749 status = rs600_irq_ack(rdev);
750 }
751 if (queue_hotplug)
752 schedule_work(&rdev->hotplug_work);
753 if (queue_hdmi)
754 schedule_work(&rdev->audio_work);
755 if (rdev->msi_enabled) {
756 switch (rdev->family) {
757 case CHIP_RS600:
758 case CHIP_RS690:
759 case CHIP_RS740:
760 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
761 WREG32(RADEON_BUS_CNTL, msi_rearm);
762 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
763 break;
764 default:
765 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
766 break;
767 }
768 }
769 return IRQ_HANDLED;
770}
771
772u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
773{
774 if (crtc == 0)
775 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
776 else
777 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
778}
779
780int rs600_mc_wait_for_idle(struct radeon_device *rdev)
781{
782 unsigned i;
783
784 for (i = 0; i < rdev->usec_timeout; i++) {
785 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
786 return 0;
787 udelay(1);
788 }
789 return -1;
790}
791
792static void rs600_gpu_init(struct radeon_device *rdev)
793{
794 r420_pipes_init(rdev);
795
796 if (rs600_mc_wait_for_idle(rdev))
797 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
798}
799
800static void rs600_mc_init(struct radeon_device *rdev)
801{
802 u64 base;
803
804 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
805 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
806 rdev->mc.vram_is_ddr = true;
807 rdev->mc.vram_width = 128;
808 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
809 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
810 rdev->mc.visible_vram_size = rdev->mc.aper_size;
811 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
812 base = RREG32_MC(R_000004_MC_FB_LOCATION);
813 base = G_000004_MC_FB_START(base) << 16;
814 radeon_vram_location(rdev, &rdev->mc, base);
815 rdev->mc.gtt_base_align = 0;
816 radeon_gtt_location(rdev, &rdev->mc);
817 radeon_update_bandwidth_info(rdev);
818}
819
820void rs600_bandwidth_update(struct radeon_device *rdev)
821{
822 struct drm_display_mode *mode0 = NULL;
823 struct drm_display_mode *mode1 = NULL;
824 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
825
826
827 radeon_update_display_priority(rdev);
828
829 if (rdev->mode_info.crtcs[0]->base.enabled)
830 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
831 if (rdev->mode_info.crtcs[1]->base.enabled)
832 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
833
834 rs690_line_buffer_adjust(rdev, mode0, mode1);
835
836 if (rdev->disp_priority == 2) {
837 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
838 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
839 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
840 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
841 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
842 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
843 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
844 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
845 }
846}
847
848uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
849{
850 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
851 S_000070_MC_IND_CITF_ARB0(1));
852 return RREG32(R_000074_MC_IND_DATA);
853}
854
855void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
856{
857 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
858 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
859 WREG32(R_000074_MC_IND_DATA, v);
860}
861
862static void rs600_debugfs(struct radeon_device *rdev)
863{
864 if (r100_debugfs_rbbm_init(rdev))
865 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
866}
867
868void rs600_set_safe_registers(struct radeon_device *rdev)
869{
870 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
871 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
872}
873
874static void rs600_mc_program(struct radeon_device *rdev)
875{
876 struct rv515_mc_save save;
877
878
879 rv515_mc_stop(rdev, &save);
880
881
882 if (rs600_mc_wait_for_idle(rdev))
883 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
884
885
886 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
887 WREG32_MC(R_000006_AGP_BASE, 0);
888 WREG32_MC(R_000007_AGP_BASE_2, 0);
889
890 WREG32_MC(R_000004_MC_FB_LOCATION,
891 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
892 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
893 WREG32(R_000134_HDP_FB_LOCATION,
894 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
895
896 rv515_mc_resume(rdev, &save);
897}
898
899static int rs600_startup(struct radeon_device *rdev)
900{
901 int r;
902
903 rs600_mc_program(rdev);
904
905 rv515_clock_startup(rdev);
906
907 rs600_gpu_init(rdev);
908
909
910 r = rs600_gart_enable(rdev);
911 if (r)
912 return r;
913
914
915 r = radeon_wb_init(rdev);
916 if (r)
917 return r;
918
919 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
920 if (r) {
921 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
922 return r;
923 }
924
925
926 if (!rdev->irq.installed) {
927 r = radeon_irq_kms_init(rdev);
928 if (r)
929 return r;
930 }
931
932 rs600_irq_set(rdev);
933 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
934
935 r = r100_cp_init(rdev, 1024 * 1024);
936 if (r) {
937 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
938 return r;
939 }
940
941 r = radeon_ib_pool_init(rdev);
942 if (r) {
943 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
944 return r;
945 }
946
947 r = r600_audio_init(rdev);
948 if (r) {
949 dev_err(rdev->dev, "failed initializing audio\n");
950 return r;
951 }
952
953 return 0;
954}
955
956int rs600_resume(struct radeon_device *rdev)
957{
958 int r;
959
960
961 rs600_gart_disable(rdev);
962
963 rv515_clock_startup(rdev);
964
965 if (radeon_asic_reset(rdev)) {
966 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
967 RREG32(R_000E40_RBBM_STATUS),
968 RREG32(R_0007C0_CP_STAT));
969 }
970
971 atom_asic_init(rdev->mode_info.atom_context);
972
973 rv515_clock_startup(rdev);
974
975 radeon_surface_init(rdev);
976
977 rdev->accel_working = true;
978 r = rs600_startup(rdev);
979 if (r) {
980 rdev->accel_working = false;
981 }
982 return r;
983}
984
985int rs600_suspend(struct radeon_device *rdev)
986{
987 r600_audio_fini(rdev);
988 r100_cp_disable(rdev);
989 radeon_wb_disable(rdev);
990 rs600_irq_disable(rdev);
991 rs600_gart_disable(rdev);
992 return 0;
993}
994
995void rs600_fini(struct radeon_device *rdev)
996{
997 r600_audio_fini(rdev);
998 r100_cp_fini(rdev);
999 radeon_wb_fini(rdev);
1000 radeon_ib_pool_fini(rdev);
1001 radeon_gem_fini(rdev);
1002 rs600_gart_fini(rdev);
1003 radeon_irq_kms_fini(rdev);
1004 radeon_fence_driver_fini(rdev);
1005 radeon_bo_fini(rdev);
1006 radeon_atombios_fini(rdev);
1007 kfree(rdev->bios);
1008 rdev->bios = NULL;
1009}
1010
1011int rs600_init(struct radeon_device *rdev)
1012{
1013 int r;
1014
1015
1016 rv515_vga_render_disable(rdev);
1017
1018 radeon_scratch_init(rdev);
1019
1020 radeon_surface_init(rdev);
1021
1022 r100_restore_sanity(rdev);
1023
1024 if (!radeon_get_bios(rdev)) {
1025 if (ASIC_IS_AVIVO(rdev))
1026 return -EINVAL;
1027 }
1028 if (rdev->is_atom_bios) {
1029 r = radeon_atombios_init(rdev);
1030 if (r)
1031 return r;
1032 } else {
1033 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1034 return -EINVAL;
1035 }
1036
1037 if (radeon_asic_reset(rdev)) {
1038 dev_warn(rdev->dev,
1039 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1040 RREG32(R_000E40_RBBM_STATUS),
1041 RREG32(R_0007C0_CP_STAT));
1042 }
1043
1044 if (radeon_boot_test_post_card(rdev) == false)
1045 return -EINVAL;
1046
1047
1048 radeon_get_clock_info(rdev->ddev);
1049
1050 rs600_mc_init(rdev);
1051 rs600_debugfs(rdev);
1052
1053 r = radeon_fence_driver_init(rdev);
1054 if (r)
1055 return r;
1056
1057 r = radeon_bo_init(rdev);
1058 if (r)
1059 return r;
1060 r = rs600_gart_init(rdev);
1061 if (r)
1062 return r;
1063 rs600_set_safe_registers(rdev);
1064
1065 rdev->accel_working = true;
1066 r = rs600_startup(rdev);
1067 if (r) {
1068
1069 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1070 r100_cp_fini(rdev);
1071 radeon_wb_fini(rdev);
1072 radeon_ib_pool_fini(rdev);
1073 rs600_gart_fini(rdev);
1074 radeon_irq_kms_fini(rdev);
1075 rdev->accel_working = false;
1076 }
1077 return 0;
1078}
1079
