1/* via_dmablit.h -- PCI DMA BitBlt support for the VIA Unichrome/Pro 2 * 3 * Copyright 2005 Thomas Hellstrom. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sub license, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 23 * USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Thomas Hellstrom. 27 * Register info from Digeo Inc. 28 */ 29 30#ifndef _VIA_DMABLIT_H 31#define _VIA_DMABLIT_H 32 33#include <linux/dma-mapping.h> 34 35#define VIA_NUM_BLIT_ENGINES 2 36#define VIA_NUM_BLIT_SLOTS 8 37 38struct _drm_via_descriptor; 39 40typedef struct _drm_via_sg_info { 41 struct page **pages; 42 unsigned long num_pages; 43 struct _drm_via_descriptor **desc_pages; 44 int num_desc_pages; 45 int num_desc; 46 enum dma_data_direction direction; 47 unsigned char *bounce_buffer; 48 dma_addr_t chain_start; 49 uint32_t free_on_sequence; 50 unsigned int descriptors_per_page; 51 int aborted; 52 enum { 53 dr_via_device_mapped, 54 dr_via_desc_pages_alloc, 55 dr_via_pages_locked, 56 dr_via_pages_alloc, 57 dr_via_sg_init 58 } state; 59} drm_via_sg_info_t; 60 61typedef struct _drm_via_blitq { 62 struct drm_device *dev; 63 uint32_t cur_blit_handle; 64 uint32_t done_blit_handle; 65 unsigned serviced; 66 unsigned head; 67 unsigned cur; 68 unsigned num_free; 69 unsigned num_outstanding; 70 unsigned long end; 71 int aborting; 72 int is_active; 73 drm_via_sg_info_t *blits[VIA_NUM_BLIT_SLOTS]; 74 spinlock_t blit_lock; 75 wait_queue_head_t blit_queue[VIA_NUM_BLIT_SLOTS]; 76 wait_queue_head_t busy_queue; 77 struct work_struct wq; 78 struct timer_list poll_timer; 79} drm_via_blitq_t; 80 81 82/* 83 * PCI DMA Registers 84 * Channels 2 & 3 don't seem to be implemented in hardware. 85 */ 86 87#define VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */ 88#define VIA_PCI_DMA_DAR0 0xE44 /* Device Address Register of Channel 0 */ 89#define VIA_PCI_DMA_BCR0 0xE48 /* Byte Count Register of Channel 0 */ 90#define VIA_PCI_DMA_DPR0 0xE4C /* Descriptor Pointer Register of Channel 0 */ 91 92#define VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */ 93#define VIA_PCI_DMA_DAR1 0xE54 /* Device Address Register of Channel 1 */ 94#define VIA_PCI_DMA_BCR1 0xE58 /* Byte Count Register of Channel 1 */ 95#define VIA_PCI_DMA_DPR1 0xE5C /* Descriptor Pointer Register of Channel 1 */ 96 97#define VIA_PCI_DMA_MAR2 0xE60 /* Memory Address Register of Channel 2 */ 98#define VIA_PCI_DMA_DAR2 0xE64 /* Device Address Register of Channel 2 */ 99#define VIA_PCI_DMA_BCR2 0xE68 /* Byte Count Register of Channel 2 */ 100#define VIA_PCI_DMA_DPR2 0xE6C /* Descriptor Pointer Register of Channel 2 */ 101 102#define VIA_PCI_DMA_MAR3 0xE70 /* Memory Address Register of Channel 3 */ 103#define VIA_PCI_DMA_DAR3 0xE74 /* Device Address Register of Channel 3 */ 104#define VIA_PCI_DMA_BCR3 0xE78 /* Byte Count Register of Channel 3 */ 105#define VIA_PCI_DMA_DPR3 0xE7C /* Descriptor Pointer Register of Channel 3 */ 106 107#define VIA_PCI_DMA_MR0 0xE80 /* Mode Register of Channel 0 */ 108#define VIA_PCI_DMA_MR1 0xE84 /* Mode Register of Channel 1 */ 109#define VIA_PCI_DMA_MR2 0xE88 /* Mode Register of Channel 2 */ 110#define VIA_PCI_DMA_MR3 0xE8C /* Mode Register of Channel 3 */ 111 112#define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */ 113#define VIA_PCI_DMA_CSR1 0xE94 /* Command/Status Register of Channel 1 */ 114#define VIA_PCI_DMA_CSR2 0xE98 /* Command/Status Register of Channel 2 */ 115#define VIA_PCI_DMA_CSR3 0xE9C /* Command/Status Register of Channel 3 */ 116 117#define VIA_PCI_DMA_PTR 0xEA0 /* Priority Type Register */ 118 119/* Define for DMA engine */ 120/* DPR */ 121#define VIA_DMA_DPR_EC (1<<1) /* end of chain */ 122#define VIA_DMA_DPR_DDIE (1<<2) /* descriptor done interrupt enable */ 123#define VIA_DMA_DPR_DT (1<<3) /* direction of transfer (RO) */ 124 125/* MR */ 126#define VIA_DMA_MR_CM (1<<0) /* chaining mode */ 127#define VIA_DMA_MR_TDIE (1<<1) /* transfer done interrupt enable */ 128#define VIA_DMA_MR_HENDMACMD (1<<7) /* ? */ 129 130/* CSR */ 131#define VIA_DMA_CSR_DE (1<<0) /* DMA enable */ 132#define VIA_DMA_CSR_TS (1<<1) /* transfer start */ 133#define VIA_DMA_CSR_TA (1<<2) /* transfer abort */ 134#define VIA_DMA_CSR_TD (1<<3) /* transfer done */ 135#define VIA_DMA_CSR_DD (1<<4) /* descriptor done */ 136#define VIA_DMA_DPR_EC (1<<1) /* end of chain */ 137 138 139 140#endif 141