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23#include <linux/kernel.h>
24#include <linux/module.h>
25
26#include <linux/i2c.h>
27#include <linux/init.h>
28#include <linux/time.h>
29#include <linux/interrupt.h>
30#include <linux/delay.h>
31#include <linux/errno.h>
32#include <linux/err.h>
33#include <linux/platform_device.h>
34#include <linux/pm_runtime.h>
35#include <linux/clk.h>
36#include <linux/cpufreq.h>
37#include <linux/slab.h>
38#include <linux/io.h>
39#include <linux/of_i2c.h>
40#include <linux/of_gpio.h>
41#include <linux/pinctrl/consumer.h>
42
43#include <asm/irq.h>
44
45#include <linux/platform_data/i2c-s3c2410.h>
46
47
48
49#define S3C2410_IICCON 0x00
50#define S3C2410_IICSTAT 0x04
51#define S3C2410_IICADD 0x08
52#define S3C2410_IICDS 0x0C
53#define S3C2440_IICLC 0x10
54
55#define S3C2410_IICCON_ACKEN (1 << 7)
56#define S3C2410_IICCON_TXDIV_16 (0 << 6)
57#define S3C2410_IICCON_TXDIV_512 (1 << 6)
58#define S3C2410_IICCON_IRQEN (1 << 5)
59#define S3C2410_IICCON_IRQPEND (1 << 4)
60#define S3C2410_IICCON_SCALE(x) ((x) & 0xf)
61#define S3C2410_IICCON_SCALEMASK (0xf)
62
63#define S3C2410_IICSTAT_MASTER_RX (2 << 6)
64#define S3C2410_IICSTAT_MASTER_TX (3 << 6)
65#define S3C2410_IICSTAT_SLAVE_RX (0 << 6)
66#define S3C2410_IICSTAT_SLAVE_TX (1 << 6)
67#define S3C2410_IICSTAT_MODEMASK (3 << 6)
68
69#define S3C2410_IICSTAT_START (1 << 5)
70#define S3C2410_IICSTAT_BUSBUSY (1 << 5)
71#define S3C2410_IICSTAT_TXRXEN (1 << 4)
72#define S3C2410_IICSTAT_ARBITR (1 << 3)
73#define S3C2410_IICSTAT_ASSLAVE (1 << 2)
74#define S3C2410_IICSTAT_ADDR0 (1 << 1)
75#define S3C2410_IICSTAT_LASTBIT (1 << 0)
76
77#define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
78#define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
79#define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
80#define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
81#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
82
83#define S3C2410_IICLC_FILTER_ON (1 << 2)
84
85
86#define QUIRK_S3C2440 (1 << 0)
87#define QUIRK_HDMIPHY (1 << 1)
88#define QUIRK_NO_GPIO (1 << 2)
89
90
91#define S3C2410_IDLE_TIMEOUT 5000
92
93
94enum s3c24xx_i2c_state {
95 STATE_IDLE,
96 STATE_START,
97 STATE_READ,
98 STATE_WRITE,
99 STATE_STOP
100};
101
102struct s3c24xx_i2c {
103 wait_queue_head_t wait;
104 unsigned int quirks;
105 unsigned int suspended:1;
106
107 struct i2c_msg *msg;
108 unsigned int msg_num;
109 unsigned int msg_idx;
110 unsigned int msg_ptr;
111
112 unsigned int tx_setup;
113 unsigned int irq;
114
115 enum s3c24xx_i2c_state state;
116 unsigned long clkrate;
117
118 void __iomem *regs;
119 struct clk *clk;
120 struct device *dev;
121 struct i2c_adapter adap;
122
123 struct s3c2410_platform_i2c *pdata;
124 int gpios[2];
125 struct pinctrl *pctrl;
126#ifdef CONFIG_CPU_FREQ
127 struct notifier_block freq_transition;
128#endif
129};
130
131static struct platform_device_id s3c24xx_driver_ids[] = {
132 {
133 .name = "s3c2410-i2c",
134 .driver_data = 0,
135 }, {
136 .name = "s3c2440-i2c",
137 .driver_data = QUIRK_S3C2440,
138 }, {
139 .name = "s3c2440-hdmiphy-i2c",
140 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
141 }, { },
142};
143MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
144
145#ifdef CONFIG_OF
146static const struct of_device_id s3c24xx_i2c_match[] = {
147 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
148 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
149 { .compatible = "samsung,s3c2440-hdmiphy-i2c",
150 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
151 { .compatible = "samsung,exynos5440-i2c",
152 .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) },
153 {},
154};
155MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
156#endif
157
158
159
160
161
162
163static inline unsigned int s3c24xx_get_device_quirks(struct platform_device *pdev)
164{
165 if (pdev->dev.of_node) {
166 const struct of_device_id *match;
167 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
168 return (unsigned int)match->data;
169 }
170
171 return platform_get_device_id(pdev)->driver_data;
172}
173
174
175
176
177
178
179
180static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
181{
182 dev_dbg(i2c->dev, "master_complete %d\n", ret);
183
184 i2c->msg_ptr = 0;
185 i2c->msg = NULL;
186 i2c->msg_idx++;
187 i2c->msg_num = 0;
188 if (ret)
189 i2c->msg_idx = ret;
190
191 wake_up(&i2c->wait);
192}
193
194static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
195{
196 unsigned long tmp;
197
198 tmp = readl(i2c->regs + S3C2410_IICCON);
199 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
200}
201
202static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
203{
204 unsigned long tmp;
205
206 tmp = readl(i2c->regs + S3C2410_IICCON);
207 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
208}
209
210
211
212static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
213{
214 unsigned long tmp;
215
216 tmp = readl(i2c->regs + S3C2410_IICCON);
217 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
218}
219
220static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
221{
222 unsigned long tmp;
223
224 tmp = readl(i2c->regs + S3C2410_IICCON);
225 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
226}
227
228
229
230
231
232
233
234static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
235 struct i2c_msg *msg)
236{
237 unsigned int addr = (msg->addr & 0x7f) << 1;
238 unsigned long stat;
239 unsigned long iiccon;
240
241 stat = 0;
242 stat |= S3C2410_IICSTAT_TXRXEN;
243
244 if (msg->flags & I2C_M_RD) {
245 stat |= S3C2410_IICSTAT_MASTER_RX;
246 addr |= 1;
247 } else
248 stat |= S3C2410_IICSTAT_MASTER_TX;
249
250 if (msg->flags & I2C_M_REV_DIR_ADDR)
251 addr ^= 1;
252
253
254 s3c24xx_i2c_enable_ack(i2c);
255
256 iiccon = readl(i2c->regs + S3C2410_IICCON);
257 writel(stat, i2c->regs + S3C2410_IICSTAT);
258
259 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
260 writeb(addr, i2c->regs + S3C2410_IICDS);
261
262
263
264
265 ndelay(i2c->tx_setup);
266
267 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
268 writel(iiccon, i2c->regs + S3C2410_IICCON);
269
270 stat |= S3C2410_IICSTAT_START;
271 writel(stat, i2c->regs + S3C2410_IICSTAT);
272}
273
274static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
275{
276 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
277
278 dev_dbg(i2c->dev, "STOP\n");
279
280
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311
312
313
314 if (i2c->quirks & QUIRK_HDMIPHY) {
315
316 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
317 } else {
318
319 iicstat &= ~S3C2410_IICSTAT_START;
320 }
321 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
322
323 i2c->state = STATE_STOP;
324
325 s3c24xx_i2c_master_complete(i2c, ret);
326 s3c24xx_i2c_disable_irq(i2c);
327}
328
329
330
331
332
333
334
335
336
337static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
338{
339 return i2c->msg_idx >= (i2c->msg_num - 1);
340}
341
342
343
344
345
346
347static inline int is_msglast(struct s3c24xx_i2c *i2c)
348{
349
350
351
352 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
353 return 0;
354
355 return i2c->msg_ptr == i2c->msg->len-1;
356}
357
358
359
360
361
362
363static inline int is_msgend(struct s3c24xx_i2c *i2c)
364{
365 return i2c->msg_ptr >= i2c->msg->len;
366}
367
368
369
370
371
372
373static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
374{
375 unsigned long tmp;
376 unsigned char byte;
377 int ret = 0;
378
379 switch (i2c->state) {
380
381 case STATE_IDLE:
382 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
383 goto out;
384
385 case STATE_STOP:
386 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
387 s3c24xx_i2c_disable_irq(i2c);
388 goto out_ack;
389
390 case STATE_START:
391
392
393
394
395 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
396 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
397
398
399 dev_dbg(i2c->dev, "ack was not received\n");
400 s3c24xx_i2c_stop(i2c, -ENXIO);
401 goto out_ack;
402 }
403
404 if (i2c->msg->flags & I2C_M_RD)
405 i2c->state = STATE_READ;
406 else
407 i2c->state = STATE_WRITE;
408
409
410
411
412 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
413 s3c24xx_i2c_stop(i2c, 0);
414 goto out_ack;
415 }
416
417 if (i2c->state == STATE_READ)
418 goto prepare_read;
419
420
421
422
423 case STATE_WRITE:
424
425
426
427
428 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
429 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
430 dev_dbg(i2c->dev, "WRITE: No Ack\n");
431
432 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
433 goto out_ack;
434 }
435 }
436
437 retry_write:
438
439 if (!is_msgend(i2c)) {
440 byte = i2c->msg->buf[i2c->msg_ptr++];
441 writeb(byte, i2c->regs + S3C2410_IICDS);
442
443
444
445
446
447
448
449 ndelay(i2c->tx_setup);
450
451 } else if (!is_lastmsg(i2c)) {
452
453
454 dev_dbg(i2c->dev, "WRITE: Next Message\n");
455
456 i2c->msg_ptr = 0;
457 i2c->msg_idx++;
458 i2c->msg++;
459
460
461 if (i2c->msg->flags & I2C_M_NOSTART) {
462
463 if (i2c->msg->flags & I2C_M_RD) {
464
465
466
467
468 s3c24xx_i2c_stop(i2c, -EINVAL);
469 }
470
471 goto retry_write;
472 } else {
473
474 s3c24xx_i2c_message_start(i2c, i2c->msg);
475 i2c->state = STATE_START;
476 }
477
478 } else {
479
480
481 s3c24xx_i2c_stop(i2c, 0);
482 }
483 break;
484
485 case STATE_READ:
486
487
488
489
490
491 byte = readb(i2c->regs + S3C2410_IICDS);
492 i2c->msg->buf[i2c->msg_ptr++] = byte;
493
494
495 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
496 i2c->msg->len += byte;
497 prepare_read:
498 if (is_msglast(i2c)) {
499
500
501 if (is_lastmsg(i2c))
502 s3c24xx_i2c_disable_ack(i2c);
503
504 } else if (is_msgend(i2c)) {
505
506
507
508 if (is_lastmsg(i2c)) {
509
510 dev_dbg(i2c->dev, "READ: Send Stop\n");
511
512 s3c24xx_i2c_stop(i2c, 0);
513 } else {
514
515 dev_dbg(i2c->dev, "READ: Next Transfer\n");
516
517 i2c->msg_ptr = 0;
518 i2c->msg_idx++;
519 i2c->msg++;
520 }
521 }
522
523 break;
524 }
525
526
527
528 out_ack:
529 tmp = readl(i2c->regs + S3C2410_IICCON);
530 tmp &= ~S3C2410_IICCON_IRQPEND;
531 writel(tmp, i2c->regs + S3C2410_IICCON);
532 out:
533 return ret;
534}
535
536
537
538
539
540
541static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
542{
543 struct s3c24xx_i2c *i2c = dev_id;
544 unsigned long status;
545 unsigned long tmp;
546
547 status = readl(i2c->regs + S3C2410_IICSTAT);
548
549 if (status & S3C2410_IICSTAT_ARBITR) {
550
551 dev_err(i2c->dev, "deal with arbitration loss\n");
552 }
553
554 if (i2c->state == STATE_IDLE) {
555 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
556
557 tmp = readl(i2c->regs + S3C2410_IICCON);
558 tmp &= ~S3C2410_IICCON_IRQPEND;
559 writel(tmp, i2c->regs + S3C2410_IICCON);
560 goto out;
561 }
562
563
564
565
566 i2c_s3c_irq_nextbyte(i2c, status);
567
568 out:
569 return IRQ_HANDLED;
570}
571
572
573
574
575
576
577
578static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
579{
580 unsigned long iicstat;
581 int timeout = 400;
582
583 while (timeout-- > 0) {
584 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
585
586 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
587 return 0;
588
589 msleep(1);
590 }
591
592 return -ETIMEDOUT;
593}
594
595
596
597
598
599
600static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
601{
602 unsigned long iicstat;
603 ktime_t start, now;
604 unsigned long delay;
605 int spins;
606
607
608
609 dev_dbg(i2c->dev, "waiting for bus idle\n");
610
611 start = now = ktime_get();
612
613
614
615
616
617
618
619
620
621 spins = 3;
622 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
623 while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
624 cpu_relax();
625 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
626 }
627
628
629
630
631
632
633
634
635 delay = 1;
636 while ((iicstat & S3C2410_IICSTAT_START) &&
637 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
638 usleep_range(delay, 2 * delay);
639 if (delay < S3C2410_IDLE_TIMEOUT / 10)
640 delay <<= 1;
641 now = ktime_get();
642 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
643 }
644
645 if (iicstat & S3C2410_IICSTAT_START)
646 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
647}
648
649
650
651
652
653
654static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
655 struct i2c_msg *msgs, int num)
656{
657 unsigned long timeout;
658 int ret;
659
660 if (i2c->suspended)
661 return -EIO;
662
663 ret = s3c24xx_i2c_set_master(i2c);
664 if (ret != 0) {
665 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
666 ret = -EAGAIN;
667 goto out;
668 }
669
670 i2c->msg = msgs;
671 i2c->msg_num = num;
672 i2c->msg_ptr = 0;
673 i2c->msg_idx = 0;
674 i2c->state = STATE_START;
675
676 s3c24xx_i2c_enable_irq(i2c);
677 s3c24xx_i2c_message_start(i2c, msgs);
678
679 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
680
681 ret = i2c->msg_idx;
682
683
684
685
686 if (timeout == 0)
687 dev_dbg(i2c->dev, "timeout\n");
688 else if (ret != num)
689 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
690
691
692 if (i2c->quirks & QUIRK_HDMIPHY)
693 goto out;
694
695 s3c24xx_i2c_wait_idle(i2c);
696
697 out:
698 return ret;
699}
700
701
702
703
704
705
706
707static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
708 struct i2c_msg *msgs, int num)
709{
710 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
711 int retry;
712 int ret;
713
714 pm_runtime_get_sync(&adap->dev);
715 clk_prepare_enable(i2c->clk);
716
717 for (retry = 0; retry < adap->retries; retry++) {
718
719 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
720
721 if (ret != -EAGAIN) {
722 clk_disable_unprepare(i2c->clk);
723 pm_runtime_put(&adap->dev);
724 return ret;
725 }
726
727 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
728
729 udelay(100);
730 }
731
732 clk_disable_unprepare(i2c->clk);
733 pm_runtime_put(&adap->dev);
734 return -EREMOTEIO;
735}
736
737
738static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
739{
740 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
741 I2C_FUNC_PROTOCOL_MANGLING;
742}
743
744
745
746static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
747 .master_xfer = s3c24xx_i2c_xfer,
748 .functionality = s3c24xx_i2c_func,
749};
750
751
752
753
754
755
756static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
757 unsigned int *div1, unsigned int *divs)
758{
759 unsigned int calc_divs = clkin / wanted;
760 unsigned int calc_div1;
761
762 if (calc_divs > (16*16))
763 calc_div1 = 512;
764 else
765 calc_div1 = 16;
766
767 calc_divs += calc_div1-1;
768 calc_divs /= calc_div1;
769
770 if (calc_divs == 0)
771 calc_divs = 1;
772 if (calc_divs > 17)
773 calc_divs = 17;
774
775 *divs = calc_divs;
776 *div1 = calc_div1;
777
778 return clkin / (calc_divs * calc_div1);
779}
780
781
782
783
784
785
786
787
788static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
789{
790 struct s3c2410_platform_i2c *pdata = i2c->pdata;
791 unsigned long clkin = clk_get_rate(i2c->clk);
792 unsigned int divs, div1;
793 unsigned long target_frequency;
794 u32 iiccon;
795 int freq;
796
797 i2c->clkrate = clkin;
798 clkin /= 1000;
799
800 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
801
802 target_frequency = pdata->frequency ? pdata->frequency : 100000;
803
804 target_frequency /= 1000;
805
806 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
807
808 if (freq > target_frequency) {
809 dev_err(i2c->dev,
810 "Unable to achieve desired frequency %luKHz." \
811 " Lowest achievable %dKHz\n", target_frequency, freq);
812 return -EINVAL;
813 }
814
815 *got = freq;
816
817 iiccon = readl(i2c->regs + S3C2410_IICCON);
818 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
819 iiccon |= (divs-1);
820
821 if (div1 == 512)
822 iiccon |= S3C2410_IICCON_TXDIV_512;
823
824 writel(iiccon, i2c->regs + S3C2410_IICCON);
825
826 if (i2c->quirks & QUIRK_S3C2440) {
827 unsigned long sda_delay;
828
829 if (pdata->sda_delay) {
830 sda_delay = clkin * pdata->sda_delay;
831 sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
832 sda_delay = DIV_ROUND_UP(sda_delay, 5);
833 if (sda_delay > 3)
834 sda_delay = 3;
835 sda_delay |= S3C2410_IICLC_FILTER_ON;
836 } else
837 sda_delay = 0;
838
839 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
840 writel(sda_delay, i2c->regs + S3C2440_IICLC);
841 }
842
843 return 0;
844}
845
846#ifdef CONFIG_CPU_FREQ
847
848#define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
849
850static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
851 unsigned long val, void *data)
852{
853 struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
854 unsigned int got;
855 int delta_f;
856 int ret;
857
858 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
859
860
861
862
863
864
865 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
866 (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
867 i2c_lock_adapter(&i2c->adap);
868 ret = s3c24xx_i2c_clockrate(i2c, &got);
869 i2c_unlock_adapter(&i2c->adap);
870
871 if (ret < 0)
872 dev_err(i2c->dev, "cannot find frequency\n");
873 else
874 dev_info(i2c->dev, "setting freq %d\n", got);
875 }
876
877 return 0;
878}
879
880static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
881{
882 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
883
884 return cpufreq_register_notifier(&i2c->freq_transition,
885 CPUFREQ_TRANSITION_NOTIFIER);
886}
887
888static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
889{
890 cpufreq_unregister_notifier(&i2c->freq_transition,
891 CPUFREQ_TRANSITION_NOTIFIER);
892}
893
894#else
895static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
896{
897 return 0;
898}
899
900static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
901{
902}
903#endif
904
905#ifdef CONFIG_OF
906static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
907{
908 int idx, gpio, ret;
909
910 if (i2c->quirks & QUIRK_NO_GPIO)
911 return 0;
912
913 for (idx = 0; idx < 2; idx++) {
914 gpio = of_get_gpio(i2c->dev->of_node, idx);
915 if (!gpio_is_valid(gpio)) {
916 dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
917 goto free_gpio;
918 }
919 i2c->gpios[idx] = gpio;
920
921 ret = gpio_request(gpio, "i2c-bus");
922 if (ret) {
923 dev_err(i2c->dev, "gpio [%d] request failed\n", gpio);
924 goto free_gpio;
925 }
926 }
927 return 0;
928
929free_gpio:
930 while (--idx >= 0)
931 gpio_free(i2c->gpios[idx]);
932 return -EINVAL;
933}
934
935static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
936{
937 unsigned int idx;
938
939 if (i2c->quirks & QUIRK_NO_GPIO)
940 return;
941
942 for (idx = 0; idx < 2; idx++)
943 gpio_free(i2c->gpios[idx]);
944}
945#else
946static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
947{
948 return 0;
949}
950
951static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
952{
953}
954#endif
955
956
957
958
959
960
961static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
962{
963 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
964 struct s3c2410_platform_i2c *pdata;
965 unsigned int freq;
966
967
968
969 pdata = i2c->pdata;
970
971
972
973 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
974
975 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
976
977 writel(iicon, i2c->regs + S3C2410_IICCON);
978
979
980
981 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
982 writel(0, i2c->regs + S3C2410_IICCON);
983 dev_err(i2c->dev, "cannot meet bus frequency required\n");
984 return -EINVAL;
985 }
986
987
988
989 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
990 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
991
992 return 0;
993}
994
995#ifdef CONFIG_OF
996
997
998
999
1000
1001static void
1002s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1003{
1004 struct s3c2410_platform_i2c *pdata = i2c->pdata;
1005
1006 if (!np)
1007 return;
1008
1009 pdata->bus_num = -1;
1010 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1011 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1012 of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1013 (u32 *)&pdata->frequency);
1014}
1015#else
1016static void
1017s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1018{
1019 return;
1020}
1021#endif
1022
1023
1024
1025
1026
1027
1028static int s3c24xx_i2c_probe(struct platform_device *pdev)
1029{
1030 struct s3c24xx_i2c *i2c;
1031 struct s3c2410_platform_i2c *pdata = NULL;
1032 struct resource *res;
1033 int ret;
1034
1035 if (!pdev->dev.of_node) {
1036 pdata = pdev->dev.platform_data;
1037 if (!pdata) {
1038 dev_err(&pdev->dev, "no platform data\n");
1039 return -EINVAL;
1040 }
1041 }
1042
1043 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1044 if (!i2c) {
1045 dev_err(&pdev->dev, "no memory for state\n");
1046 return -ENOMEM;
1047 }
1048
1049 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1050 if (!i2c->pdata) {
1051 dev_err(&pdev->dev, "no memory for platform data\n");
1052 return -ENOMEM;
1053 }
1054
1055 i2c->quirks = s3c24xx_get_device_quirks(pdev);
1056 if (pdata)
1057 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1058 else
1059 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1060
1061 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1062 i2c->adap.owner = THIS_MODULE;
1063 i2c->adap.algo = &s3c24xx_i2c_algorithm;
1064 i2c->adap.retries = 2;
1065 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1066 i2c->tx_setup = 50;
1067
1068 init_waitqueue_head(&i2c->wait);
1069
1070
1071
1072 i2c->dev = &pdev->dev;
1073 i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1074 if (IS_ERR(i2c->clk)) {
1075 dev_err(&pdev->dev, "cannot get clock\n");
1076 return -ENOENT;
1077 }
1078
1079 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1080
1081
1082
1083
1084 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1085 i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1086
1087 if (IS_ERR(i2c->regs))
1088 return PTR_ERR(i2c->regs);
1089
1090 dev_dbg(&pdev->dev, "registers %p (%p)\n",
1091 i2c->regs, res);
1092
1093
1094
1095 i2c->adap.algo_data = i2c;
1096 i2c->adap.dev.parent = &pdev->dev;
1097
1098 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1099
1100
1101
1102 if (i2c->pdata->cfg_gpio) {
1103 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1104 } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) {
1105 return -EINVAL;
1106 }
1107
1108
1109
1110 clk_prepare_enable(i2c->clk);
1111 ret = s3c24xx_i2c_init(i2c);
1112 clk_disable_unprepare(i2c->clk);
1113 if (ret != 0) {
1114 dev_err(&pdev->dev, "I2C controller init failed\n");
1115 return ret;
1116 }
1117
1118
1119
1120
1121 i2c->irq = ret = platform_get_irq(pdev, 0);
1122 if (ret <= 0) {
1123 dev_err(&pdev->dev, "cannot find IRQ\n");
1124 return ret;
1125 }
1126
1127 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0,
1128 dev_name(&pdev->dev), i2c);
1129
1130 if (ret != 0) {
1131 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1132 return ret;
1133 }
1134
1135 ret = s3c24xx_i2c_register_cpufreq(i2c);
1136 if (ret < 0) {
1137 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1138 return ret;
1139 }
1140
1141
1142
1143
1144
1145
1146
1147 i2c->adap.nr = i2c->pdata->bus_num;
1148 i2c->adap.dev.of_node = pdev->dev.of_node;
1149
1150 ret = i2c_add_numbered_adapter(&i2c->adap);
1151 if (ret < 0) {
1152 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
1153 s3c24xx_i2c_deregister_cpufreq(i2c);
1154 return ret;
1155 }
1156
1157 of_i2c_register_devices(&i2c->adap);
1158 platform_set_drvdata(pdev, i2c);
1159
1160 pm_runtime_enable(&pdev->dev);
1161 pm_runtime_enable(&i2c->adap.dev);
1162
1163 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1164 return 0;
1165}
1166
1167
1168
1169
1170
1171
1172static int s3c24xx_i2c_remove(struct platform_device *pdev)
1173{
1174 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1175
1176 pm_runtime_disable(&i2c->adap.dev);
1177 pm_runtime_disable(&pdev->dev);
1178
1179 s3c24xx_i2c_deregister_cpufreq(i2c);
1180
1181 i2c_del_adapter(&i2c->adap);
1182
1183 clk_disable_unprepare(i2c->clk);
1184
1185 if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1186 s3c24xx_i2c_dt_gpio_free(i2c);
1187
1188 return 0;
1189}
1190
1191#ifdef CONFIG_PM_SLEEP
1192static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1193{
1194 struct platform_device *pdev = to_platform_device(dev);
1195 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1196
1197 i2c->suspended = 1;
1198
1199 return 0;
1200}
1201
1202static int s3c24xx_i2c_resume(struct device *dev)
1203{
1204 struct platform_device *pdev = to_platform_device(dev);
1205 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1206
1207 i2c->suspended = 0;
1208 clk_prepare_enable(i2c->clk);
1209 s3c24xx_i2c_init(i2c);
1210 clk_disable_unprepare(i2c->clk);
1211
1212 return 0;
1213}
1214#endif
1215
1216#ifdef CONFIG_PM
1217static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1218#ifdef CONFIG_PM_SLEEP
1219 .suspend_noirq = s3c24xx_i2c_suspend_noirq,
1220 .resume = s3c24xx_i2c_resume,
1221#endif
1222};
1223
1224#define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1225#else
1226#define S3C24XX_DEV_PM_OPS NULL
1227#endif
1228
1229
1230
1231static struct platform_driver s3c24xx_i2c_driver = {
1232 .probe = s3c24xx_i2c_probe,
1233 .remove = s3c24xx_i2c_remove,
1234 .id_table = s3c24xx_driver_ids,
1235 .driver = {
1236 .owner = THIS_MODULE,
1237 .name = "s3c-i2c",
1238 .pm = S3C24XX_DEV_PM_OPS,
1239 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1240 },
1241};
1242
1243static int __init i2c_adap_s3c_init(void)
1244{
1245 return platform_driver_register(&s3c24xx_i2c_driver);
1246}
1247subsys_initcall(i2c_adap_s3c_init);
1248
1249static void __exit i2c_adap_s3c_exit(void)
1250{
1251 platform_driver_unregister(&s3c24xx_i2c_driver);
1252}
1253module_exit(i2c_adap_s3c_exit);
1254
1255MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1256MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1257MODULE_LICENSE("GPL");
1258