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9#include <linux/interrupt.h>
10#include <linux/irq.h>
11#include <linux/delay.h>
12#include <linux/mutex.h>
13#include <linux/device.h>
14#include <linux/kernel.h>
15#include <linux/spi/spi.h>
16#include <linux/slab.h>
17#include <linux/sysfs.h>
18#include <linux/list.h>
19#include <linux/module.h>
20
21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
23
24#define ADXRS450_STARTUP_DELAY 50
25
26
27#define ADXRS450_SENSOR_DATA (0x20 << 24)
28#define ADXRS450_WRITE_DATA (0x40 << 24)
29#define ADXRS450_READ_DATA (0x80 << 24)
30
31#define ADXRS450_RATE1 0x00
32#define ADXRS450_TEMP1 0x02
33#define ADXRS450_LOCST1 0x04
34#define ADXRS450_HICST1 0x06
35#define ADXRS450_QUAD1 0x08
36#define ADXRS450_FAULT1 0x0A
37#define ADXRS450_PID1 0x0C
38#define ADXRS450_SNH 0x0E
39#define ADXRS450_SNL 0x10
40#define ADXRS450_DNC1 0x12
41
42#define ADXRS450_P 0x01
43#define ADXRS450_CHK 0x02
44#define ADXRS450_CST 0x04
45#define ADXRS450_PWR 0x08
46#define ADXRS450_POR 0x10
47#define ADXRS450_NVM 0x20
48#define ADXRS450_Q 0x40
49#define ADXRS450_PLL 0x80
50#define ADXRS450_UV 0x100
51#define ADXRS450_OV 0x200
52#define ADXRS450_AMP 0x400
53#define ADXRS450_FAIL 0x800
54
55#define ADXRS450_WRERR_MASK (0x7 << 29)
56
57#define ADXRS450_MAX_RX 4
58#define ADXRS450_MAX_TX 4
59
60#define ADXRS450_GET_ST(a) ((a >> 26) & 0x3)
61
62enum {
63 ID_ADXRS450,
64 ID_ADXRS453,
65};
66
67
68
69
70
71
72
73
74struct adxrs450_state {
75 struct spi_device *us;
76 struct mutex buf_lock;
77 __be32 tx ____cacheline_aligned;
78 __be32 rx;
79
80};
81
82
83
84
85
86
87
88
89static int adxrs450_spi_read_reg_16(struct iio_dev *indio_dev,
90 u8 reg_address,
91 u16 *val)
92{
93 struct spi_message msg;
94 struct adxrs450_state *st = iio_priv(indio_dev);
95 u32 tx;
96 int ret;
97 struct spi_transfer xfers[] = {
98 {
99 .tx_buf = &st->tx,
100 .bits_per_word = 8,
101 .len = sizeof(st->tx),
102 .cs_change = 1,
103 }, {
104 .rx_buf = &st->rx,
105 .bits_per_word = 8,
106 .len = sizeof(st->rx),
107 },
108 };
109
110 mutex_lock(&st->buf_lock);
111 tx = ADXRS450_READ_DATA | (reg_address << 17);
112
113 if (!(hweight32(tx) & 1))
114 tx |= ADXRS450_P;
115
116 st->tx = cpu_to_be32(tx);
117 spi_message_init(&msg);
118 spi_message_add_tail(&xfers[0], &msg);
119 spi_message_add_tail(&xfers[1], &msg);
120 ret = spi_sync(st->us, &msg);
121 if (ret) {
122 dev_err(&st->us->dev, "problem while reading 16 bit register 0x%02x\n",
123 reg_address);
124 goto error_ret;
125 }
126
127 *val = (be32_to_cpu(st->rx) >> 5) & 0xFFFF;
128
129error_ret:
130 mutex_unlock(&st->buf_lock);
131 return ret;
132}
133
134
135
136
137
138
139
140
141static int adxrs450_spi_write_reg_16(struct iio_dev *indio_dev,
142 u8 reg_address,
143 u16 val)
144{
145 struct adxrs450_state *st = iio_priv(indio_dev);
146 u32 tx;
147 int ret;
148
149 mutex_lock(&st->buf_lock);
150 tx = ADXRS450_WRITE_DATA | (reg_address << 17) | (val << 1);
151
152 if (!(hweight32(tx) & 1))
153 tx |= ADXRS450_P;
154
155 st->tx = cpu_to_be32(tx);
156 ret = spi_write(st->us, &st->tx, sizeof(st->tx));
157 if (ret)
158 dev_err(&st->us->dev, "problem while writing 16 bit register 0x%02x\n",
159 reg_address);
160 usleep_range(100, 1000);
161 mutex_unlock(&st->buf_lock);
162 return ret;
163}
164
165
166
167
168
169
170static int adxrs450_spi_sensor_data(struct iio_dev *indio_dev, s16 *val)
171{
172 struct spi_message msg;
173 struct adxrs450_state *st = iio_priv(indio_dev);
174 int ret;
175 struct spi_transfer xfers[] = {
176 {
177 .tx_buf = &st->tx,
178 .bits_per_word = 8,
179 .len = sizeof(st->tx),
180 .cs_change = 1,
181 }, {
182 .rx_buf = &st->rx,
183 .bits_per_word = 8,
184 .len = sizeof(st->rx),
185 },
186 };
187
188 mutex_lock(&st->buf_lock);
189 st->tx = cpu_to_be32(ADXRS450_SENSOR_DATA);
190
191 spi_message_init(&msg);
192 spi_message_add_tail(&xfers[0], &msg);
193 spi_message_add_tail(&xfers[1], &msg);
194 ret = spi_sync(st->us, &msg);
195 if (ret) {
196 dev_err(&st->us->dev, "Problem while reading sensor data\n");
197 goto error_ret;
198 }
199
200 *val = (be32_to_cpu(st->rx) >> 10) & 0xFFFF;
201
202error_ret:
203 mutex_unlock(&st->buf_lock);
204 return ret;
205}
206
207
208
209
210
211
212
213static int adxrs450_spi_initial(struct adxrs450_state *st,
214 u32 *val, char chk)
215{
216 int ret;
217 u32 tx;
218 struct spi_transfer xfers = {
219 .tx_buf = &st->tx,
220 .rx_buf = &st->rx,
221 .bits_per_word = 8,
222 .len = sizeof(st->tx),
223 };
224
225 mutex_lock(&st->buf_lock);
226 tx = ADXRS450_SENSOR_DATA;
227 if (chk)
228 tx |= (ADXRS450_CHK | ADXRS450_P);
229 st->tx = cpu_to_be32(tx);
230 ret = spi_sync_transfer(st->us, &xfers, 1);
231 if (ret) {
232 dev_err(&st->us->dev, "Problem while reading initializing data\n");
233 goto error_ret;
234 }
235
236 *val = be32_to_cpu(st->rx);
237
238error_ret:
239 mutex_unlock(&st->buf_lock);
240 return ret;
241}
242
243
244static int adxrs450_initial_setup(struct iio_dev *indio_dev)
245{
246 u32 t;
247 u16 data;
248 int ret;
249 struct adxrs450_state *st = iio_priv(indio_dev);
250
251 msleep(ADXRS450_STARTUP_DELAY*2);
252 ret = adxrs450_spi_initial(st, &t, 1);
253 if (ret)
254 return ret;
255 if (t != 0x01)
256 dev_warn(&st->us->dev, "The initial power on response is not correct! Restart without reset?\n");
257
258 msleep(ADXRS450_STARTUP_DELAY);
259 ret = adxrs450_spi_initial(st, &t, 0);
260 if (ret)
261 return ret;
262
263 msleep(ADXRS450_STARTUP_DELAY);
264 ret = adxrs450_spi_initial(st, &t, 0);
265 if (ret)
266 return ret;
267 if (((t & 0xff) | 0x01) != 0xff || ADXRS450_GET_ST(t) != 2) {
268 dev_err(&st->us->dev, "The second response is not correct!\n");
269 return -EIO;
270
271 }
272 ret = adxrs450_spi_initial(st, &t, 0);
273 if (ret)
274 return ret;
275 if (((t & 0xff) | 0x01) != 0xff || ADXRS450_GET_ST(t) != 2) {
276 dev_err(&st->us->dev, "The third response is not correct!\n");
277 return -EIO;
278
279 }
280 ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_FAULT1, &data);
281 if (ret)
282 return ret;
283 if (data & 0x0fff) {
284 dev_err(&st->us->dev, "The device is not in normal status!\n");
285 return -EINVAL;
286 }
287
288 return 0;
289}
290
291static int adxrs450_write_raw(struct iio_dev *indio_dev,
292 struct iio_chan_spec const *chan,
293 int val,
294 int val2,
295 long mask)
296{
297 int ret;
298 switch (mask) {
299 case IIO_CHAN_INFO_CALIBBIAS:
300 if (val < -0x400 || val >= 0x400)
301 return -EINVAL;
302 ret = adxrs450_spi_write_reg_16(indio_dev,
303 ADXRS450_DNC1, val);
304 break;
305 default:
306 ret = -EINVAL;
307 break;
308 }
309 return ret;
310}
311
312static int adxrs450_read_raw(struct iio_dev *indio_dev,
313 struct iio_chan_spec const *chan,
314 int *val,
315 int *val2,
316 long mask)
317{
318 int ret;
319 s16 t;
320
321 switch (mask) {
322 case IIO_CHAN_INFO_RAW:
323 switch (chan->type) {
324 case IIO_ANGL_VEL:
325 ret = adxrs450_spi_sensor_data(indio_dev, &t);
326 if (ret)
327 break;
328 *val = t;
329 ret = IIO_VAL_INT;
330 break;
331 case IIO_TEMP:
332 ret = adxrs450_spi_read_reg_16(indio_dev,
333 ADXRS450_TEMP1, &t);
334 if (ret)
335 break;
336 *val = (t >> 6) + 225;
337 ret = IIO_VAL_INT;
338 break;
339 default:
340 ret = -EINVAL;
341 break;
342 }
343 break;
344 case IIO_CHAN_INFO_SCALE:
345 switch (chan->type) {
346 case IIO_ANGL_VEL:
347 *val = 0;
348 *val2 = 218166;
349 return IIO_VAL_INT_PLUS_NANO;
350 case IIO_TEMP:
351 *val = 200;
352 *val2 = 0;
353 return IIO_VAL_INT;
354 default:
355 return -EINVAL;
356 }
357 break;
358 case IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW:
359 ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_QUAD1, &t);
360 if (ret)
361 break;
362 *val = t;
363 ret = IIO_VAL_INT;
364 break;
365 case IIO_CHAN_INFO_CALIBBIAS:
366 ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_DNC1, &t);
367 if (ret)
368 break;
369 *val = sign_extend32(t, 9);
370 ret = IIO_VAL_INT;
371 break;
372 default:
373 ret = -EINVAL;
374 break;
375 }
376
377 return ret;
378}
379
380static const struct iio_chan_spec adxrs450_channels[2][2] = {
381 [ID_ADXRS450] = {
382 {
383 .type = IIO_ANGL_VEL,
384 .modified = 1,
385 .channel2 = IIO_MOD_Z,
386 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
387 BIT(IIO_CHAN_INFO_CALIBBIAS) |
388 BIT(IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW) |
389 BIT(IIO_CHAN_INFO_SCALE),
390 }, {
391 .type = IIO_TEMP,
392 .indexed = 1,
393 .channel = 0,
394 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
395 BIT(IIO_CHAN_INFO_SCALE),
396 }
397 },
398 [ID_ADXRS453] = {
399 {
400 .type = IIO_ANGL_VEL,
401 .modified = 1,
402 .channel2 = IIO_MOD_Z,
403 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
404 BIT(IIO_CHAN_INFO_SCALE) |
405 BIT(IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW),
406 }, {
407 .type = IIO_TEMP,
408 .indexed = 1,
409 .channel = 0,
410 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
411 BIT(IIO_CHAN_INFO_SCALE),
412 }
413 },
414};
415
416static const struct iio_info adxrs450_info = {
417 .driver_module = THIS_MODULE,
418 .read_raw = &adxrs450_read_raw,
419 .write_raw = &adxrs450_write_raw,
420};
421
422static int adxrs450_probe(struct spi_device *spi)
423{
424 int ret;
425 struct adxrs450_state *st;
426 struct iio_dev *indio_dev;
427
428
429 indio_dev = iio_device_alloc(sizeof(*st));
430 if (indio_dev == NULL) {
431 ret = -ENOMEM;
432 goto error_ret;
433 }
434 st = iio_priv(indio_dev);
435 st->us = spi;
436 mutex_init(&st->buf_lock);
437
438 spi_set_drvdata(spi, indio_dev);
439
440 indio_dev->dev.parent = &spi->dev;
441 indio_dev->info = &adxrs450_info;
442 indio_dev->modes = INDIO_DIRECT_MODE;
443 indio_dev->channels =
444 adxrs450_channels[spi_get_device_id(spi)->driver_data];
445 indio_dev->num_channels = ARRAY_SIZE(adxrs450_channels);
446 indio_dev->name = spi->dev.driver->name;
447
448 ret = iio_device_register(indio_dev);
449 if (ret)
450 goto error_free_dev;
451
452
453 ret = adxrs450_initial_setup(indio_dev);
454 if (ret)
455 goto error_initial;
456 return 0;
457error_initial:
458 iio_device_unregister(indio_dev);
459error_free_dev:
460 iio_device_free(indio_dev);
461
462error_ret:
463 return ret;
464}
465
466static int adxrs450_remove(struct spi_device *spi)
467{
468 iio_device_unregister(spi_get_drvdata(spi));
469 iio_device_free(spi_get_drvdata(spi));
470
471 return 0;
472}
473
474static const struct spi_device_id adxrs450_id[] = {
475 {"adxrs450", ID_ADXRS450},
476 {"adxrs453", ID_ADXRS453},
477 {}
478};
479MODULE_DEVICE_TABLE(spi, adxrs450_id);
480
481static struct spi_driver adxrs450_driver = {
482 .driver = {
483 .name = "adxrs450",
484 .owner = THIS_MODULE,
485 },
486 .probe = adxrs450_probe,
487 .remove = adxrs450_remove,
488 .id_table = adxrs450_id,
489};
490module_spi_driver(adxrs450_driver);
491
492MODULE_AUTHOR("Cliff Cai <cliff.cai@xxxxxxxxxx>");
493MODULE_DESCRIPTION("Analog Devices ADXRS450/ADXRS453 Gyroscope SPI driver");
494MODULE_LICENSE("GPL v2");
495
