1#ifndef _QIB_KERNEL_H
2#define _QIB_KERNEL_H
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42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/dma-mapping.h>
45#include <linux/mutex.h>
46#include <linux/list.h>
47#include <linux/scatterlist.h>
48#include <linux/slab.h>
49#include <linux/io.h>
50#include <linux/fs.h>
51#include <linux/completion.h>
52#include <linux/kref.h>
53#include <linux/sched.h>
54
55#include "qib_common.h"
56#include "qib_verbs.h"
57
58
59#define QIB_CHIP_VERS_MAJ 2U
60
61
62#define QIB_CHIP_VERS_MIN 0U
63
64
65#define QIB_OUI 0x001175
66#define QIB_OUI_LSB 40
67
68
69
70
71
72
73
74
75
76struct qlogic_ib_stats {
77 __u64 sps_ints;
78 __u64 sps_errints;
79 __u64 sps_txerrs;
80 __u64 sps_rcverrs;
81 __u64 sps_hwerrs;
82 __u64 sps_nopiobufs;
83 __u64 sps_ctxts;
84 __u64 sps_lenerrs;
85 __u64 sps_buffull;
86 __u64 sps_hdrfull;
87};
88
89extern struct qlogic_ib_stats qib_stats;
90extern const struct pci_error_handlers qib_pci_err_handler;
91extern struct pci_driver qib_driver;
92
93#define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ
94
95
96
97
98
99
100#define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000)
101
102
103
104
105
106
107
108#define QIB_EEP_LOG_CNT (4)
109struct qib_eep_log_mask {
110 u64 errs_to_log;
111 u64 hwerrs_to_log;
112};
113
114
115
116
117struct qib_ctxtdata {
118 void **rcvegrbuf;
119 dma_addr_t *rcvegrbuf_phys;
120
121 void *rcvhdrq;
122
123 void *rcvhdrtail_kvaddr;
124
125
126
127
128 void *tid_pg_list;
129
130
131
132
133
134 unsigned long *user_event_mask;
135
136 wait_queue_head_t wait;
137
138
139
140
141 dma_addr_t rcvegr_phys;
142
143 dma_addr_t rcvhdrq_phys;
144 dma_addr_t rcvhdrqtailaddr_phys;
145
146
147
148
149
150 int cnt;
151
152
153
154
155
156 unsigned ctxt;
157
158 u16 subctxt_cnt;
159
160 u16 subctxt_id;
161
162 u16 rcvegrcnt;
163
164 u16 rcvegr_tid_base;
165
166 u32 piocnt;
167
168 u32 pio_base;
169
170 u32 piobufs;
171
172 u32 rcvegrbuf_chunks;
173
174 u16 rcvegrbufs_perchunk;
175
176 u16 rcvegrbufs_perchunk_shift;
177
178 size_t rcvegrbuf_size;
179
180 size_t rcvhdrq_size;
181
182 unsigned long flag;
183
184 u32 tidcursor;
185
186 u32 rcvwait_to;
187
188 u32 piowait_to;
189
190 u32 rcvnowait;
191
192 u32 pionowait;
193
194 u32 urgent;
195
196 u32 urgent_poll;
197
198 pid_t pid;
199 pid_t subpid[QLOGIC_IB_MAX_SUBCTXT];
200
201 char comm[16];
202
203 u16 pkeys[4];
204
205 struct qib_devdata *dd;
206
207 struct qib_pportdata *ppd;
208
209 void *subctxt_uregbase;
210
211 void *subctxt_rcvegrbuf;
212
213 void *subctxt_rcvhdr_base;
214
215 u32 userversion;
216
217 u32 active_slaves;
218
219 u16 poll_type;
220
221 u8 seq_cnt;
222 u8 redirect_seq_cnt;
223
224 u32 head;
225 u32 pkt_count;
226
227 struct qib_qp *lookaside_qp;
228 u32 lookaside_qpn;
229
230 struct list_head qp_wait_list;
231};
232
233struct qib_sge_state;
234
235struct qib_sdma_txreq {
236 int flags;
237 int sg_count;
238 dma_addr_t addr;
239 void (*callback)(struct qib_sdma_txreq *, int);
240 u16 start_idx;
241 u16 next_descq_idx;
242 struct list_head list;
243};
244
245struct qib_sdma_desc {
246 __le64 qw[2];
247};
248
249struct qib_verbs_txreq {
250 struct qib_sdma_txreq txreq;
251 struct qib_qp *qp;
252 struct qib_swqe *wqe;
253 u32 dwords;
254 u16 hdr_dwords;
255 u16 hdr_inx;
256 struct qib_pio_header *align_buf;
257 struct qib_mregion *mr;
258 struct qib_sge_state *ss;
259};
260
261#define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1
262#define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2
263#define QIB_SDMA_TXREQ_F_INTREQ 0x4
264#define QIB_SDMA_TXREQ_F_FREEBUF 0x8
265#define QIB_SDMA_TXREQ_F_FREEDESC 0x10
266
267#define QIB_SDMA_TXREQ_S_OK 0
268#define QIB_SDMA_TXREQ_S_SENDERROR 1
269#define QIB_SDMA_TXREQ_S_ABORTED 2
270#define QIB_SDMA_TXREQ_S_SHUTDOWN 3
271
272
273
274
275
276
277#define QIB_IB_CFG_LIDLMC 0
278#define QIB_IB_CFG_LWID_ENB 2
279#define QIB_IB_CFG_LWID 3
280#define QIB_IB_CFG_SPD_ENB 4
281#define QIB_IB_CFG_SPD 5
282#define QIB_IB_CFG_RXPOL_ENB 6
283#define QIB_IB_CFG_LREV_ENB 7
284#define QIB_IB_CFG_LINKLATENCY 8
285#define QIB_IB_CFG_HRTBT 9
286#define QIB_IB_CFG_OP_VLS 10
287#define QIB_IB_CFG_VL_HIGH_CAP 11
288#define QIB_IB_CFG_VL_LOW_CAP 12
289#define QIB_IB_CFG_OVERRUN_THRESH 13
290#define QIB_IB_CFG_PHYERR_THRESH 14
291#define QIB_IB_CFG_LINKDEFAULT 15
292#define QIB_IB_CFG_PKEYS 16
293#define QIB_IB_CFG_MTU 17
294#define QIB_IB_CFG_LSTATE 18
295#define QIB_IB_CFG_VL_HIGH_LIMIT 19
296#define QIB_IB_CFG_PMA_TICKS 20
297#define QIB_IB_CFG_PORT 21
298
299
300
301
302
303
304#define IB_LINKCMD_DOWN (0 << 16)
305#define IB_LINKCMD_ARMED (1 << 16)
306#define IB_LINKCMD_ACTIVE (2 << 16)
307#define IB_LINKINITCMD_NOP 0
308#define IB_LINKINITCMD_POLL 1
309#define IB_LINKINITCMD_SLEEP 2
310#define IB_LINKINITCMD_DISABLE 3
311
312
313
314
315#define QIB_IB_LINKDOWN 0
316#define QIB_IB_LINKARM 1
317#define QIB_IB_LINKACTIVE 2
318#define QIB_IB_LINKDOWN_ONLY 3
319#define QIB_IB_LINKDOWN_SLEEP 4
320#define QIB_IB_LINKDOWN_DISABLE 5
321
322
323
324
325
326
327
328
329#define QIB_IB_SDR 1
330#define QIB_IB_DDR 2
331#define QIB_IB_QDR 4
332
333#define QIB_DEFAULT_MTU 4096
334
335
336#define QIB_MAX_IB_PORTS 2
337
338
339
340
341#define QIB_IB_TBL_VL_HIGH_ARB 1
342#define QIB_IB_TBL_VL_LOW_ARB 2
343
344
345
346
347
348
349#define QIB_RCVCTRL_TAILUPD_ENB 0x01
350#define QIB_RCVCTRL_TAILUPD_DIS 0x02
351#define QIB_RCVCTRL_CTXT_ENB 0x04
352#define QIB_RCVCTRL_CTXT_DIS 0x08
353#define QIB_RCVCTRL_INTRAVAIL_ENB 0x10
354#define QIB_RCVCTRL_INTRAVAIL_DIS 0x20
355#define QIB_RCVCTRL_PKEY_ENB 0x40
356#define QIB_RCVCTRL_PKEY_DIS 0x80
357#define QIB_RCVCTRL_BP_ENB 0x0100
358#define QIB_RCVCTRL_BP_DIS 0x0200
359#define QIB_RCVCTRL_TIDFLOW_ENB 0x0400
360#define QIB_RCVCTRL_TIDFLOW_DIS 0x0800
361
362
363
364
365
366
367
368
369#define QIB_SENDCTRL_DISARM (0x1000)
370#define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM)
371
372#define QIB_SENDCTRL_AVAIL_DIS (0x4000)
373#define QIB_SENDCTRL_AVAIL_ENB (0x8000)
374#define QIB_SENDCTRL_AVAIL_BLIP (0x10000)
375#define QIB_SENDCTRL_SEND_DIS (0x20000)
376#define QIB_SENDCTRL_SEND_ENB (0x40000)
377#define QIB_SENDCTRL_FLUSH (0x80000)
378#define QIB_SENDCTRL_CLEAR (0x100000)
379#define QIB_SENDCTRL_DISARM_ALL (0x200000)
380
381
382
383
384
385
386
387
388#define QIBPORTCNTR_PKTSEND 0U
389#define QIBPORTCNTR_WORDSEND 1U
390#define QIBPORTCNTR_PSXMITDATA 2U
391#define QIBPORTCNTR_PSXMITPKTS 3U
392#define QIBPORTCNTR_PSXMITWAIT 4U
393#define QIBPORTCNTR_SENDSTALL 5U
394
395#define QIBPORTCNTR_PKTRCV 6U
396#define QIBPORTCNTR_PSRCVDATA 7U
397#define QIBPORTCNTR_PSRCVPKTS 8U
398#define QIBPORTCNTR_RCVEBP 9U
399#define QIBPORTCNTR_RCVOVFL 10U
400#define QIBPORTCNTR_WORDRCV 11U
401
402#define QIBPORTCNTR_RXLOCALPHYERR 12U
403#define QIBPORTCNTR_RXVLERR 13U
404#define QIBPORTCNTR_ERRICRC 14U
405#define QIBPORTCNTR_ERRVCRC 15U
406#define QIBPORTCNTR_ERRLPCRC 16U
407#define QIBPORTCNTR_BADFORMAT 17U
408#define QIBPORTCNTR_ERR_RLEN 18U
409#define QIBPORTCNTR_IBSYMBOLERR 19U
410#define QIBPORTCNTR_INVALIDRLEN 20U
411#define QIBPORTCNTR_UNSUPVL 21U
412#define QIBPORTCNTR_EXCESSBUFOVFL 22U
413#define QIBPORTCNTR_ERRLINK 23U
414#define QIBPORTCNTR_IBLINKDOWN 24U
415#define QIBPORTCNTR_IBLINKERRRECOV 25U
416#define QIBPORTCNTR_LLI 26U
417
418#define QIBPORTCNTR_RXDROPPKT 27U
419#define QIBPORTCNTR_VL15PKTDROP 28U
420#define QIBPORTCNTR_ERRPKEY 29U
421#define QIBPORTCNTR_KHDROVFL 30U
422
423#define QIBPORTCNTR_PSINTERVAL 31U
424#define QIBPORTCNTR_PSSTART 32U
425#define QIBPORTCNTR_PSSTAT 33U
426
427
428#define ACTIVITY_TIMER 5
429
430#define MAX_NAME_SIZE 64
431struct qib_msix_entry {
432 struct msix_entry msix;
433 void *arg;
434 char name[MAX_NAME_SIZE];
435 cpumask_var_t mask;
436};
437
438
439
440
441
442
443struct qib_chip_specific;
444struct qib_chipport_specific;
445
446enum qib_sdma_states {
447 qib_sdma_state_s00_hw_down,
448 qib_sdma_state_s10_hw_start_up_wait,
449 qib_sdma_state_s20_idle,
450 qib_sdma_state_s30_sw_clean_up_wait,
451 qib_sdma_state_s40_hw_clean_up_wait,
452 qib_sdma_state_s50_hw_halt_wait,
453 qib_sdma_state_s99_running,
454};
455
456enum qib_sdma_events {
457 qib_sdma_event_e00_go_hw_down,
458 qib_sdma_event_e10_go_hw_start,
459 qib_sdma_event_e20_hw_started,
460 qib_sdma_event_e30_go_running,
461 qib_sdma_event_e40_sw_cleaned,
462 qib_sdma_event_e50_hw_cleaned,
463 qib_sdma_event_e60_hw_halted,
464 qib_sdma_event_e70_go_idle,
465 qib_sdma_event_e7220_err_halted,
466 qib_sdma_event_e7322_err_halted,
467 qib_sdma_event_e90_timer_tick,
468};
469
470extern char *qib_sdma_state_names[];
471extern char *qib_sdma_event_names[];
472
473struct sdma_set_state_action {
474 unsigned op_enable:1;
475 unsigned op_intenable:1;
476 unsigned op_halt:1;
477 unsigned op_drain:1;
478 unsigned go_s99_running_tofalse:1;
479 unsigned go_s99_running_totrue:1;
480};
481
482struct qib_sdma_state {
483 struct kref kref;
484 struct completion comp;
485 enum qib_sdma_states current_state;
486 struct sdma_set_state_action *set_state_action;
487 unsigned current_op;
488 unsigned go_s99_running;
489 unsigned first_sendbuf;
490 unsigned last_sendbuf;
491
492 enum qib_sdma_states previous_state;
493 unsigned previous_op;
494 enum qib_sdma_events last_event;
495};
496
497struct xmit_wait {
498 struct timer_list timer;
499 u64 counter;
500 u8 flags;
501 struct cache {
502 u64 psxmitdata;
503 u64 psrcvdata;
504 u64 psxmitpkts;
505 u64 psrcvpkts;
506 u64 psxmitwait;
507 } counter_cache;
508};
509
510
511
512
513
514
515
516struct qib_pportdata {
517 struct qib_ibport ibport_data;
518
519 struct qib_devdata *dd;
520 struct qib_chippport_specific *cpspec;
521 struct kobject pport_kobj;
522 struct kobject pport_cc_kobj;
523 struct kobject sl2vl_kobj;
524 struct kobject diagc_kobj;
525
526
527 __be64 guid;
528
529
530 u32 lflags;
531
532 u32 state_wanted;
533 spinlock_t lflags_lock;
534
535
536 atomic_t pkeyrefs[4];
537
538
539
540
541
542 u64 *statusp;
543
544
545
546
547 struct qib_sdma_desc *sdma_descq;
548 struct workqueue_struct *qib_wq;
549 struct qib_sdma_state sdma_state;
550 dma_addr_t sdma_descq_phys;
551 volatile __le64 *sdma_head_dma;
552 dma_addr_t sdma_head_phys;
553 u16 sdma_descq_cnt;
554
555
556 spinlock_t sdma_lock ____cacheline_aligned_in_smp;
557 struct list_head sdma_activelist;
558 u64 sdma_descq_added;
559 u64 sdma_descq_removed;
560 u16 sdma_descq_tail;
561 u16 sdma_descq_head;
562 u8 sdma_generation;
563
564 struct tasklet_struct sdma_sw_clean_up_task
565 ____cacheline_aligned_in_smp;
566
567 wait_queue_head_t state_wait;
568
569
570 unsigned hol_state;
571 struct timer_list hol_timer;
572
573
574
575
576
577
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579
580
581
582
583
584
585
586
587
588 u64 lastibcstat;
589
590
591
592
593
594
595
596 unsigned long p_rcvctrl;
597 unsigned long p_sendctrl;
598
599 u32 ibmtu;
600
601
602
603
604 u32 ibmaxlen;
605
606
607
608
609 u32 init_ibmaxlen;
610
611 u16 lid;
612
613 u16 pkeys[4];
614
615 u8 lmc;
616 u8 link_width_supported;
617 u8 link_speed_supported;
618 u8 link_width_enabled;
619 u8 link_speed_enabled;
620 u8 link_width_active;
621 u8 link_speed_active;
622 u8 vls_supported;
623 u8 vls_operational;
624
625 u8 rx_pol_inv;
626
627 u8 hw_pidx;
628 u8 port;
629
630 u8 delay_mult;
631
632
633 u8 led_override;
634 u16 led_override_timeoff;
635 u8 led_override_vals[2];
636 u8 led_override_phase;
637 atomic_t led_override_timer_active;
638
639 struct timer_list led_override_timer;
640 struct xmit_wait cong_stats;
641 struct timer_list symerr_clear_timer;
642
643
644 spinlock_t cc_shadow_lock
645 ____cacheline_aligned_in_smp;
646
647
648 struct cc_table_shadow *ccti_entries_shadow;
649
650
651 struct ib_cc_congestion_setting_attr_shadow *congestion_entries_shadow;
652
653
654 struct ib_cc_table_entry_shadow *ccti_entries;
655
656
657 struct ib_cc_congestion_entry_shadow *congestion_entries;
658
659
660
661
662 u16 cc_supported_table_entries;
663
664
665 u16 total_cct_entry;
666
667
668 u16 cc_sl_control_map;
669
670
671 u16 ccti_limit;
672
673
674 u8 cc_max_table_entries;
675};
676
677
678
679
680
681
682
683
684struct diag_observer;
685
686typedef int (*diag_hook) (struct qib_devdata *dd,
687 const struct diag_observer *op,
688 u32 offs, u64 *data, u64 mask, int only_32);
689
690struct diag_observer {
691 diag_hook hook;
692 u32 bottom;
693 u32 top;
694};
695
696extern int qib_register_observer(struct qib_devdata *dd,
697 const struct diag_observer *op);
698
699
700struct diag_observer_list_elt;
701
702
703
704
705
706
707struct qib_devdata {
708 struct qib_ibdev verbs_dev;
709 struct list_head list;
710
711
712 struct pci_dev *pcidev;
713 struct cdev *user_cdev;
714 struct cdev *diag_cdev;
715 struct device *user_device;
716 struct device *diag_device;
717
718
719 u64 __iomem *kregbase;
720
721 u64 __iomem *kregend;
722
723 resource_size_t physaddr;
724
725 struct qib_ctxtdata **rcd;
726
727
728
729
730 struct qib_pportdata *pport;
731 struct qib_chip_specific *cspec;
732
733
734 void __iomem *pio2kbase;
735
736 void __iomem *pio4kbase;
737
738 void __iomem *piobase;
739
740 u64 __iomem *userbase;
741 void __iomem *piovl15base;
742
743
744
745
746
747
748
749 volatile __le64 *pioavailregs_dma;
750
751 dma_addr_t pioavailregs_phys;
752
753
754
755
756
757
758
759 int (*f_intr_fallback)(struct qib_devdata *);
760
761 int (*f_reset)(struct qib_devdata *);
762 void (*f_quiet_serdes)(struct qib_pportdata *);
763 int (*f_bringup_serdes)(struct qib_pportdata *);
764 int (*f_early_init)(struct qib_devdata *);
765 void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *);
766 void (*f_put_tid)(struct qib_devdata *, u64 __iomem*,
767 u32, unsigned long);
768 void (*f_cleanup)(struct qib_devdata *);
769 void (*f_setextled)(struct qib_pportdata *, u32);
770
771 int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *);
772
773 void (*f_free_irq)(struct qib_devdata *);
774 struct qib_message_header *(*f_get_msgheader)
775 (struct qib_devdata *, __le32 *);
776 void (*f_config_ctxts)(struct qib_devdata *);
777 int (*f_get_ib_cfg)(struct qib_pportdata *, int);
778 int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32);
779 int (*f_set_ib_loopback)(struct qib_pportdata *, const char *);
780 int (*f_get_ib_table)(struct qib_pportdata *, int, void *);
781 int (*f_set_ib_table)(struct qib_pportdata *, int, void *);
782 u32 (*f_iblink_state)(u64);
783 u8 (*f_ibphys_portstate)(u64);
784 void (*f_xgxs_reset)(struct qib_pportdata *);
785
786 int (*f_ib_updown)(struct qib_pportdata *, int, u64);
787 u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *);
788
789 int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir,
790 u32 mask);
791
792 int (*f_eeprom_wen)(struct qib_devdata *dd, int wen);
793
794
795
796
797
798
799 void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op,
800 int ctxt);
801
802 void (*f_sendctrl)(struct qib_pportdata *, u32 op);
803 void (*f_set_intr_state)(struct qib_devdata *, u32);
804 void (*f_set_armlaunch)(struct qib_devdata *, u32);
805 void (*f_wantpiobuf_intr)(struct qib_devdata *, u32);
806 int (*f_late_initreg)(struct qib_devdata *);
807 int (*f_init_sdma_regs)(struct qib_pportdata *);
808 u16 (*f_sdma_gethead)(struct qib_pportdata *);
809 int (*f_sdma_busy)(struct qib_pportdata *);
810 void (*f_sdma_update_tail)(struct qib_pportdata *, u16);
811 void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned);
812 void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned);
813 void (*f_sdma_hw_clean_up)(struct qib_pportdata *);
814 void (*f_sdma_hw_start_up)(struct qib_pportdata *);
815 void (*f_sdma_init_early)(struct qib_pportdata *);
816 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32);
817 void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32);
818 u32 (*f_hdrqempty)(struct qib_ctxtdata *);
819 u64 (*f_portcntr)(struct qib_pportdata *, u32);
820 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
821 u64 **);
822 u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32,
823 char **, u64 **);
824 u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8);
825 void (*f_initvl15_bufs)(struct qib_devdata *);
826 void (*f_init_ctxt)(struct qib_ctxtdata *);
827 void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32,
828 struct qib_ctxtdata *);
829 void (*f_writescratch)(struct qib_devdata *, u32);
830 int (*f_tempsense_rd)(struct qib_devdata *, int regnum);
831
832 char *boardname;
833
834
835 u64 tidtemplate;
836
837 u64 tidinvalid;
838
839
840 u32 pioavregs;
841
842 u32 flags;
843
844 u32 lastctxt_piobuf;
845
846
847 u32 int_counter;
848
849
850 u32 pbufsctxt;
851
852 u32 ctxts_extrabuf;
853
854
855
856
857 u32 cfgctxts;
858
859
860
861 u32 freectxts;
862
863
864
865
866
867 u32 upd_pio_shadow;
868
869
870 u32 maxpkts_call;
871 u32 avgpkts_call;
872 u64 nopiobufs;
873
874
875 u16 vendorid;
876
877 u16 deviceid;
878
879 unsigned long wc_cookie;
880 unsigned long wc_base;
881 unsigned long wc_len;
882
883
884 struct page **pageshadow;
885
886 dma_addr_t *physshadow;
887 u64 __iomem *egrtidbase;
888 spinlock_t sendctrl_lock;
889
890 spinlock_t uctxt_lock;
891
892
893
894
895
896 u64 *devstatusp;
897 char *freezemsg;
898 u32 freezelen;
899
900 struct timer_list stats_timer;
901
902
903 struct timer_list intrchk_timer;
904 unsigned long ureg_align;
905
906
907
908
909
910 spinlock_t pioavail_lock;
911
912
913
914 u32 last_pio;
915
916
917
918 u32 min_kernel_pio;
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934 unsigned long pioavailshadow[6];
935
936 unsigned long pioavailkernel[6];
937
938 unsigned long pio_need_disarm[3];
939
940 unsigned long pio_writing[3];
941
942 u64 revision;
943
944 __be64 base_guid;
945
946
947
948
949
950 u64 piobufbase;
951 u32 pio2k_bufbase;
952
953
954
955
956 u32 nguid;
957
958
959
960
961 unsigned long rcvctrl;
962 unsigned long sendctrl;
963
964
965 u32 rcvhdrcnt;
966
967 u32 rcvhdrsize;
968
969 u32 rcvhdrentsize;
970
971 u32 ctxtcnt;
972
973 u32 palign;
974
975 u32 piobcnt2k;
976
977 u32 piosize2k;
978
979 u32 piosize2kmax_dwords;
980
981 u32 piobcnt4k;
982
983 u32 piosize4k;
984
985 u32 rcvegrbase;
986
987 u32 rcvtidbase;
988
989 u32 rcvtidcnt;
990
991 u32 uregbase;
992
993 u32 control;
994
995
996 u32 align4k;
997
998 u16 rcvegrbufsize;
999
1000 u16 rcvegrbufsize_shift;
1001
1002 u32 lbus_width;
1003
1004 u32 lbus_speed;
1005 int unit;
1006
1007
1008
1009 u32 msi_lo;
1010
1011 u32 msi_hi;
1012
1013 u16 msi_data;
1014
1015 u32 pcibar0;
1016
1017 u32 pcibar1;
1018 u64 rhdrhead_intr_off;
1019
1020
1021
1022
1023
1024 u8 serial[16];
1025
1026 u8 boardversion[96];
1027 u8 lbus_info[32];
1028
1029 u8 majrev;
1030
1031 u8 minrev;
1032
1033
1034
1035 u8 num_pports;
1036
1037 u8 first_user_ctxt;
1038 u8 n_krcv_queues;
1039 u8 qpn_mask;
1040 u8 skip_kctxt_mask;
1041
1042 u16 rhf_offset;
1043
1044
1045
1046
1047 u8 gpio_sda_num;
1048 u8 gpio_scl_num;
1049 u8 twsi_eeprom_dev;
1050 u8 board_atten;
1051
1052
1053
1054 spinlock_t eep_st_lock;
1055
1056 struct mutex eep_lock;
1057 uint64_t traffic_wds;
1058
1059 atomic_t active_time;
1060
1061 uint8_t eep_st_errs[QIB_EEP_LOG_CNT];
1062 uint8_t eep_st_new_errs[QIB_EEP_LOG_CNT];
1063 uint16_t eep_hrs;
1064
1065
1066
1067
1068 struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT];
1069 struct qib_diag_client *diag_client;
1070 spinlock_t qib_diag_trans_lock;
1071 struct diag_observer_list_elt *diag_observer_list;
1072
1073 u8 psxmitwait_supported;
1074
1075 u16 psxmitwait_check_rate;
1076
1077 struct tasklet_struct error_tasklet;
1078};
1079
1080
1081#define QIB_HOL_UP 0
1082#define QIB_HOL_INIT 1
1083
1084#define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0)
1085#define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1)
1086#define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2)
1087#define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3)
1088#define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4)
1089
1090
1091#define TXCHK_CHG_TYPE_DIS1 3
1092#define TXCHK_CHG_TYPE_ENAB1 2
1093#define TXCHK_CHG_TYPE_KERN 1
1094#define TXCHK_CHG_TYPE_USER 0
1095
1096#define QIB_CHASE_TIME msecs_to_jiffies(145)
1097#define QIB_CHASE_DIS_TIME msecs_to_jiffies(160)
1098
1099
1100struct qib_filedata {
1101 struct qib_ctxtdata *rcd;
1102 unsigned subctxt;
1103 unsigned tidcursor;
1104 struct qib_user_sdma_queue *pq;
1105 int rec_cpu_num;
1106};
1107
1108extern struct list_head qib_dev_list;
1109extern spinlock_t qib_devs_lock;
1110extern struct qib_devdata *qib_lookup(int unit);
1111extern u32 qib_cpulist_count;
1112extern unsigned long *qib_cpulist;
1113
1114extern unsigned qib_wc_pat;
1115extern unsigned qib_cc_table_size;
1116int qib_init(struct qib_devdata *, int);
1117int init_chip_wc_pat(struct qib_devdata *dd, u32);
1118int qib_enable_wc(struct qib_devdata *dd);
1119void qib_disable_wc(struct qib_devdata *dd);
1120int qib_count_units(int *npresentp, int *nupp);
1121int qib_count_active_units(void);
1122
1123int qib_cdev_init(int minor, const char *name,
1124 const struct file_operations *fops,
1125 struct cdev **cdevp, struct device **devp);
1126void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp);
1127int qib_dev_init(void);
1128void qib_dev_cleanup(void);
1129
1130int qib_diag_add(struct qib_devdata *);
1131void qib_diag_remove(struct qib_devdata *);
1132void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64);
1133void qib_sdma_update_tail(struct qib_pportdata *, u16);
1134
1135int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err);
1136void qib_bad_intrstatus(struct qib_devdata *);
1137void qib_handle_urcv(struct qib_devdata *, u64);
1138
1139
1140void qib_chip_cleanup(struct qib_devdata *);
1141
1142void qib_chip_done(void);
1143
1144
1145int qib_unordered_wc(void);
1146void qib_pio_copy(void __iomem *to, const void *from, size_t count);
1147
1148void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned);
1149int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *);
1150void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned);
1151void qib_cancel_sends(struct qib_pportdata *);
1152
1153int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *);
1154int qib_setup_eagerbufs(struct qib_ctxtdata *);
1155void qib_set_ctxtcnt(struct qib_devdata *);
1156int qib_create_ctxts(struct qib_devdata *dd);
1157struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32);
1158void qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8);
1159void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *);
1160
1161u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *);
1162int qib_reset_device(int);
1163int qib_wait_linkstate(struct qib_pportdata *, u32, int);
1164int qib_set_linkstate(struct qib_pportdata *, u8);
1165int qib_set_mtu(struct qib_pportdata *, u16);
1166int qib_set_lid(struct qib_pportdata *, u32, u8);
1167void qib_hol_down(struct qib_pportdata *);
1168void qib_hol_init(struct qib_pportdata *);
1169void qib_hol_up(struct qib_pportdata *);
1170void qib_hol_event(unsigned long);
1171void qib_disable_after_error(struct qib_devdata *);
1172int qib_set_uevent_bits(struct qib_pportdata *, const int);
1173
1174
1175#define ctxt_fp(fp) \
1176 (((struct qib_filedata *)(fp)->private_data)->rcd)
1177#define subctxt_fp(fp) \
1178 (((struct qib_filedata *)(fp)->private_data)->subctxt)
1179#define tidcursor_fp(fp) \
1180 (((struct qib_filedata *)(fp)->private_data)->tidcursor)
1181#define user_sdma_queue_fp(fp) \
1182 (((struct qib_filedata *)(fp)->private_data)->pq)
1183
1184static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd)
1185{
1186 return ppd->dd;
1187}
1188
1189static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev)
1190{
1191 return container_of(dev, struct qib_devdata, verbs_dev);
1192}
1193
1194static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev)
1195{
1196 return dd_from_dev(to_idev(ibdev));
1197}
1198
1199static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp)
1200{
1201 return container_of(ibp, struct qib_pportdata, ibport_data);
1202}
1203
1204static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u8 port)
1205{
1206 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1207 unsigned pidx = port - 1;
1208
1209 WARN_ON(pidx >= dd->num_pports);
1210 return &dd->pport[pidx].ibport_data;
1211}
1212
1213
1214
1215
1216#define QIB_HAS_LINK_LATENCY 0x1
1217#define QIB_INITTED 0x2
1218#define QIB_DOING_RESET 0x4
1219#define QIB_PRESENT 0x8
1220#define QIB_PIO_FLUSH_WC 0x10
1221#define QIB_HAS_THRESH_UPDATE 0x40
1222#define QIB_HAS_SDMA_TIMEOUT 0x80
1223#define QIB_USE_SPCL_TRIG 0x100
1224#define QIB_NODMA_RTAIL 0x200
1225#define QIB_HAS_INTX 0x800
1226#define QIB_HAS_SEND_DMA 0x1000
1227#define QIB_HAS_VLSUPP 0x2000
1228#define QIB_HAS_HDRSUPP 0x4000
1229#define QIB_BADINTR 0x8000
1230#define QIB_DCA_ENABLED 0x10000
1231#define QIB_HAS_QSFP 0x20000
1232
1233
1234
1235
1236#define QIBL_LINKV 0x1
1237#define QIBL_LINKDOWN 0x8
1238#define QIBL_LINKINIT 0x10
1239#define QIBL_LINKARMED 0x20
1240#define QIBL_LINKACTIVE 0x40
1241
1242#define QIBL_IB_AUTONEG_INPROG 0x1000
1243#define QIBL_IB_AUTONEG_FAILED 0x2000
1244#define QIBL_IB_LINK_DISABLED 0x4000
1245
1246#define QIBL_IB_FORCE_NOTIFY 0x8000
1247
1248
1249#define QIB_PBC_LENGTH_MASK ((1 << 11) - 1)
1250
1251
1252
1253
1254#define QIB_CTXT_WAITING_RCV 2
1255
1256#define QIB_CTXT_MASTER_UNINIT 4
1257
1258#define QIB_CTXT_WAITING_URG 5
1259
1260
1261void qib_free_data(struct qib_ctxtdata *dd);
1262void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned,
1263 u32, struct qib_ctxtdata *);
1264struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *,
1265 const struct pci_device_id *);
1266struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *,
1267 const struct pci_device_id *);
1268struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *,
1269 const struct pci_device_id *);
1270void qib_free_devdata(struct qib_devdata *);
1271struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra);
1272
1273#define QIB_TWSI_NO_DEV 0xFF
1274
1275int qib_twsi_reset(struct qib_devdata *dd);
1276int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer,
1277 int len);
1278int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
1279 const void *buffer, int len);
1280void qib_get_eeprom_info(struct qib_devdata *);
1281int qib_update_eeprom_log(struct qib_devdata *dd);
1282void qib_inc_eeprom_err(struct qib_devdata *dd, u32 eidx, u32 incr);
1283void qib_dump_lookup_output_queue(struct qib_devdata *);
1284void qib_force_pio_avail_update(struct qib_devdata *);
1285void qib_clear_symerror_on_linkup(unsigned long opaque);
1286
1287
1288
1289
1290
1291
1292#define QIB_LED_PHYS 1
1293#define QIB_LED_LOG 2
1294void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val);
1295
1296
1297int qib_setup_sdma(struct qib_pportdata *);
1298void qib_teardown_sdma(struct qib_pportdata *);
1299void __qib_sdma_intr(struct qib_pportdata *);
1300void qib_sdma_intr(struct qib_pportdata *);
1301int qib_sdma_verbs_send(struct qib_pportdata *, struct qib_sge_state *,
1302 u32, struct qib_verbs_txreq *);
1303
1304int qib_sdma_make_progress(struct qib_pportdata *dd);
1305
1306static inline int qib_sdma_empty(const struct qib_pportdata *ppd)
1307{
1308 return ppd->sdma_descq_added == ppd->sdma_descq_removed;
1309}
1310
1311
1312static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd)
1313{
1314 return ppd->sdma_descq_cnt -
1315 (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1;
1316}
1317
1318static inline int __qib_sdma_running(struct qib_pportdata *ppd)
1319{
1320 return ppd->sdma_state.current_state == qib_sdma_state_s99_running;
1321}
1322int qib_sdma_running(struct qib_pportdata *);
1323
1324void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1325void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1326
1327
1328
1329
1330#define QIB_DFLT_RCVHDRSIZE 9
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343#define QIB_RCVHDR_ENTSIZE 32
1344
1345int qib_get_user_pages(unsigned long, size_t, struct page **);
1346void qib_release_user_pages(struct page **, size_t);
1347int qib_eeprom_read(struct qib_devdata *, u8, void *, int);
1348int qib_eeprom_write(struct qib_devdata *, u8, const void *, int);
1349u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32);
1350void qib_sendbuf_done(struct qib_devdata *, unsigned);
1351
1352static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd)
1353{
1354 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL;
1355}
1356
1357static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd)
1358{
1359
1360
1361
1362
1363 return (u32) le64_to_cpu(
1364 *((volatile __le64 *)rcd->rcvhdrtail_kvaddr));
1365}
1366
1367static inline u32 qib_get_hdrqtail(const struct qib_ctxtdata *rcd)
1368{
1369 const struct qib_devdata *dd = rcd->dd;
1370 u32 hdrqtail;
1371
1372 if (dd->flags & QIB_NODMA_RTAIL) {
1373 __le32 *rhf_addr;
1374 u32 seq;
1375
1376 rhf_addr = (__le32 *) rcd->rcvhdrq +
1377 rcd->head + dd->rhf_offset;
1378 seq = qib_hdrget_seq(rhf_addr);
1379 hdrqtail = rcd->head;
1380 if (seq == rcd->seq_cnt)
1381 hdrqtail++;
1382 } else
1383 hdrqtail = qib_get_rcvhdrtail(rcd);
1384
1385 return hdrqtail;
1386}
1387
1388
1389
1390
1391
1392extern const char ib_qib_version[];
1393
1394int qib_device_create(struct qib_devdata *);
1395void qib_device_remove(struct qib_devdata *);
1396
1397int qib_create_port_files(struct ib_device *ibdev, u8 port_num,
1398 struct kobject *kobj);
1399int qib_verbs_register_sysfs(struct qib_devdata *);
1400void qib_verbs_unregister_sysfs(struct qib_devdata *);
1401
1402extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len);
1403
1404int __init qib_init_qibfs(void);
1405int __exit qib_exit_qibfs(void);
1406
1407int qibfs_add(struct qib_devdata *);
1408int qibfs_remove(struct qib_devdata *);
1409
1410int qib_pcie_init(struct pci_dev *, const struct pci_device_id *);
1411int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *,
1412 const struct pci_device_id *);
1413void qib_pcie_ddcleanup(struct qib_devdata *);
1414int qib_pcie_params(struct qib_devdata *, u32, u32 *, struct qib_msix_entry *);
1415int qib_reinit_intr(struct qib_devdata *);
1416void qib_enable_intx(struct pci_dev *);
1417void qib_nomsi(struct qib_devdata *);
1418void qib_nomsix(struct qib_devdata *);
1419void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *);
1420void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8);
1421
1422
1423
1424
1425dma_addr_t qib_map_page(struct pci_dev *, struct page *, unsigned long,
1426 size_t, int);
1427const char *qib_get_unit_name(int unit);
1428
1429
1430
1431
1432
1433#if defined(CONFIG_X86_64)
1434#define qib_flush_wc() asm volatile("sfence" : : : "memory")
1435#else
1436#define qib_flush_wc() wmb()
1437#endif
1438
1439
1440extern unsigned qib_ibmtu;
1441extern ushort qib_cfgctxts;
1442extern ushort qib_num_cfg_vls;
1443extern ushort qib_mini_init;
1444extern unsigned qib_n_krcv_queues;
1445extern unsigned qib_sdma_fetch_arb;
1446extern unsigned qib_compat_ddr_negotiate;
1447extern int qib_special_trigger;
1448
1449extern struct mutex qib_mutex;
1450
1451
1452#define STATUS_TIMEOUT 60
1453
1454#define QIB_DRV_NAME "ib_qib"
1455#define QIB_USER_MINOR_BASE 0
1456#define QIB_TRACE_MINOR 127
1457#define QIB_DIAGPKT_MINOR 128
1458#define QIB_DIAG_MINOR_BASE 129
1459#define QIB_NMINORS 255
1460
1461#define PCI_VENDOR_ID_PATHSCALE 0x1fc1
1462#define PCI_VENDOR_ID_QLOGIC 0x1077
1463#define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10
1464#define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220
1465#define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476#define qib_early_err(dev, fmt, ...) \
1477 do { \
1478 dev_err(dev, fmt, ##__VA_ARGS__); \
1479 } while (0)
1480
1481#define qib_dev_err(dd, fmt, ...) \
1482 do { \
1483 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1484 qib_get_unit_name((dd)->unit), ##__VA_ARGS__); \
1485 } while (0)
1486
1487#define qib_dev_porterr(dd, port, fmt, ...) \
1488 do { \
1489 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \
1490 qib_get_unit_name((dd)->unit), (dd)->unit, (port), \
1491 ##__VA_ARGS__); \
1492 } while (0)
1493
1494#define qib_devinfo(pcidev, fmt, ...) \
1495 do { \
1496 dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__); \
1497 } while (0)
1498
1499
1500
1501
1502struct qib_hwerror_msgs {
1503 u64 mask;
1504 const char *msg;
1505 size_t sz;
1506};
1507
1508#define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b }
1509
1510
1511void qib_format_hwerrors(u64 hwerrs,
1512 const struct qib_hwerror_msgs *hwerrmsgs,
1513 size_t nhwerrmsgs, char *msg, size_t lmsg);
1514#endif
1515