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39#include <linux/interrupt.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/module.h>
43#include <linux/io.h>
44#include <rdma/ib_verbs.h>
45
46#include "qib.h"
47#include "qib_7220.h"
48
49static void qib_setup_7220_setextled(struct qib_pportdata *, u32);
50static void qib_7220_handle_hwerrors(struct qib_devdata *, char *, size_t);
51static void sendctrl_7220_mod(struct qib_pportdata *ppd, u32 op);
52static u32 qib_7220_iblink_state(u64);
53static u8 qib_7220_phys_portstate(u64);
54static void qib_sdma_update_7220_tail(struct qib_pportdata *, u16);
55static void qib_set_ib_7220_lstate(struct qib_pportdata *, u16, u16);
56
57
58
59
60
61
62
63
64#define KREG_IDX(regname) (QIB_7220_##regname##_OFFS / sizeof(u64))
65
66
67#define kr_control KREG_IDX(Control)
68#define kr_counterregbase KREG_IDX(CntrRegBase)
69#define kr_errclear KREG_IDX(ErrClear)
70#define kr_errmask KREG_IDX(ErrMask)
71#define kr_errstatus KREG_IDX(ErrStatus)
72#define kr_extctrl KREG_IDX(EXTCtrl)
73#define kr_extstatus KREG_IDX(EXTStatus)
74#define kr_gpio_clear KREG_IDX(GPIOClear)
75#define kr_gpio_mask KREG_IDX(GPIOMask)
76#define kr_gpio_out KREG_IDX(GPIOOut)
77#define kr_gpio_status KREG_IDX(GPIOStatus)
78#define kr_hrtbt_guid KREG_IDX(HRTBT_GUID)
79#define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
80#define kr_hwerrclear KREG_IDX(HwErrClear)
81#define kr_hwerrmask KREG_IDX(HwErrMask)
82#define kr_hwerrstatus KREG_IDX(HwErrStatus)
83#define kr_ibcctrl KREG_IDX(IBCCtrl)
84#define kr_ibcddrctrl KREG_IDX(IBCDDRCtrl)
85#define kr_ibcddrstatus KREG_IDX(IBCDDRStatus)
86#define kr_ibcstatus KREG_IDX(IBCStatus)
87#define kr_ibserdesctrl KREG_IDX(IBSerDesCtrl)
88#define kr_intclear KREG_IDX(IntClear)
89#define kr_intmask KREG_IDX(IntMask)
90#define kr_intstatus KREG_IDX(IntStatus)
91#define kr_ncmodectrl KREG_IDX(IBNCModeCtrl)
92#define kr_palign KREG_IDX(PageAlign)
93#define kr_partitionkey KREG_IDX(RcvPartitionKey)
94#define kr_portcnt KREG_IDX(PortCnt)
95#define kr_rcvbthqp KREG_IDX(RcvBTHQP)
96#define kr_rcvctrl KREG_IDX(RcvCtrl)
97#define kr_rcvegrbase KREG_IDX(RcvEgrBase)
98#define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
99#define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
100#define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
101#define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
102#define kr_rcvpktledcnt KREG_IDX(RcvPktLEDCnt)
103#define kr_rcvtidbase KREG_IDX(RcvTIDBase)
104#define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
105#define kr_revision KREG_IDX(Revision)
106#define kr_scratch KREG_IDX(Scratch)
107#define kr_sendbuffererror KREG_IDX(SendBufErr0)
108#define kr_sendctrl KREG_IDX(SendCtrl)
109#define kr_senddmabase KREG_IDX(SendDmaBase)
110#define kr_senddmabufmask0 KREG_IDX(SendDmaBufMask0)
111#define kr_senddmabufmask1 (KREG_IDX(SendDmaBufMask0) + 1)
112#define kr_senddmabufmask2 (KREG_IDX(SendDmaBufMask0) + 2)
113#define kr_senddmahead KREG_IDX(SendDmaHead)
114#define kr_senddmaheadaddr KREG_IDX(SendDmaHeadAddr)
115#define kr_senddmalengen KREG_IDX(SendDmaLenGen)
116#define kr_senddmastatus KREG_IDX(SendDmaStatus)
117#define kr_senddmatail KREG_IDX(SendDmaTail)
118#define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
119#define kr_sendpiobufbase KREG_IDX(SendBufBase)
120#define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
121#define kr_sendpiosize KREG_IDX(SendBufSize)
122#define kr_sendregbase KREG_IDX(SendRegBase)
123#define kr_userregbase KREG_IDX(UserRegBase)
124#define kr_xgxs_cfg KREG_IDX(XGXSCfg)
125
126
127#define kr_rcvhdraddr KREG_IDX(RcvHdrAddr0)
128#define kr_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
129
130
131#define CREG_IDX(regname) ((QIB_7220_##regname##_OFFS - \
132 QIB_7220_LBIntCnt_OFFS) / sizeof(u64))
133
134#define cr_badformat CREG_IDX(RxVersionErrCnt)
135#define cr_erricrc CREG_IDX(RxICRCErrCnt)
136#define cr_errlink CREG_IDX(RxLinkMalformCnt)
137#define cr_errlpcrc CREG_IDX(RxLPCRCErrCnt)
138#define cr_errpkey CREG_IDX(RxPKeyMismatchCnt)
139#define cr_rcvflowctrl_err CREG_IDX(RxFlowCtrlViolCnt)
140#define cr_err_rlen CREG_IDX(RxLenErrCnt)
141#define cr_errslen CREG_IDX(TxLenErrCnt)
142#define cr_errtidfull CREG_IDX(RxTIDFullErrCnt)
143#define cr_errtidvalid CREG_IDX(RxTIDValidErrCnt)
144#define cr_errvcrc CREG_IDX(RxVCRCErrCnt)
145#define cr_ibstatuschange CREG_IDX(IBStatusChangeCnt)
146#define cr_lbint CREG_IDX(LBIntCnt)
147#define cr_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
148#define cr_invalidslen CREG_IDX(TxMaxMinLenErrCnt)
149#define cr_lbflowstall CREG_IDX(LBFlowStallCnt)
150#define cr_pktrcv CREG_IDX(RxDataPktCnt)
151#define cr_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
152#define cr_pktsend CREG_IDX(TxDataPktCnt)
153#define cr_pktsendflow CREG_IDX(TxFlowPktCnt)
154#define cr_portovfl CREG_IDX(RxP0HdrEgrOvflCnt)
155#define cr_rcvebp CREG_IDX(RxEBPCnt)
156#define cr_rcvovfl CREG_IDX(RxBufOvflCnt)
157#define cr_senddropped CREG_IDX(TxDroppedPktCnt)
158#define cr_sendstall CREG_IDX(TxFlowStallCnt)
159#define cr_sendunderrun CREG_IDX(TxUnderrunCnt)
160#define cr_wordrcv CREG_IDX(RxDwordCnt)
161#define cr_wordsend CREG_IDX(TxDwordCnt)
162#define cr_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
163#define cr_rxdroppkt CREG_IDX(RxDroppedPktCnt)
164#define cr_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
165#define cr_iblinkdown CREG_IDX(IBLinkDownedCnt)
166#define cr_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
167#define cr_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
168#define cr_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
169#define cr_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
170#define cr_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
171#define cr_rxvlerr CREG_IDX(RxVlErrCnt)
172#define cr_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
173#define cr_psstat CREG_IDX(PSStat)
174#define cr_psstart CREG_IDX(PSStart)
175#define cr_psinterval CREG_IDX(PSInterval)
176#define cr_psrcvdatacount CREG_IDX(PSRcvDataCount)
177#define cr_psrcvpktscount CREG_IDX(PSRcvPktsCount)
178#define cr_psxmitdatacount CREG_IDX(PSXmitDataCount)
179#define cr_psxmitpktscount CREG_IDX(PSXmitPktsCount)
180#define cr_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
181#define cr_txsdmadesc CREG_IDX(TxSDmaDescCnt)
182#define cr_pcieretrydiag CREG_IDX(PcieRetryBufDiagQwordCnt)
183
184#define SYM_RMASK(regname, fldname) ((u64) \
185 QIB_7220_##regname##_##fldname##_RMASK)
186#define SYM_MASK(regname, fldname) ((u64) \
187 QIB_7220_##regname##_##fldname##_RMASK << \
188 QIB_7220_##regname##_##fldname##_LSB)
189#define SYM_LSB(regname, fldname) (QIB_7220_##regname##_##fldname##_LSB)
190#define SYM_FIELD(value, regname, fldname) ((u64) \
191 (((value) >> SYM_LSB(regname, fldname)) & \
192 SYM_RMASK(regname, fldname)))
193#define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
194#define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
195
196
197#define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
198
199#define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
200
201#define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
202#define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
203
204#define QLOGIC_IB_IBCC_LINKCMD_DOWN 1
205#define QLOGIC_IB_IBCC_LINKCMD_ARMED 2
206#define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3
207
208#define BLOB_7220_IBCHG 0x81
209
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228
229static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
230 enum qib_ureg regno, int ctxt)
231{
232 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
233 return 0;
234
235 if (dd->userbase)
236 return readl(regno + (u64 __iomem *)
237 ((char __iomem *)dd->userbase +
238 dd->ureg_align * ctxt));
239 else
240 return readl(regno + (u64 __iomem *)
241 (dd->uregbase +
242 (char __iomem *)dd->kregbase +
243 dd->ureg_align * ctxt));
244}
245
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253
254
255static inline void qib_write_ureg(const struct qib_devdata *dd,
256 enum qib_ureg regno, u64 value, int ctxt)
257{
258 u64 __iomem *ubase;
259
260 if (dd->userbase)
261 ubase = (u64 __iomem *)
262 ((char __iomem *) dd->userbase +
263 dd->ureg_align * ctxt);
264 else
265 ubase = (u64 __iomem *)
266 (dd->uregbase +
267 (char __iomem *) dd->kregbase +
268 dd->ureg_align * ctxt);
269
270 if (dd->kregbase && (dd->flags & QIB_PRESENT))
271 writeq(value, &ubase[regno]);
272}
273
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279
280
281static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
282 const u16 regno, unsigned ctxt,
283 u64 value)
284{
285 qib_write_kreg(dd, regno + ctxt, value);
286}
287
288static inline void write_7220_creg(const struct qib_devdata *dd,
289 u16 regno, u64 value)
290{
291 if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT))
292 writeq(value, &dd->cspec->cregbase[regno]);
293}
294
295static inline u64 read_7220_creg(const struct qib_devdata *dd, u16 regno)
296{
297 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
298 return 0;
299 return readq(&dd->cspec->cregbase[regno]);
300}
301
302static inline u32 read_7220_creg32(const struct qib_devdata *dd, u16 regno)
303{
304 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
305 return 0;
306 return readl(&dd->cspec->cregbase[regno]);
307}
308
309
310#define QLOGIC_IB_R_EMULATORREV_MASK ((1ULL << 22) - 1)
311#define QLOGIC_IB_R_EMULATORREV_SHIFT 40
312
313
314#define QLOGIC_IB_C_RESET (1U << 7)
315
316
317#define QLOGIC_IB_I_RCVURG_MASK ((1ULL << 17) - 1)
318#define QLOGIC_IB_I_RCVURG_SHIFT 32
319#define QLOGIC_IB_I_RCVAVAIL_MASK ((1ULL << 17) - 1)
320#define QLOGIC_IB_I_RCVAVAIL_SHIFT 0
321#define QLOGIC_IB_I_SERDESTRIMDONE (1ULL << 27)
322
323#define QLOGIC_IB_C_FREEZEMODE 0x00000002
324#define QLOGIC_IB_C_LINKENABLE 0x00000004
325
326#define QLOGIC_IB_I_SDMAINT 0x8000000000000000ULL
327#define QLOGIC_IB_I_SDMADISABLED 0x4000000000000000ULL
328#define QLOGIC_IB_I_ERROR 0x0000000080000000ULL
329#define QLOGIC_IB_I_SPIOSENT 0x0000000040000000ULL
330#define QLOGIC_IB_I_SPIOBUFAVAIL 0x0000000020000000ULL
331#define QLOGIC_IB_I_GPIO 0x0000000010000000ULL
332
333
334#define QLOGIC_IB_I_BITSEXTANT \
335 (QLOGIC_IB_I_SDMAINT | QLOGIC_IB_I_SDMADISABLED | \
336 (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT) | \
337 (QLOGIC_IB_I_RCVAVAIL_MASK << \
338 QLOGIC_IB_I_RCVAVAIL_SHIFT) | \
339 QLOGIC_IB_I_ERROR | QLOGIC_IB_I_SPIOSENT | \
340 QLOGIC_IB_I_SPIOBUFAVAIL | QLOGIC_IB_I_GPIO | \
341 QLOGIC_IB_I_SERDESTRIMDONE)
342
343#define IB_HWE_BITSEXTANT \
344 (HWE_MASK(RXEMemParityErr) | \
345 HWE_MASK(TXEMemParityErr) | \
346 (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK << \
347 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) | \
348 QLOGIC_IB_HWE_PCIE1PLLFAILED | \
349 QLOGIC_IB_HWE_PCIE0PLLFAILED | \
350 QLOGIC_IB_HWE_PCIEPOISONEDTLP | \
351 QLOGIC_IB_HWE_PCIECPLTIMEOUT | \
352 QLOGIC_IB_HWE_PCIEBUSPARITYXTLH | \
353 QLOGIC_IB_HWE_PCIEBUSPARITYXADM | \
354 QLOGIC_IB_HWE_PCIEBUSPARITYRADM | \
355 HWE_MASK(PowerOnBISTFailed) | \
356 QLOGIC_IB_HWE_COREPLL_FBSLIP | \
357 QLOGIC_IB_HWE_COREPLL_RFSLIP | \
358 QLOGIC_IB_HWE_SERDESPLLFAILED | \
359 HWE_MASK(IBCBusToSPCParityErr) | \
360 HWE_MASK(IBCBusFromSPCParityErr) | \
361 QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR | \
362 QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR | \
363 QLOGIC_IB_HWE_SDMAMEMREADERR | \
364 QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED | \
365 QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT | \
366 QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT | \
367 QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT | \
368 QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT | \
369 QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR | \
370 QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR | \
371 QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR | \
372 QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR)
373
374#define IB_E_BITSEXTANT \
375 (ERR_MASK(RcvFormatErr) | ERR_MASK(RcvVCRCErr) | \
376 ERR_MASK(RcvICRCErr) | ERR_MASK(RcvMinPktLenErr) | \
377 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvLongPktLenErr) | \
378 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvUnexpectedCharErr) | \
379 ERR_MASK(RcvUnsupportedVLErr) | ERR_MASK(RcvEBPErr) | \
380 ERR_MASK(RcvIBFlowErr) | ERR_MASK(RcvBadVersionErr) | \
381 ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) | \
382 ERR_MASK(RcvBadTidErr) | ERR_MASK(RcvHdrLenErr) | \
383 ERR_MASK(RcvHdrErr) | ERR_MASK(RcvIBLostLinkErr) | \
384 ERR_MASK(SendSpecialTriggerErr) | \
385 ERR_MASK(SDmaDisabledErr) | ERR_MASK(SendMinPktLenErr) | \
386 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnderRunErr) | \
387 ERR_MASK(SendPktLenErr) | ERR_MASK(SendDroppedSmpPktErr) | \
388 ERR_MASK(SendDroppedDataPktErr) | \
389 ERR_MASK(SendPioArmLaunchErr) | \
390 ERR_MASK(SendUnexpectedPktNumErr) | \
391 ERR_MASK(SendUnsupportedVLErr) | ERR_MASK(SendBufMisuseErr) | \
392 ERR_MASK(SDmaGenMismatchErr) | ERR_MASK(SDmaOutOfBoundErr) | \
393 ERR_MASK(SDmaTailOutOfBoundErr) | ERR_MASK(SDmaBaseErr) | \
394 ERR_MASK(SDma1stDescErr) | ERR_MASK(SDmaRpyTagErr) | \
395 ERR_MASK(SDmaDwEnErr) | ERR_MASK(SDmaMissingDwErr) | \
396 ERR_MASK(SDmaUnexpDataErr) | \
397 ERR_MASK(IBStatusChanged) | ERR_MASK(InvalidAddrErr) | \
398 ERR_MASK(ResetNegated) | ERR_MASK(HardwareErr) | \
399 ERR_MASK(SDmaDescAddrMisalignErr) | \
400 ERR_MASK(InvalidEEPCmd))
401
402
403#define QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK 0x00000000000000ffULL
404#define QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT 0
405#define QLOGIC_IB_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
406#define QLOGIC_IB_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
407#define QLOGIC_IB_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
408#define QLOGIC_IB_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
409#define QLOGIC_IB_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
410#define QLOGIC_IB_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
411#define QLOGIC_IB_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
412#define QLOGIC_IB_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
413#define QLOGIC_IB_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
414#define QLOGIC_IB_HWE_SERDESPLLFAILED 0x1000000000000000ULL
415
416#define QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR 0x0000000000000040ULL
417#define QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR 0x0000000000000080ULL
418#define QLOGIC_IB_HWE_SDMAMEMREADERR 0x0000000010000000ULL
419#define QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED 0x2000000000000000ULL
420#define QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT 0x0100000000000000ULL
421#define QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT 0x0200000000000000ULL
422#define QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT 0x0400000000000000ULL
423#define QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT 0x0800000000000000ULL
424#define QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR 0x0000008000000000ULL
425#define QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR 0x0000004000000000ULL
426#define QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR 0x0000001000000000ULL
427#define QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR 0x0000002000000000ULL
428
429#define IBA7220_IBCC_LINKCMD_SHIFT 19
430
431
432#define IBA7220_IBC_DLIDLMC_MASK 0xFFFFFFFFUL
433#define IBA7220_IBC_DLIDLMC_SHIFT 32
434
435#define IBA7220_IBC_HRTBT_MASK (SYM_RMASK(IBCDDRCtrl, HRTBT_AUTO) | \
436 SYM_RMASK(IBCDDRCtrl, HRTBT_ENB))
437#define IBA7220_IBC_HRTBT_SHIFT SYM_LSB(IBCDDRCtrl, HRTBT_ENB)
438
439#define IBA7220_IBC_LANE_REV_SUPPORTED (1<<8)
440#define IBA7220_IBC_LREV_MASK 1
441#define IBA7220_IBC_LREV_SHIFT 8
442#define IBA7220_IBC_RXPOL_MASK 1
443#define IBA7220_IBC_RXPOL_SHIFT 7
444#define IBA7220_IBC_WIDTH_SHIFT 5
445#define IBA7220_IBC_WIDTH_MASK 0x3
446#define IBA7220_IBC_WIDTH_1X_ONLY (0 << IBA7220_IBC_WIDTH_SHIFT)
447#define IBA7220_IBC_WIDTH_4X_ONLY (1 << IBA7220_IBC_WIDTH_SHIFT)
448#define IBA7220_IBC_WIDTH_AUTONEG (2 << IBA7220_IBC_WIDTH_SHIFT)
449#define IBA7220_IBC_SPEED_AUTONEG (1 << 1)
450#define IBA7220_IBC_SPEED_SDR (1 << 2)
451#define IBA7220_IBC_SPEED_DDR (1 << 3)
452#define IBA7220_IBC_SPEED_AUTONEG_MASK (0x7 << 1)
453#define IBA7220_IBC_IBTA_1_2_MASK (1)
454
455
456
457#define IBA7220_DDRSTAT_LINKLAT_MASK 0x3ffffff
458
459
460#define QLOGIC_IB_EXTS_FREQSEL 0x2
461#define QLOGIC_IB_EXTS_SERDESSEL 0x4
462#define QLOGIC_IB_EXTS_MEMBIST_ENDTEST 0x0000000000004000
463#define QLOGIC_IB_EXTS_MEMBIST_DISABLED 0x0000000000008000
464
465
466#define QLOGIC_IB_XGXS_RESET 0x5ULL
467#define QLOGIC_IB_XGXS_FC_SAFE (1ULL << 63)
468
469
470#define IBA7220_LEDBLINK_ON_SHIFT 32
471#define IBA7220_LEDBLINK_OFF_SHIFT 0
472
473#define _QIB_GPIO_SDA_NUM 1
474#define _QIB_GPIO_SCL_NUM 0
475#define QIB_TWSI_EEPROM_DEV 0xA2
476#define QIB_TWSI_TEMP_DEV 0x98
477
478
479#define QIB_7220_PSXMITWAIT_CHECK_RATE 4000
480
481#define IBA7220_R_INTRAVAIL_SHIFT 17
482#define IBA7220_R_PKEY_DIS_SHIFT 34
483#define IBA7220_R_TAILUPD_SHIFT 35
484#define IBA7220_R_CTXTCFG_SHIFT 36
485
486#define IBA7220_HDRHEAD_PKTINT_SHIFT 32
487
488
489
490
491
492#define IBA7220_TID_SZ_SHIFT 37
493#define IBA7220_TID_SZ_2K (1UL << IBA7220_TID_SZ_SHIFT)
494#define IBA7220_TID_SZ_4K (2UL << IBA7220_TID_SZ_SHIFT)
495#define IBA7220_TID_PA_SHIFT 11U
496#define PBC_7220_VL15_SEND (1ULL << 63)
497#define PBC_7220_VL15_SEND_CTRL (1ULL << 31)
498
499#define AUTONEG_TRIES 5
500
501
502static u8 rate_to_delay[2][2] = {
503
504 { 8, 2 },
505 { 4, 1 }
506};
507
508static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
509 [IB_RATE_2_5_GBPS] = 8,
510 [IB_RATE_5_GBPS] = 4,
511 [IB_RATE_10_GBPS] = 2,
512 [IB_RATE_20_GBPS] = 1
513};
514
515#define IBA7220_LINKSPEED_SHIFT SYM_LSB(IBCStatus, LinkSpeedActive)
516#define IBA7220_LINKWIDTH_SHIFT SYM_LSB(IBCStatus, LinkWidthActive)
517
518
519#define IB_7220_LT_STATE_DISABLED 0x00
520#define IB_7220_LT_STATE_LINKUP 0x01
521#define IB_7220_LT_STATE_POLLACTIVE 0x02
522#define IB_7220_LT_STATE_POLLQUIET 0x03
523#define IB_7220_LT_STATE_SLEEPDELAY 0x04
524#define IB_7220_LT_STATE_SLEEPQUIET 0x05
525#define IB_7220_LT_STATE_CFGDEBOUNCE 0x08
526#define IB_7220_LT_STATE_CFGRCVFCFG 0x09
527#define IB_7220_LT_STATE_CFGWAITRMT 0x0a
528#define IB_7220_LT_STATE_CFGIDLE 0x0b
529#define IB_7220_LT_STATE_RECOVERRETRAIN 0x0c
530#define IB_7220_LT_STATE_RECOVERWAITRMT 0x0e
531#define IB_7220_LT_STATE_RECOVERIDLE 0x0f
532
533
534#define IB_7220_L_STATE_DOWN 0x0
535#define IB_7220_L_STATE_INIT 0x1
536#define IB_7220_L_STATE_ARM 0x2
537#define IB_7220_L_STATE_ACTIVE 0x3
538#define IB_7220_L_STATE_ACT_DEFER 0x4
539
540static const u8 qib_7220_physportstate[0x20] = {
541 [IB_7220_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
542 [IB_7220_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
543 [IB_7220_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
544 [IB_7220_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
545 [IB_7220_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
546 [IB_7220_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
547 [IB_7220_LT_STATE_CFGDEBOUNCE] =
548 IB_PHYSPORTSTATE_CFG_TRAIN,
549 [IB_7220_LT_STATE_CFGRCVFCFG] =
550 IB_PHYSPORTSTATE_CFG_TRAIN,
551 [IB_7220_LT_STATE_CFGWAITRMT] =
552 IB_PHYSPORTSTATE_CFG_TRAIN,
553 [IB_7220_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_TRAIN,
554 [IB_7220_LT_STATE_RECOVERRETRAIN] =
555 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
556 [IB_7220_LT_STATE_RECOVERWAITRMT] =
557 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
558 [IB_7220_LT_STATE_RECOVERIDLE] =
559 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
560 [0x10] = IB_PHYSPORTSTATE_CFG_TRAIN,
561 [0x11] = IB_PHYSPORTSTATE_CFG_TRAIN,
562 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
563 [0x13] = IB_PHYSPORTSTATE_CFG_TRAIN,
564 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
565 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
566 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
567 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
568};
569
570int qib_special_trigger;
571module_param_named(special_trigger, qib_special_trigger, int, S_IRUGO);
572MODULE_PARM_DESC(special_trigger, "Enable SpecialTrigger arm/launch");
573
574#define IBCBUSFRSPCPARITYERR HWE_MASK(IBCBusFromSPCParityErr)
575#define IBCBUSTOSPCPARITYERR HWE_MASK(IBCBusToSPCParityErr)
576
577#define SYM_MASK_BIT(regname, fldname, bit) ((u64) \
578 (1ULL << (SYM_LSB(regname, fldname) + (bit))))
579
580#define TXEMEMPARITYERR_PIOBUF \
581 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 0)
582#define TXEMEMPARITYERR_PIOPBC \
583 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 1)
584#define TXEMEMPARITYERR_PIOLAUNCHFIFO \
585 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 2)
586
587#define RXEMEMPARITYERR_RCVBUF \
588 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 0)
589#define RXEMEMPARITYERR_LOOKUPQ \
590 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 1)
591#define RXEMEMPARITYERR_EXPTID \
592 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 2)
593#define RXEMEMPARITYERR_EAGERTID \
594 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 3)
595#define RXEMEMPARITYERR_FLAGBUF \
596 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 4)
597#define RXEMEMPARITYERR_DATAINFO \
598 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 5)
599#define RXEMEMPARITYERR_HDRINFO \
600 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 6)
601
602
603static const struct qib_hwerror_msgs qib_7220_hwerror_msgs[] = {
604
605 QLOGIC_IB_HWE_MSG(IBCBUSFRSPCPARITYERR, "QIB2IB Parity"),
606 QLOGIC_IB_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2QIB Parity"),
607
608 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOBUF,
609 "TXE PIOBUF Memory Parity"),
610 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOPBC,
611 "TXE PIOPBC Memory Parity"),
612 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOLAUNCHFIFO,
613 "TXE PIOLAUNCHFIFO Memory Parity"),
614
615 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_RCVBUF,
616 "RXE RCVBUF Memory Parity"),
617 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_LOOKUPQ,
618 "RXE LOOKUPQ Memory Parity"),
619 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EAGERTID,
620 "RXE EAGERTID Memory Parity"),
621 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EXPTID,
622 "RXE EXPTID Memory Parity"),
623 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_FLAGBUF,
624 "RXE FLAGBUF Memory Parity"),
625 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_DATAINFO,
626 "RXE DATAINFO Memory Parity"),
627 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_HDRINFO,
628 "RXE HDRINFO Memory Parity"),
629
630
631 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEPOISONEDTLP,
632 "PCIe Poisoned TLP"),
633 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLTIMEOUT,
634 "PCIe completion timeout"),
635
636
637
638
639
640
641
642 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE1PLLFAILED,
643 "PCIePLL1"),
644 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE0PLLFAILED,
645 "PCIePLL0"),
646 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXTLH,
647 "PCIe XTLH core parity"),
648 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXADM,
649 "PCIe ADM TX core parity"),
650 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYRADM,
651 "PCIe ADM RX core parity"),
652 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SERDESPLLFAILED,
653 "SerDes PLL"),
654 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR,
655 "PCIe cpl header queue"),
656 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR,
657 "PCIe cpl data queue"),
658 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SDMAMEMREADERR,
659 "Send DMA memory read"),
660 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED,
661 "uC PLL clock not locked"),
662 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT,
663 "PCIe serdes Q0 no clock"),
664 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT,
665 "PCIe serdes Q1 no clock"),
666 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT,
667 "PCIe serdes Q2 no clock"),
668 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT,
669 "PCIe serdes Q3 no clock"),
670 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR,
671 "DDS RXEQ memory parity"),
672 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR,
673 "IB uC memory parity"),
674 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR,
675 "PCIe uC oct0 memory parity"),
676 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR,
677 "PCIe uC oct1 memory parity"),
678};
679
680#define RXE_PARITY (RXEMEMPARITYERR_EAGERTID|RXEMEMPARITYERR_EXPTID)
681
682#define QLOGIC_IB_E_PKTERRS (\
683 ERR_MASK(SendPktLenErr) | \
684 ERR_MASK(SendDroppedDataPktErr) | \
685 ERR_MASK(RcvVCRCErr) | \
686 ERR_MASK(RcvICRCErr) | \
687 ERR_MASK(RcvShortPktLenErr) | \
688 ERR_MASK(RcvEBPErr))
689
690
691#define QLOGIC_IB_E_SDMAERRS ( \
692 ERR_MASK(SDmaGenMismatchErr) | \
693 ERR_MASK(SDmaOutOfBoundErr) | \
694 ERR_MASK(SDmaTailOutOfBoundErr) | ERR_MASK(SDmaBaseErr) | \
695 ERR_MASK(SDma1stDescErr) | ERR_MASK(SDmaRpyTagErr) | \
696 ERR_MASK(SDmaDwEnErr) | ERR_MASK(SDmaMissingDwErr) | \
697 ERR_MASK(SDmaUnexpDataErr) | \
698 ERR_MASK(SDmaDescAddrMisalignErr) | \
699 ERR_MASK(SDmaDisabledErr) | \
700 ERR_MASK(SendBufMisuseErr))
701
702
703#define E_SUM_PKTERRS \
704 (ERR_MASK(RcvHdrLenErr) | ERR_MASK(RcvBadTidErr) | \
705 ERR_MASK(RcvBadVersionErr) | ERR_MASK(RcvHdrErr) | \
706 ERR_MASK(RcvLongPktLenErr) | ERR_MASK(RcvShortPktLenErr) | \
707 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
708 ERR_MASK(RcvFormatErr) | ERR_MASK(RcvUnsupportedVLErr) | \
709 ERR_MASK(RcvUnexpectedCharErr) | ERR_MASK(RcvEBPErr))
710
711
712#define E_SUM_ERRS \
713 (ERR_MASK(SendPioArmLaunchErr) | ERR_MASK(SendUnexpectedPktNumErr) | \
714 ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
715 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnsupportedVLErr) | \
716 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
717 ERR_MASK(InvalidAddrErr))
718
719
720
721
722
723
724
725#define E_SPKT_ERRS_IGNORE \
726 (ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
727 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendMinPktLenErr) | \
728 ERR_MASK(SendPktLenErr))
729
730
731
732
733
734
735
736#define E_SUM_LINK_PKTERRS \
737 (ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
738 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
739 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
740 ERR_MASK(RcvUnexpectedCharErr))
741
742static void autoneg_7220_work(struct work_struct *);
743static u32 __iomem *qib_7220_getsendbuf(struct qib_pportdata *, u64, u32 *);
744
745
746
747
748
749
750static void qib_disarm_7220_senderrbufs(struct qib_pportdata *ppd)
751{
752 unsigned long sbuf[3];
753 struct qib_devdata *dd = ppd->dd;
754
755
756
757
758
759
760 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
761 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
762 sbuf[2] = qib_read_kreg64(dd, kr_sendbuffererror + 2);
763
764 if (sbuf[0] || sbuf[1] || sbuf[2])
765 qib_disarm_piobufs_set(dd, sbuf,
766 dd->piobcnt2k + dd->piobcnt4k);
767}
768
769static void qib_7220_txe_recover(struct qib_devdata *dd)
770{
771 qib_devinfo(dd->pcidev, "Recovering from TXE PIO parity error\n");
772 qib_disarm_7220_senderrbufs(dd->pport);
773}
774
775
776
777
778static void qib_7220_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
779{
780 struct qib_devdata *dd = ppd->dd;
781 u64 set_sendctrl = 0;
782 u64 clr_sendctrl = 0;
783
784 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
785 set_sendctrl |= SYM_MASK(SendCtrl, SDmaEnable);
786 else
787 clr_sendctrl |= SYM_MASK(SendCtrl, SDmaEnable);
788
789 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
790 set_sendctrl |= SYM_MASK(SendCtrl, SDmaIntEnable);
791 else
792 clr_sendctrl |= SYM_MASK(SendCtrl, SDmaIntEnable);
793
794 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
795 set_sendctrl |= SYM_MASK(SendCtrl, SDmaHalt);
796 else
797 clr_sendctrl |= SYM_MASK(SendCtrl, SDmaHalt);
798
799 spin_lock(&dd->sendctrl_lock);
800
801 dd->sendctrl |= set_sendctrl;
802 dd->sendctrl &= ~clr_sendctrl;
803
804 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
805 qib_write_kreg(dd, kr_scratch, 0);
806
807 spin_unlock(&dd->sendctrl_lock);
808}
809
810static void qib_decode_7220_sdma_errs(struct qib_pportdata *ppd,
811 u64 err, char *buf, size_t blen)
812{
813 static const struct {
814 u64 err;
815 const char *msg;
816 } errs[] = {
817 { ERR_MASK(SDmaGenMismatchErr),
818 "SDmaGenMismatch" },
819 { ERR_MASK(SDmaOutOfBoundErr),
820 "SDmaOutOfBound" },
821 { ERR_MASK(SDmaTailOutOfBoundErr),
822 "SDmaTailOutOfBound" },
823 { ERR_MASK(SDmaBaseErr),
824 "SDmaBase" },
825 { ERR_MASK(SDma1stDescErr),
826 "SDma1stDesc" },
827 { ERR_MASK(SDmaRpyTagErr),
828 "SDmaRpyTag" },
829 { ERR_MASK(SDmaDwEnErr),
830 "SDmaDwEn" },
831 { ERR_MASK(SDmaMissingDwErr),
832 "SDmaMissingDw" },
833 { ERR_MASK(SDmaUnexpDataErr),
834 "SDmaUnexpData" },
835 { ERR_MASK(SDmaDescAddrMisalignErr),
836 "SDmaDescAddrMisalign" },
837 { ERR_MASK(SendBufMisuseErr),
838 "SendBufMisuse" },
839 { ERR_MASK(SDmaDisabledErr),
840 "SDmaDisabled" },
841 };
842 int i;
843 size_t bidx = 0;
844
845 for (i = 0; i < ARRAY_SIZE(errs); i++) {
846 if (err & errs[i].err)
847 bidx += scnprintf(buf + bidx, blen - bidx,
848 "%s ", errs[i].msg);
849 }
850}
851
852
853
854
855
856static void qib_7220_sdma_hw_clean_up(struct qib_pportdata *ppd)
857{
858
859 sendctrl_7220_mod(ppd, QIB_SENDCTRL_DISARM_ALL | QIB_SENDCTRL_FLUSH |
860 QIB_SENDCTRL_AVAIL_BLIP);
861 ppd->dd->upd_pio_shadow = 1;
862}
863
864static void qib_sdma_7220_setlengen(struct qib_pportdata *ppd)
865{
866
867
868
869
870
871 qib_write_kreg(ppd->dd, kr_senddmalengen, ppd->sdma_descq_cnt);
872 qib_write_kreg(ppd->dd, kr_senddmalengen,
873 ppd->sdma_descq_cnt |
874 (1ULL << QIB_7220_SendDmaLenGen_Generation_MSB));
875}
876
877static void qib_7220_sdma_hw_start_up(struct qib_pportdata *ppd)
878{
879 qib_sdma_7220_setlengen(ppd);
880 qib_sdma_update_7220_tail(ppd, 0);
881 ppd->sdma_head_dma[0] = 0;
882}
883
884#define DISABLES_SDMA ( \
885 ERR_MASK(SDmaDisabledErr) | \
886 ERR_MASK(SDmaBaseErr) | \
887 ERR_MASK(SDmaTailOutOfBoundErr) | \
888 ERR_MASK(SDmaOutOfBoundErr) | \
889 ERR_MASK(SDma1stDescErr) | \
890 ERR_MASK(SDmaRpyTagErr) | \
891 ERR_MASK(SDmaGenMismatchErr) | \
892 ERR_MASK(SDmaDescAddrMisalignErr) | \
893 ERR_MASK(SDmaMissingDwErr) | \
894 ERR_MASK(SDmaDwEnErr))
895
896static void sdma_7220_errors(struct qib_pportdata *ppd, u64 errs)
897{
898 unsigned long flags;
899 struct qib_devdata *dd = ppd->dd;
900 char *msg;
901
902 errs &= QLOGIC_IB_E_SDMAERRS;
903
904 msg = dd->cspec->sdmamsgbuf;
905 qib_decode_7220_sdma_errs(ppd, errs, msg, sizeof dd->cspec->sdmamsgbuf);
906 spin_lock_irqsave(&ppd->sdma_lock, flags);
907
908 if (errs & ERR_MASK(SendBufMisuseErr)) {
909 unsigned long sbuf[3];
910
911 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
912 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
913 sbuf[2] = qib_read_kreg64(dd, kr_sendbuffererror + 2);
914
915 qib_dev_err(ppd->dd,
916 "IB%u:%u SendBufMisuse: %04lx %016lx %016lx\n",
917 ppd->dd->unit, ppd->port, sbuf[2], sbuf[1],
918 sbuf[0]);
919 }
920
921 if (errs & ERR_MASK(SDmaUnexpDataErr))
922 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", ppd->dd->unit,
923 ppd->port);
924
925 switch (ppd->sdma_state.current_state) {
926 case qib_sdma_state_s00_hw_down:
927
928 break;
929
930 case qib_sdma_state_s10_hw_start_up_wait:
931
932 break;
933
934 case qib_sdma_state_s20_idle:
935
936 break;
937
938 case qib_sdma_state_s30_sw_clean_up_wait:
939
940 break;
941
942 case qib_sdma_state_s40_hw_clean_up_wait:
943 if (errs & ERR_MASK(SDmaDisabledErr))
944 __qib_sdma_process_event(ppd,
945 qib_sdma_event_e50_hw_cleaned);
946 break;
947
948 case qib_sdma_state_s50_hw_halt_wait:
949
950 break;
951
952 case qib_sdma_state_s99_running:
953 if (errs & DISABLES_SDMA)
954 __qib_sdma_process_event(ppd,
955 qib_sdma_event_e7220_err_halted);
956 break;
957 }
958
959 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
960}
961
962
963
964
965
966
967
968static int qib_decode_7220_err(struct qib_devdata *dd, char *buf, size_t blen,
969 u64 err)
970{
971 int iserr = 1;
972
973 *buf = '\0';
974 if (err & QLOGIC_IB_E_PKTERRS) {
975 if (!(err & ~QLOGIC_IB_E_PKTERRS))
976 iserr = 0;
977 if ((err & ERR_MASK(RcvICRCErr)) &&
978 !(err & (ERR_MASK(RcvVCRCErr) | ERR_MASK(RcvEBPErr))))
979 strlcat(buf, "CRC ", blen);
980 if (!iserr)
981 goto done;
982 }
983 if (err & ERR_MASK(RcvHdrLenErr))
984 strlcat(buf, "rhdrlen ", blen);
985 if (err & ERR_MASK(RcvBadTidErr))
986 strlcat(buf, "rbadtid ", blen);
987 if (err & ERR_MASK(RcvBadVersionErr))
988 strlcat(buf, "rbadversion ", blen);
989 if (err & ERR_MASK(RcvHdrErr))
990 strlcat(buf, "rhdr ", blen);
991 if (err & ERR_MASK(SendSpecialTriggerErr))
992 strlcat(buf, "sendspecialtrigger ", blen);
993 if (err & ERR_MASK(RcvLongPktLenErr))
994 strlcat(buf, "rlongpktlen ", blen);
995 if (err & ERR_MASK(RcvMaxPktLenErr))
996 strlcat(buf, "rmaxpktlen ", blen);
997 if (err & ERR_MASK(RcvMinPktLenErr))
998 strlcat(buf, "rminpktlen ", blen);
999 if (err & ERR_MASK(SendMinPktLenErr))
1000 strlcat(buf, "sminpktlen ", blen);
1001 if (err & ERR_MASK(RcvFormatErr))
1002 strlcat(buf, "rformaterr ", blen);
1003 if (err & ERR_MASK(RcvUnsupportedVLErr))
1004 strlcat(buf, "runsupvl ", blen);
1005 if (err & ERR_MASK(RcvUnexpectedCharErr))
1006 strlcat(buf, "runexpchar ", blen);
1007 if (err & ERR_MASK(RcvIBFlowErr))
1008 strlcat(buf, "ribflow ", blen);
1009 if (err & ERR_MASK(SendUnderRunErr))
1010 strlcat(buf, "sunderrun ", blen);
1011 if (err & ERR_MASK(SendPioArmLaunchErr))
1012 strlcat(buf, "spioarmlaunch ", blen);
1013 if (err & ERR_MASK(SendUnexpectedPktNumErr))
1014 strlcat(buf, "sunexperrpktnum ", blen);
1015 if (err & ERR_MASK(SendDroppedSmpPktErr))
1016 strlcat(buf, "sdroppedsmppkt ", blen);
1017 if (err & ERR_MASK(SendMaxPktLenErr))
1018 strlcat(buf, "smaxpktlen ", blen);
1019 if (err & ERR_MASK(SendUnsupportedVLErr))
1020 strlcat(buf, "sunsupVL ", blen);
1021 if (err & ERR_MASK(InvalidAddrErr))
1022 strlcat(buf, "invalidaddr ", blen);
1023 if (err & ERR_MASK(RcvEgrFullErr))
1024 strlcat(buf, "rcvegrfull ", blen);
1025 if (err & ERR_MASK(RcvHdrFullErr))
1026 strlcat(buf, "rcvhdrfull ", blen);
1027 if (err & ERR_MASK(IBStatusChanged))
1028 strlcat(buf, "ibcstatuschg ", blen);
1029 if (err & ERR_MASK(RcvIBLostLinkErr))
1030 strlcat(buf, "riblostlink ", blen);
1031 if (err & ERR_MASK(HardwareErr))
1032 strlcat(buf, "hardware ", blen);
1033 if (err & ERR_MASK(ResetNegated))
1034 strlcat(buf, "reset ", blen);
1035 if (err & QLOGIC_IB_E_SDMAERRS)
1036 qib_decode_7220_sdma_errs(dd->pport, err, buf, blen);
1037 if (err & ERR_MASK(InvalidEEPCmd))
1038 strlcat(buf, "invalideepromcmd ", blen);
1039done:
1040 return iserr;
1041}
1042
1043static void reenable_7220_chase(unsigned long opaque)
1044{
1045 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1046 ppd->cpspec->chase_timer.expires = 0;
1047 qib_set_ib_7220_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1048 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1049}
1050
1051static void handle_7220_chase(struct qib_pportdata *ppd, u64 ibcst)
1052{
1053 u8 ibclt;
1054 unsigned long tnow;
1055
1056 ibclt = (u8)SYM_FIELD(ibcst, IBCStatus, LinkTrainingState);
1057
1058
1059
1060
1061
1062
1063
1064 switch (ibclt) {
1065 case IB_7220_LT_STATE_CFGRCVFCFG:
1066 case IB_7220_LT_STATE_CFGWAITRMT:
1067 case IB_7220_LT_STATE_TXREVLANES:
1068 case IB_7220_LT_STATE_CFGENH:
1069 tnow = jiffies;
1070 if (ppd->cpspec->chase_end &&
1071 time_after(tnow, ppd->cpspec->chase_end)) {
1072 ppd->cpspec->chase_end = 0;
1073 qib_set_ib_7220_lstate(ppd,
1074 QLOGIC_IB_IBCC_LINKCMD_DOWN,
1075 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1076 ppd->cpspec->chase_timer.expires = jiffies +
1077 QIB_CHASE_DIS_TIME;
1078 add_timer(&ppd->cpspec->chase_timer);
1079 } else if (!ppd->cpspec->chase_end)
1080 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1081 break;
1082
1083 default:
1084 ppd->cpspec->chase_end = 0;
1085 break;
1086 }
1087}
1088
1089static void handle_7220_errors(struct qib_devdata *dd, u64 errs)
1090{
1091 char *msg;
1092 u64 ignore_this_time = 0;
1093 u64 iserr = 0;
1094 int log_idx;
1095 struct qib_pportdata *ppd = dd->pport;
1096 u64 mask;
1097
1098
1099 errs &= dd->cspec->errormask;
1100 msg = dd->cspec->emsgbuf;
1101
1102
1103 if (errs & ERR_MASK(HardwareErr))
1104 qib_7220_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1105 else
1106 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1107 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1108 qib_inc_eeprom_err(dd, log_idx, 1);
1109
1110 if (errs & QLOGIC_IB_E_SDMAERRS)
1111 sdma_7220_errors(ppd, errs);
1112
1113 if (errs & ~IB_E_BITSEXTANT)
1114 qib_dev_err(dd,
1115 "error interrupt with unknown errors %llx set\n",
1116 (unsigned long long) (errs & ~IB_E_BITSEXTANT));
1117
1118 if (errs & E_SUM_ERRS) {
1119 qib_disarm_7220_senderrbufs(ppd);
1120 if ((errs & E_SUM_LINK_PKTERRS) &&
1121 !(ppd->lflags & QIBL_LINKACTIVE)) {
1122
1123
1124
1125
1126
1127
1128
1129 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1130 }
1131 } else if ((errs & E_SUM_LINK_PKTERRS) &&
1132 !(ppd->lflags & QIBL_LINKACTIVE)) {
1133
1134
1135
1136
1137
1138
1139
1140 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1141 }
1142
1143 qib_write_kreg(dd, kr_errclear, errs);
1144
1145 errs &= ~ignore_this_time;
1146 if (!errs)
1147 goto done;
1148
1149
1150
1151
1152
1153
1154 mask = ERR_MASK(IBStatusChanged) |
1155 ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) |
1156 ERR_MASK(HardwareErr) | ERR_MASK(SDmaDisabledErr);
1157
1158 qib_decode_7220_err(dd, msg, sizeof dd->cspec->emsgbuf, errs & ~mask);
1159
1160 if (errs & E_SUM_PKTERRS)
1161 qib_stats.sps_rcverrs++;
1162 if (errs & E_SUM_ERRS)
1163 qib_stats.sps_txerrs++;
1164 iserr = errs & ~(E_SUM_PKTERRS | QLOGIC_IB_E_PKTERRS |
1165 ERR_MASK(SDmaDisabledErr));
1166
1167 if (errs & ERR_MASK(IBStatusChanged)) {
1168 u64 ibcs;
1169
1170 ibcs = qib_read_kreg64(dd, kr_ibcstatus);
1171 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1172 handle_7220_chase(ppd, ibcs);
1173
1174
1175 ppd->link_width_active =
1176 ((ibcs >> IBA7220_LINKWIDTH_SHIFT) & 1) ?
1177 IB_WIDTH_4X : IB_WIDTH_1X;
1178 ppd->link_speed_active =
1179 ((ibcs >> IBA7220_LINKSPEED_SHIFT) & 1) ?
1180 QIB_IB_DDR : QIB_IB_SDR;
1181
1182
1183
1184
1185
1186
1187
1188
1189 if (qib_7220_phys_portstate(ibcs) !=
1190 IB_PHYSPORTSTATE_LINK_ERR_RECOVER)
1191 qib_handle_e_ibstatuschanged(ppd, ibcs);
1192 }
1193
1194 if (errs & ERR_MASK(ResetNegated)) {
1195 qib_dev_err(dd,
1196 "Got reset, requires re-init (unload and reload driver)\n");
1197 dd->flags &= ~QIB_INITTED;
1198
1199 *dd->devstatusp |= QIB_STATUS_HWERROR;
1200 *dd->pport->statusp &= ~QIB_STATUS_IB_CONF;
1201 }
1202
1203 if (*msg && iserr)
1204 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1205
1206 if (ppd->state_wanted & ppd->lflags)
1207 wake_up_interruptible(&ppd->state_wait);
1208
1209
1210
1211
1212
1213
1214
1215
1216 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1217 qib_handle_urcv(dd, ~0U);
1218 if (errs & ERR_MASK(RcvEgrFullErr))
1219 qib_stats.sps_buffull++;
1220 else
1221 qib_stats.sps_hdrfull++;
1222 }
1223done:
1224 return;
1225}
1226
1227
1228static void qib_7220_set_intr_state(struct qib_devdata *dd, u32 enable)
1229{
1230 if (enable) {
1231 if (dd->flags & QIB_BADINTR)
1232 return;
1233 qib_write_kreg(dd, kr_intmask, ~0ULL);
1234
1235 qib_write_kreg(dd, kr_intclear, 0ULL);
1236 } else
1237 qib_write_kreg(dd, kr_intmask, 0ULL);
1238}
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255static void qib_7220_clear_freeze(struct qib_devdata *dd)
1256{
1257
1258 qib_write_kreg(dd, kr_errmask, 0ULL);
1259
1260
1261 qib_7220_set_intr_state(dd, 0);
1262
1263 qib_cancel_sends(dd->pport);
1264
1265
1266 qib_write_kreg(dd, kr_control, dd->control);
1267 qib_read_kreg32(dd, kr_scratch);
1268
1269
1270 qib_force_pio_avail_update(dd);
1271
1272
1273
1274
1275
1276
1277
1278 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1279 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1280 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1281 qib_7220_set_intr_state(dd, 1);
1282}
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295static void qib_7220_handle_hwerrors(struct qib_devdata *dd, char *msg,
1296 size_t msgl)
1297{
1298 u64 hwerrs;
1299 u32 bits, ctrl;
1300 int isfatal = 0;
1301 char *bitsmsg;
1302 int log_idx;
1303
1304 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
1305 if (!hwerrs)
1306 goto bail;
1307 if (hwerrs == ~0ULL) {
1308 qib_dev_err(dd,
1309 "Read of hardware error status failed (all bits set); ignoring\n");
1310 goto bail;
1311 }
1312 qib_stats.sps_hwerrs++;
1313
1314
1315
1316
1317
1318
1319
1320
1321 qib_write_kreg(dd, kr_hwerrclear,
1322 hwerrs & ~HWE_MASK(PowerOnBISTFailed));
1323
1324 hwerrs &= dd->cspec->hwerrmask;
1325
1326
1327 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1328 if (hwerrs & dd->eep_st_masks[log_idx].hwerrs_to_log)
1329 qib_inc_eeprom_err(dd, log_idx, 1);
1330 if (hwerrs & ~(TXEMEMPARITYERR_PIOBUF | TXEMEMPARITYERR_PIOPBC |
1331 RXE_PARITY))
1332 qib_devinfo(dd->pcidev,
1333 "Hardware error: hwerr=0x%llx (cleared)\n",
1334 (unsigned long long) hwerrs);
1335
1336 if (hwerrs & ~IB_HWE_BITSEXTANT)
1337 qib_dev_err(dd,
1338 "hwerror interrupt with unknown errors %llx set\n",
1339 (unsigned long long) (hwerrs & ~IB_HWE_BITSEXTANT));
1340
1341 if (hwerrs & QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR)
1342 qib_sd7220_clr_ibpar(dd);
1343
1344 ctrl = qib_read_kreg32(dd, kr_control);
1345 if ((ctrl & QLOGIC_IB_C_FREEZEMODE) && !dd->diag_client) {
1346
1347
1348
1349
1350 if (hwerrs & (TXEMEMPARITYERR_PIOBUF |
1351 TXEMEMPARITYERR_PIOPBC)) {
1352 qib_7220_txe_recover(dd);
1353 hwerrs &= ~(TXEMEMPARITYERR_PIOBUF |
1354 TXEMEMPARITYERR_PIOPBC);
1355 }
1356 if (hwerrs)
1357 isfatal = 1;
1358 else
1359 qib_7220_clear_freeze(dd);
1360 }
1361
1362 *msg = '\0';
1363
1364 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
1365 isfatal = 1;
1366 strlcat(msg,
1367 "[Memory BIST test failed, InfiniPath hardware unusable]",
1368 msgl);
1369
1370 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
1371 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1372 }
1373
1374 qib_format_hwerrors(hwerrs, qib_7220_hwerror_msgs,
1375 ARRAY_SIZE(qib_7220_hwerror_msgs), msg, msgl);
1376
1377 bitsmsg = dd->cspec->bitsmsgbuf;
1378 if (hwerrs & (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK <<
1379 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT)) {
1380 bits = (u32) ((hwerrs >>
1381 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) &
1382 QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK);
1383 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
1384 "[PCIe Mem Parity Errs %x] ", bits);
1385 strlcat(msg, bitsmsg, msgl);
1386 }
1387
1388#define _QIB_PLL_FAIL (QLOGIC_IB_HWE_COREPLL_FBSLIP | \
1389 QLOGIC_IB_HWE_COREPLL_RFSLIP)
1390
1391 if (hwerrs & _QIB_PLL_FAIL) {
1392 isfatal = 1;
1393 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
1394 "[PLL failed (%llx), InfiniPath hardware unusable]",
1395 (unsigned long long) hwerrs & _QIB_PLL_FAIL);
1396 strlcat(msg, bitsmsg, msgl);
1397
1398 dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL);
1399 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1400 }
1401
1402 if (hwerrs & QLOGIC_IB_HWE_SERDESPLLFAILED) {
1403
1404
1405
1406
1407 dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED;
1408 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1409 }
1410
1411 qib_dev_err(dd, "%s hardware error\n", msg);
1412
1413 if (isfatal && !dd->diag_client) {
1414 qib_dev_err(dd,
1415 "Fatal Hardware Error, no longer usable, SN %.16s\n",
1416 dd->serial);
1417
1418
1419
1420
1421 if (dd->freezemsg)
1422 snprintf(dd->freezemsg, dd->freezelen,
1423 "{%s}", msg);
1424 qib_disable_after_error(dd);
1425 }
1426bail:;
1427}
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439static void qib_7220_init_hwerrors(struct qib_devdata *dd)
1440{
1441 u64 val;
1442 u64 extsval;
1443
1444 extsval = qib_read_kreg64(dd, kr_extstatus);
1445
1446 if (!(extsval & (QLOGIC_IB_EXTS_MEMBIST_ENDTEST |
1447 QLOGIC_IB_EXTS_MEMBIST_DISABLED)))
1448 qib_dev_err(dd, "MemBIST did not complete!\n");
1449 if (extsval & QLOGIC_IB_EXTS_MEMBIST_DISABLED)
1450 qib_devinfo(dd->pcidev, "MemBIST is disabled.\n");
1451
1452 val = ~0ULL;
1453
1454 val &= ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR;
1455 dd->cspec->hwerrmask = val;
1456
1457 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
1458 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1459
1460
1461 qib_write_kreg(dd, kr_errclear, ~0ULL);
1462
1463 qib_write_kreg(dd, kr_errmask, ~0ULL);
1464 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
1465
1466 qib_write_kreg(dd, kr_intclear, ~0ULL);
1467}
1468
1469
1470
1471
1472
1473
1474
1475static void qib_set_7220_armlaunch(struct qib_devdata *dd, u32 enable)
1476{
1477 if (enable) {
1478 qib_write_kreg(dd, kr_errclear, ERR_MASK(SendPioArmLaunchErr));
1479 dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr);
1480 } else
1481 dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr);
1482 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1483}
1484
1485
1486
1487
1488
1489
1490static void qib_set_ib_7220_lstate(struct qib_pportdata *ppd, u16 linkcmd,
1491 u16 linitcmd)
1492{
1493 u64 mod_wd;
1494 struct qib_devdata *dd = ppd->dd;
1495 unsigned long flags;
1496
1497 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
1498
1499
1500
1501
1502 spin_lock_irqsave(&ppd->lflags_lock, flags);
1503 ppd->lflags |= QIBL_IB_LINK_DISABLED;
1504 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1505 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
1506
1507
1508
1509
1510
1511 spin_lock_irqsave(&ppd->lflags_lock, flags);
1512 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
1513 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1514 }
1515
1516 mod_wd = (linkcmd << IBA7220_IBCC_LINKCMD_SHIFT) |
1517 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1518
1519 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl | mod_wd);
1520
1521 qib_write_kreg(dd, kr_scratch, 0);
1522}
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535static int qib_7220_bringup_serdes(struct qib_pportdata *ppd)
1536{
1537 struct qib_devdata *dd = ppd->dd;
1538 u64 val, prev_val, guid, ibc;
1539 int ret = 0;
1540
1541
1542 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1543 qib_write_kreg(dd, kr_control, 0ULL);
1544
1545 if (qib_compat_ddr_negotiate) {
1546 ppd->cpspec->ibdeltainprog = 1;
1547 ppd->cpspec->ibsymsnap = read_7220_creg32(dd, cr_ibsymbolerr);
1548 ppd->cpspec->iblnkerrsnap =
1549 read_7220_creg32(dd, cr_iblinkerrrecov);
1550 }
1551
1552
1553 ibc = 0x5ULL << SYM_LSB(IBCCtrl, FlowCtrlWaterMark);
1554
1555
1556
1557
1558
1559 ibc |= 0x3ULL << SYM_LSB(IBCCtrl, FlowCtrlPeriod);
1560
1561 ibc |= 0xfULL << SYM_LSB(IBCCtrl, PhyerrThreshold);
1562
1563 ibc |= 4ULL << SYM_LSB(IBCCtrl, CreditScale);
1564
1565 ibc |= 0xfULL << SYM_LSB(IBCCtrl, OverrunThreshold);
1566
1567
1568
1569
1570 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << SYM_LSB(IBCCtrl, MaxPktLen);
1571 ppd->cpspec->ibcctrl = ibc;
1572
1573
1574 val = ppd->cpspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
1575 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1576 qib_write_kreg(dd, kr_ibcctrl, val);
1577
1578 if (!ppd->cpspec->ibcddrctrl) {
1579
1580 ppd->cpspec->ibcddrctrl = qib_read_kreg64(dd, kr_ibcddrctrl);
1581
1582 if (ppd->link_speed_enabled == (QIB_IB_SDR | QIB_IB_DDR))
1583 ppd->cpspec->ibcddrctrl |=
1584 IBA7220_IBC_SPEED_AUTONEG_MASK |
1585 IBA7220_IBC_IBTA_1_2_MASK;
1586 else
1587 ppd->cpspec->ibcddrctrl |=
1588 ppd->link_speed_enabled == QIB_IB_DDR ?
1589 IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
1590 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
1591 (IB_WIDTH_1X | IB_WIDTH_4X))
1592 ppd->cpspec->ibcddrctrl |= IBA7220_IBC_WIDTH_AUTONEG;
1593 else
1594 ppd->cpspec->ibcddrctrl |=
1595 ppd->link_width_enabled == IB_WIDTH_4X ?
1596 IBA7220_IBC_WIDTH_4X_ONLY :
1597 IBA7220_IBC_WIDTH_1X_ONLY;
1598
1599
1600 ppd->cpspec->ibcddrctrl |=
1601 IBA7220_IBC_RXPOL_MASK << IBA7220_IBC_RXPOL_SHIFT;
1602 ppd->cpspec->ibcddrctrl |=
1603 IBA7220_IBC_HRTBT_MASK << IBA7220_IBC_HRTBT_SHIFT;
1604
1605
1606 ppd->cpspec->ibcddrctrl |= IBA7220_IBC_LANE_REV_SUPPORTED;
1607 } else
1608
1609 qib_write_kreg(dd, kr_scratch, 0);
1610
1611 qib_write_kreg(dd, kr_ibcddrctrl, ppd->cpspec->ibcddrctrl);
1612 qib_write_kreg(dd, kr_scratch, 0);
1613
1614 qib_write_kreg(dd, kr_ncmodectrl, 0Ull);
1615 qib_write_kreg(dd, kr_scratch, 0);
1616
1617 ret = qib_sd7220_init(dd);
1618
1619 val = qib_read_kreg64(dd, kr_xgxs_cfg);
1620 prev_val = val;
1621 val |= QLOGIC_IB_XGXS_FC_SAFE;
1622 if (val != prev_val) {
1623 qib_write_kreg(dd, kr_xgxs_cfg, val);
1624 qib_read_kreg32(dd, kr_scratch);
1625 }
1626 if (val & QLOGIC_IB_XGXS_RESET)
1627 val &= ~QLOGIC_IB_XGXS_RESET;
1628 if (val != prev_val)
1629 qib_write_kreg(dd, kr_xgxs_cfg, val);
1630
1631
1632 if (!ppd->guid)
1633 ppd->guid = dd->base_guid;
1634 guid = be64_to_cpu(ppd->guid);
1635
1636 qib_write_kreg(dd, kr_hrtbt_guid, guid);
1637 if (!ret) {
1638 dd->control |= QLOGIC_IB_C_LINKENABLE;
1639 qib_write_kreg(dd, kr_control, dd->control);
1640 } else
1641
1642 qib_write_kreg(dd, kr_scratch, 0);
1643 return ret;
1644}
1645
1646
1647
1648
1649
1650
1651static void qib_7220_quiet_serdes(struct qib_pportdata *ppd)
1652{
1653 u64 val;
1654 struct qib_devdata *dd = ppd->dd;
1655 unsigned long flags;
1656
1657
1658 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1659 qib_write_kreg(dd, kr_control,
1660 dd->control | QLOGIC_IB_C_FREEZEMODE);
1661
1662 ppd->cpspec->chase_end = 0;
1663 if (ppd->cpspec->chase_timer.data)
1664 del_timer_sync(&ppd->cpspec->chase_timer);
1665
1666 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
1667 ppd->cpspec->ibdeltainprog) {
1668 u64 diagc;
1669
1670
1671 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
1672 qib_write_kreg(dd, kr_hwdiagctrl,
1673 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
1674
1675 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
1676 val = read_7220_creg32(dd, cr_ibsymbolerr);
1677 if (ppd->cpspec->ibdeltainprog)
1678 val -= val - ppd->cpspec->ibsymsnap;
1679 val -= ppd->cpspec->ibsymdelta;
1680 write_7220_creg(dd, cr_ibsymbolerr, val);
1681 }
1682 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
1683 val = read_7220_creg32(dd, cr_iblinkerrrecov);
1684 if (ppd->cpspec->ibdeltainprog)
1685 val -= val - ppd->cpspec->iblnkerrsnap;
1686 val -= ppd->cpspec->iblnkerrdelta;
1687 write_7220_creg(dd, cr_iblinkerrrecov, val);
1688 }
1689
1690
1691 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
1692 }
1693 qib_set_ib_7220_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1694
1695 spin_lock_irqsave(&ppd->lflags_lock, flags);
1696 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
1697 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1698 wake_up(&ppd->cpspec->autoneg_wait);
1699 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
1700
1701 shutdown_7220_relock_poll(ppd->dd);
1702 val = qib_read_kreg64(ppd->dd, kr_xgxs_cfg);
1703 val |= QLOGIC_IB_XGXS_RESET;
1704 qib_write_kreg(ppd->dd, kr_xgxs_cfg, val);
1705}
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730static void qib_setup_7220_setextled(struct qib_pportdata *ppd, u32 on)
1731{
1732 struct qib_devdata *dd = ppd->dd;
1733 u64 extctl, ledblink = 0, val, lst, ltst;
1734 unsigned long flags;
1735
1736
1737
1738
1739
1740 if (dd->diag_client)
1741 return;
1742
1743 if (ppd->led_override) {
1744 ltst = (ppd->led_override & QIB_LED_PHYS) ?
1745 IB_PHYSPORTSTATE_LINKUP : IB_PHYSPORTSTATE_DISABLED,
1746 lst = (ppd->led_override & QIB_LED_LOG) ?
1747 IB_PORT_ACTIVE : IB_PORT_DOWN;
1748 } else if (on) {
1749 val = qib_read_kreg64(dd, kr_ibcstatus);
1750 ltst = qib_7220_phys_portstate(val);
1751 lst = qib_7220_iblink_state(val);
1752 } else {
1753 ltst = 0;
1754 lst = 0;
1755 }
1756
1757 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
1758 extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) |
1759 SYM_MASK(EXTCtrl, LEDPriPortYellowOn));
1760 if (ltst == IB_PHYSPORTSTATE_LINKUP) {
1761 extctl |= SYM_MASK(EXTCtrl, LEDPriPortGreenOn);
1762
1763
1764
1765
1766
1767 ledblink = ((66600 * 1000UL / 4) << IBA7220_LEDBLINK_ON_SHIFT)
1768 | ((187500 * 1000UL / 4) << IBA7220_LEDBLINK_OFF_SHIFT);
1769 }
1770 if (lst == IB_PORT_ACTIVE)
1771 extctl |= SYM_MASK(EXTCtrl, LEDPriPortYellowOn);
1772 dd->cspec->extctrl = extctl;
1773 qib_write_kreg(dd, kr_extctrl, extctl);
1774 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
1775
1776 if (ledblink)
1777 qib_write_kreg(dd, kr_rcvpktledcnt, ledblink);
1778}
1779
1780static void qib_7220_free_irq(struct qib_devdata *dd)
1781{
1782 if (dd->cspec->irq) {
1783 free_irq(dd->cspec->irq, dd);
1784 dd->cspec->irq = 0;
1785 }
1786 qib_nomsi(dd);
1787}
1788
1789
1790
1791
1792
1793
1794
1795
1796static void qib_setup_7220_cleanup(struct qib_devdata *dd)
1797{
1798 qib_7220_free_irq(dd);
1799 kfree(dd->cspec->cntrs);
1800 kfree(dd->cspec->portcntrs);
1801}
1802
1803
1804
1805
1806
1807static void sdma_7220_intr(struct qib_pportdata *ppd, u64 istat)
1808{
1809 unsigned long flags;
1810
1811 spin_lock_irqsave(&ppd->sdma_lock, flags);
1812
1813 switch (ppd->sdma_state.current_state) {
1814 case qib_sdma_state_s00_hw_down:
1815 break;
1816
1817 case qib_sdma_state_s10_hw_start_up_wait:
1818 __qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
1819 break;
1820
1821 case qib_sdma_state_s20_idle:
1822 break;
1823
1824 case qib_sdma_state_s30_sw_clean_up_wait:
1825 break;
1826
1827 case qib_sdma_state_s40_hw_clean_up_wait:
1828 break;
1829
1830 case qib_sdma_state_s50_hw_halt_wait:
1831 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1832 break;
1833
1834 case qib_sdma_state_s99_running:
1835
1836 __qib_sdma_intr(ppd);
1837 break;
1838 }
1839 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1840}
1841
1842static void qib_wantpiobuf_7220_intr(struct qib_devdata *dd, u32 needint)
1843{
1844 unsigned long flags;
1845
1846 spin_lock_irqsave(&dd->sendctrl_lock, flags);
1847 if (needint) {
1848 if (!(dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
1849 goto done;
1850
1851
1852
1853
1854
1855 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl &
1856 ~SYM_MASK(SendCtrl, SendBufAvailUpd));
1857 qib_write_kreg(dd, kr_scratch, 0ULL);
1858 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
1859 } else
1860 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
1861 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
1862 qib_write_kreg(dd, kr_scratch, 0ULL);
1863done:
1864 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
1865}
1866
1867
1868
1869
1870
1871static noinline void unlikely_7220_intr(struct qib_devdata *dd, u64 istat)
1872{
1873 if (unlikely(istat & ~QLOGIC_IB_I_BITSEXTANT))
1874 qib_dev_err(dd,
1875 "interrupt with unknown interrupts %Lx set\n",
1876 istat & ~QLOGIC_IB_I_BITSEXTANT);
1877
1878 if (istat & QLOGIC_IB_I_GPIO) {
1879 u32 gpiostatus;
1880
1881
1882
1883
1884
1885
1886
1887
1888 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
1889
1890
1891
1892
1893
1894
1895
1896 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
1897
1898 if (gpiostatus) {
1899 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
1900 u32 gpio_irq = mask & gpiostatus;
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913 dd->cspec->gpio_mask &= ~gpio_irq;
1914 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1915 }
1916 }
1917
1918 if (istat & QLOGIC_IB_I_ERROR) {
1919 u64 estat;
1920
1921 qib_stats.sps_errints++;
1922 estat = qib_read_kreg64(dd, kr_errstatus);
1923 if (!estat)
1924 qib_devinfo(dd->pcidev,
1925 "error interrupt (%Lx), but no error bits set!\n",
1926 istat);
1927 else
1928 handle_7220_errors(dd, estat);
1929 }
1930}
1931
1932static irqreturn_t qib_7220intr(int irq, void *data)
1933{
1934 struct qib_devdata *dd = data;
1935 irqreturn_t ret;
1936 u64 istat;
1937 u64 ctxtrbits;
1938 u64 rmask;
1939 unsigned i;
1940
1941 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
1942
1943
1944
1945
1946
1947
1948 ret = IRQ_HANDLED;
1949 goto bail;
1950 }
1951
1952 istat = qib_read_kreg64(dd, kr_intstatus);
1953
1954 if (unlikely(!istat)) {
1955 ret = IRQ_NONE;
1956 goto bail;
1957 }
1958 if (unlikely(istat == -1)) {
1959 qib_bad_intrstatus(dd);
1960
1961 ret = IRQ_NONE;
1962 goto bail;
1963 }
1964
1965 qib_stats.sps_ints++;
1966 if (dd->int_counter != (u32) -1)
1967 dd->int_counter++;
1968
1969 if (unlikely(istat & (~QLOGIC_IB_I_BITSEXTANT |
1970 QLOGIC_IB_I_GPIO | QLOGIC_IB_I_ERROR)))
1971 unlikely_7220_intr(dd, istat);
1972
1973
1974
1975
1976
1977
1978
1979 qib_write_kreg(dd, kr_intclear, istat);
1980
1981
1982
1983
1984
1985
1986 ctxtrbits = istat &
1987 ((QLOGIC_IB_I_RCVAVAIL_MASK << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1988 (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT));
1989 if (ctxtrbits) {
1990 rmask = (1ULL << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1991 (1ULL << QLOGIC_IB_I_RCVURG_SHIFT);
1992 for (i = 0; i < dd->first_user_ctxt; i++) {
1993 if (ctxtrbits & rmask) {
1994 ctxtrbits &= ~rmask;
1995 qib_kreceive(dd->rcd[i], NULL, NULL);
1996 }
1997 rmask <<= 1;
1998 }
1999 if (ctxtrbits) {
2000 ctxtrbits =
2001 (ctxtrbits >> QLOGIC_IB_I_RCVAVAIL_SHIFT) |
2002 (ctxtrbits >> QLOGIC_IB_I_RCVURG_SHIFT);
2003 qib_handle_urcv(dd, ctxtrbits);
2004 }
2005 }
2006
2007
2008 if (istat & QLOGIC_IB_I_SDMAINT)
2009 sdma_7220_intr(dd->pport, istat);
2010
2011 if ((istat & QLOGIC_IB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2012 qib_ib_piobufavail(dd);
2013
2014 ret = IRQ_HANDLED;
2015bail:
2016 return ret;
2017}
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027static void qib_setup_7220_interrupt(struct qib_devdata *dd)
2028{
2029 if (!dd->cspec->irq)
2030 qib_dev_err(dd,
2031 "irq is 0, BIOS error? Interrupts won't work\n");
2032 else {
2033 int ret = request_irq(dd->cspec->irq, qib_7220intr,
2034 dd->msi_lo ? 0 : IRQF_SHARED,
2035 QIB_DRV_NAME, dd);
2036
2037 if (ret)
2038 qib_dev_err(dd,
2039 "Couldn't setup %s interrupt (irq=%d): %d\n",
2040 dd->msi_lo ? "MSI" : "INTx",
2041 dd->cspec->irq, ret);
2042 }
2043}
2044
2045
2046
2047
2048
2049
2050
2051static void qib_7220_boardname(struct qib_devdata *dd)
2052{
2053 char *n;
2054 u32 boardid, namelen;
2055
2056 boardid = SYM_FIELD(dd->revision, Revision,
2057 BoardID);
2058
2059 switch (boardid) {
2060 case 1:
2061 n = "InfiniPath_QLE7240";
2062 break;
2063 case 2:
2064 n = "InfiniPath_QLE7280";
2065 break;
2066 default:
2067 qib_dev_err(dd, "Unknown 7220 board with ID %u\n", boardid);
2068 n = "Unknown_InfiniPath_7220";
2069 break;
2070 }
2071
2072 namelen = strlen(n) + 1;
2073 dd->boardname = kmalloc(namelen, GFP_KERNEL);
2074 if (!dd->boardname)
2075 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
2076 else
2077 snprintf(dd->boardname, namelen, "%s", n);
2078
2079 if (dd->majrev != 5 || !dd->minrev || dd->minrev > 2)
2080 qib_dev_err(dd,
2081 "Unsupported InfiniPath hardware revision %u.%u!\n",
2082 dd->majrev, dd->minrev);
2083
2084 snprintf(dd->boardversion, sizeof(dd->boardversion),
2085 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
2086 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
2087 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
2088 dd->majrev, dd->minrev,
2089 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
2090}
2091
2092
2093
2094
2095
2096static int qib_setup_7220_reset(struct qib_devdata *dd)
2097{
2098 u64 val;
2099 int i;
2100 int ret;
2101 u16 cmdval;
2102 u8 int_line, clinesz;
2103 unsigned long flags;
2104
2105 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
2106
2107
2108 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
2109
2110
2111 qib_7220_set_intr_state(dd, 0);
2112
2113 dd->pport->cpspec->ibdeltainprog = 0;
2114 dd->pport->cpspec->ibsymdelta = 0;
2115 dd->pport->cpspec->iblnkerrdelta = 0;
2116
2117
2118
2119
2120
2121
2122 dd->flags &= ~(QIB_INITTED | QIB_PRESENT);
2123 dd->int_counter = 0;
2124 val = dd->control | QLOGIC_IB_C_RESET;
2125 writeq(val, &dd->kregbase[kr_control]);
2126 mb();
2127
2128 for (i = 1; i <= 5; i++) {
2129
2130
2131
2132
2133
2134 msleep(1000 + (1 + i) * 2000);
2135
2136 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
2137
2138
2139
2140
2141
2142 val = readq(&dd->kregbase[kr_revision]);
2143 if (val == dd->revision) {
2144 dd->flags |= QIB_PRESENT;
2145 ret = qib_reinit_intr(dd);
2146 goto bail;
2147 }
2148 }
2149 ret = 0;
2150
2151bail:
2152 if (ret) {
2153 if (qib_pcie_params(dd, dd->lbus_width, NULL, NULL))
2154 qib_dev_err(dd,
2155 "Reset failed to setup PCIe or interrupts; continuing anyway\n");
2156
2157
2158 qib_write_kreg(dd, kr_control, 0ULL);
2159
2160
2161 qib_7220_init_hwerrors(dd);
2162
2163
2164 if (dd->pport->cpspec->ibcddrctrl & IBA7220_IBC_IBTA_1_2_MASK)
2165 dd->cspec->presets_needed = 1;
2166 spin_lock_irqsave(&dd->pport->lflags_lock, flags);
2167 dd->pport->lflags |= QIBL_IB_FORCE_NOTIFY;
2168 dd->pport->lflags &= ~QIBL_IB_AUTONEG_FAILED;
2169 spin_unlock_irqrestore(&dd->pport->lflags_lock, flags);
2170 }
2171
2172 return ret;
2173}
2174
2175
2176
2177
2178
2179
2180
2181
2182static void qib_7220_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
2183 u32 type, unsigned long pa)
2184{
2185 if (pa != dd->tidinvalid) {
2186 u64 chippa = pa >> IBA7220_TID_PA_SHIFT;
2187
2188
2189 if (pa != (chippa << IBA7220_TID_PA_SHIFT)) {
2190 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
2191 pa);
2192 return;
2193 }
2194 if (chippa >= (1UL << IBA7220_TID_SZ_SHIFT)) {
2195 qib_dev_err(dd,
2196 "Physical page address 0x%lx larger than supported\n",
2197 pa);
2198 return;
2199 }
2200
2201 if (type == RCVHQ_RCV_TYPE_EAGER)
2202 chippa |= dd->tidtemplate;
2203 else
2204 chippa |= IBA7220_TID_SZ_4K;
2205 pa = chippa;
2206 }
2207 writeq(pa, tidptr);
2208 mmiowb();
2209}
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221static void qib_7220_clear_tids(struct qib_devdata *dd,
2222 struct qib_ctxtdata *rcd)
2223{
2224 u64 __iomem *tidbase;
2225 unsigned long tidinv;
2226 u32 ctxt;
2227 int i;
2228
2229 if (!dd->kregbase || !rcd)
2230 return;
2231
2232 ctxt = rcd->ctxt;
2233
2234 tidinv = dd->tidinvalid;
2235 tidbase = (u64 __iomem *)
2236 ((char __iomem *)(dd->kregbase) +
2237 dd->rcvtidbase +
2238 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
2239
2240 for (i = 0; i < dd->rcvtidcnt; i++)
2241 qib_7220_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
2242 tidinv);
2243
2244 tidbase = (u64 __iomem *)
2245 ((char __iomem *)(dd->kregbase) +
2246 dd->rcvegrbase +
2247 rcd->rcvegr_tid_base * sizeof(*tidbase));
2248
2249 for (i = 0; i < rcd->rcvegrcnt; i++)
2250 qib_7220_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
2251 tidinv);
2252}
2253
2254
2255
2256
2257
2258
2259
2260static void qib_7220_tidtemplate(struct qib_devdata *dd)
2261{
2262 if (dd->rcvegrbufsize == 2048)
2263 dd->tidtemplate = IBA7220_TID_SZ_2K;
2264 else if (dd->rcvegrbufsize == 4096)
2265 dd->tidtemplate = IBA7220_TID_SZ_4K;
2266 dd->tidinvalid = 0;
2267}
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277static int qib_7220_get_base_info(struct qib_ctxtdata *rcd,
2278 struct qib_base_info *kinfo)
2279{
2280 kinfo->spi_runtime_flags |= QIB_RUNTIME_PCIE |
2281 QIB_RUNTIME_NODMA_RTAIL | QIB_RUNTIME_SDMA;
2282
2283 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
2284 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
2285
2286 return 0;
2287}
2288
2289static struct qib_message_header *
2290qib_7220_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
2291{
2292 u32 offset = qib_hdrget_offset(rhf_addr);
2293
2294 return (struct qib_message_header *)
2295 (rhf_addr - dd->rhf_offset + offset);
2296}
2297
2298static void qib_7220_config_ctxts(struct qib_devdata *dd)
2299{
2300 unsigned long flags;
2301 u32 nchipctxts;
2302
2303 nchipctxts = qib_read_kreg32(dd, kr_portcnt);
2304 dd->cspec->numctxts = nchipctxts;
2305 if (qib_n_krcv_queues > 1) {
2306 dd->qpn_mask = 0x3e;
2307 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports;
2308 if (dd->first_user_ctxt > nchipctxts)
2309 dd->first_user_ctxt = nchipctxts;
2310 } else
2311 dd->first_user_ctxt = dd->num_pports;
2312 dd->n_krcv_queues = dd->first_user_ctxt;
2313
2314 if (!qib_cfgctxts) {
2315 int nctxts = dd->first_user_ctxt + num_online_cpus();
2316
2317 if (nctxts <= 5)
2318 dd->ctxtcnt = 5;
2319 else if (nctxts <= 9)
2320 dd->ctxtcnt = 9;
2321 else if (nctxts <= nchipctxts)
2322 dd->ctxtcnt = nchipctxts;
2323 } else if (qib_cfgctxts <= nchipctxts)
2324 dd->ctxtcnt = qib_cfgctxts;
2325 if (!dd->ctxtcnt)
2326 dd->ctxtcnt = nchipctxts;
2327
2328
2329
2330
2331
2332
2333 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2334 if (dd->ctxtcnt > 9)
2335 dd->rcvctrl |= 2ULL << IBA7220_R_CTXTCFG_SHIFT;
2336 else if (dd->ctxtcnt > 5)
2337 dd->rcvctrl |= 1ULL << IBA7220_R_CTXTCFG_SHIFT;
2338
2339 if (dd->qpn_mask)
2340 dd->rcvctrl |= 1ULL << QIB_7220_RcvCtrl_RcvQPMapEnable_LSB;
2341 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2342 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2343
2344
2345 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
2346 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, IBA7220_KRCVEGRCNT);
2347}
2348
2349static int qib_7220_get_ib_cfg(struct qib_pportdata *ppd, int which)
2350{
2351 int lsb, ret = 0;
2352 u64 maskr;
2353
2354 switch (which) {
2355 case QIB_IB_CFG_LWID_ENB:
2356 ret = ppd->link_width_enabled;
2357 goto done;
2358
2359 case QIB_IB_CFG_LWID:
2360 ret = ppd->link_width_active;
2361 goto done;
2362
2363 case QIB_IB_CFG_SPD_ENB:
2364 ret = ppd->link_speed_enabled;
2365 goto done;
2366
2367 case QIB_IB_CFG_SPD:
2368 ret = ppd->link_speed_active;
2369 goto done;
2370
2371 case QIB_IB_CFG_RXPOL_ENB:
2372 lsb = IBA7220_IBC_RXPOL_SHIFT;
2373 maskr = IBA7220_IBC_RXPOL_MASK;
2374 break;
2375
2376 case QIB_IB_CFG_LREV_ENB:
2377 lsb = IBA7220_IBC_LREV_SHIFT;
2378 maskr = IBA7220_IBC_LREV_MASK;
2379 break;
2380
2381 case QIB_IB_CFG_LINKLATENCY:
2382 ret = qib_read_kreg64(ppd->dd, kr_ibcddrstatus)
2383 & IBA7220_DDRSTAT_LINKLAT_MASK;
2384 goto done;
2385
2386 case QIB_IB_CFG_OP_VLS:
2387 ret = ppd->vls_operational;
2388 goto done;
2389
2390 case QIB_IB_CFG_VL_HIGH_CAP:
2391 ret = 0;
2392 goto done;
2393
2394 case QIB_IB_CFG_VL_LOW_CAP:
2395 ret = 0;
2396 goto done;
2397
2398 case QIB_IB_CFG_OVERRUN_THRESH:
2399 ret = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2400 OverrunThreshold);
2401 goto done;
2402
2403 case QIB_IB_CFG_PHYERR_THRESH:
2404 ret = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2405 PhyerrThreshold);
2406 goto done;
2407
2408 case QIB_IB_CFG_LINKDEFAULT:
2409
2410 ret = (ppd->cpspec->ibcctrl &
2411 SYM_MASK(IBCCtrl, LinkDownDefaultState)) ?
2412 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
2413 goto done;
2414
2415 case QIB_IB_CFG_HRTBT:
2416 lsb = IBA7220_IBC_HRTBT_SHIFT;
2417 maskr = IBA7220_IBC_HRTBT_MASK;
2418 break;
2419
2420 case QIB_IB_CFG_PMA_TICKS:
2421
2422
2423
2424
2425 ret = (ppd->link_speed_active == QIB_IB_DDR);
2426 goto done;
2427
2428 default:
2429 ret = -EINVAL;
2430 goto done;
2431 }
2432 ret = (int)((ppd->cpspec->ibcddrctrl >> lsb) & maskr);
2433done:
2434 return ret;
2435}
2436
2437static int qib_7220_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
2438{
2439 struct qib_devdata *dd = ppd->dd;
2440 u64 maskr;
2441 int lsb, ret = 0, setforce = 0;
2442 u16 lcmd, licmd;
2443 unsigned long flags;
2444 u32 tmp = 0;
2445
2446 switch (which) {
2447 case QIB_IB_CFG_LIDLMC:
2448
2449
2450
2451
2452 lsb = IBA7220_IBC_DLIDLMC_SHIFT;
2453 maskr = IBA7220_IBC_DLIDLMC_MASK;
2454 break;
2455
2456 case QIB_IB_CFG_LWID_ENB:
2457
2458
2459
2460
2461
2462 ppd->link_width_enabled = val;
2463 if (!(ppd->lflags & QIBL_LINKDOWN))
2464 goto bail;
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474 val--;
2475 maskr = IBA7220_IBC_WIDTH_MASK;
2476 lsb = IBA7220_IBC_WIDTH_SHIFT;
2477 setforce = 1;
2478 break;
2479
2480 case QIB_IB_CFG_SPD_ENB:
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490 ppd->link_speed_enabled = val;
2491 if ((ppd->cpspec->ibcddrctrl & IBA7220_IBC_IBTA_1_2_MASK) &&
2492 !(val & (val - 1)))
2493 dd->cspec->presets_needed = 1;
2494 if (!(ppd->lflags & QIBL_LINKDOWN))
2495 goto bail;
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505 if (val == (QIB_IB_SDR | QIB_IB_DDR)) {
2506 val = IBA7220_IBC_SPEED_AUTONEG_MASK |
2507 IBA7220_IBC_IBTA_1_2_MASK;
2508 spin_lock_irqsave(&ppd->lflags_lock, flags);
2509 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
2510 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2511 } else
2512 val = val == QIB_IB_DDR ?
2513 IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
2514 maskr = IBA7220_IBC_SPEED_AUTONEG_MASK |
2515 IBA7220_IBC_IBTA_1_2_MASK;
2516
2517 lsb = SYM_LSB(IBCDDRCtrl, IB_ENHANCED_MODE);
2518 setforce = 1;
2519 break;
2520
2521 case QIB_IB_CFG_RXPOL_ENB:
2522 lsb = IBA7220_IBC_RXPOL_SHIFT;
2523 maskr = IBA7220_IBC_RXPOL_MASK;
2524 break;
2525
2526 case QIB_IB_CFG_LREV_ENB:
2527 lsb = IBA7220_IBC_LREV_SHIFT;
2528 maskr = IBA7220_IBC_LREV_MASK;
2529 break;
2530
2531 case QIB_IB_CFG_OVERRUN_THRESH:
2532 maskr = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2533 OverrunThreshold);
2534 if (maskr != val) {
2535 ppd->cpspec->ibcctrl &=
2536 ~SYM_MASK(IBCCtrl, OverrunThreshold);
2537 ppd->cpspec->ibcctrl |= (u64) val <<
2538 SYM_LSB(IBCCtrl, OverrunThreshold);
2539 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2540 qib_write_kreg(dd, kr_scratch, 0);
2541 }
2542 goto bail;
2543
2544 case QIB_IB_CFG_PHYERR_THRESH:
2545 maskr = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2546 PhyerrThreshold);
2547 if (maskr != val) {
2548 ppd->cpspec->ibcctrl &=
2549 ~SYM_MASK(IBCCtrl, PhyerrThreshold);
2550 ppd->cpspec->ibcctrl |= (u64) val <<
2551 SYM_LSB(IBCCtrl, PhyerrThreshold);
2552 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2553 qib_write_kreg(dd, kr_scratch, 0);
2554 }
2555 goto bail;
2556
2557 case QIB_IB_CFG_PKEYS:
2558 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
2559 ((u64) ppd->pkeys[2] << 32) |
2560 ((u64) ppd->pkeys[3] << 48);
2561 qib_write_kreg(dd, kr_partitionkey, maskr);
2562 goto bail;
2563
2564 case QIB_IB_CFG_LINKDEFAULT:
2565
2566 if (val == IB_LINKINITCMD_POLL)
2567 ppd->cpspec->ibcctrl &=
2568 ~SYM_MASK(IBCCtrl, LinkDownDefaultState);
2569 else
2570 ppd->cpspec->ibcctrl |=
2571 SYM_MASK(IBCCtrl, LinkDownDefaultState);
2572 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2573 qib_write_kreg(dd, kr_scratch, 0);
2574 goto bail;
2575
2576 case QIB_IB_CFG_MTU:
2577
2578
2579
2580
2581
2582
2583
2584 val = (ppd->ibmaxlen >> 2) + 1;
2585 ppd->cpspec->ibcctrl &= ~SYM_MASK(IBCCtrl, MaxPktLen);
2586 ppd->cpspec->ibcctrl |= (u64)val << SYM_LSB(IBCCtrl, MaxPktLen);
2587 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2588 qib_write_kreg(dd, kr_scratch, 0);
2589 goto bail;
2590
2591 case QIB_IB_CFG_LSTATE:
2592 switch (val & 0xffff0000) {
2593 case IB_LINKCMD_DOWN:
2594 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
2595 if (!ppd->cpspec->ibdeltainprog &&
2596 qib_compat_ddr_negotiate) {
2597 ppd->cpspec->ibdeltainprog = 1;
2598 ppd->cpspec->ibsymsnap =
2599 read_7220_creg32(dd, cr_ibsymbolerr);
2600 ppd->cpspec->iblnkerrsnap =
2601 read_7220_creg32(dd, cr_iblinkerrrecov);
2602 }
2603 break;
2604
2605 case IB_LINKCMD_ARMED:
2606 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
2607 break;
2608
2609 case IB_LINKCMD_ACTIVE:
2610 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
2611 break;
2612
2613 default:
2614 ret = -EINVAL;
2615 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
2616 goto bail;
2617 }
2618 switch (val & 0xffff) {
2619 case IB_LINKINITCMD_NOP:
2620 licmd = 0;
2621 break;
2622
2623 case IB_LINKINITCMD_POLL:
2624 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
2625 break;
2626
2627 case IB_LINKINITCMD_SLEEP:
2628 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
2629 break;
2630
2631 case IB_LINKINITCMD_DISABLE:
2632 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
2633 ppd->cpspec->chase_end = 0;
2634
2635
2636
2637
2638 if (ppd->cpspec->chase_timer.expires) {
2639 del_timer_sync(&ppd->cpspec->chase_timer);
2640 ppd->cpspec->chase_timer.expires = 0;
2641 }
2642 break;
2643
2644 default:
2645 ret = -EINVAL;
2646 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
2647 val & 0xffff);
2648 goto bail;
2649 }
2650 qib_set_ib_7220_lstate(ppd, lcmd, licmd);
2651
2652 maskr = IBA7220_IBC_WIDTH_MASK;
2653 lsb = IBA7220_IBC_WIDTH_SHIFT;
2654 tmp = (ppd->cpspec->ibcddrctrl >> lsb) & maskr;
2655
2656
2657
2658
2659
2660
2661 if (ppd->link_width_enabled-1 != tmp) {
2662 ppd->cpspec->ibcddrctrl &= ~(maskr << lsb);
2663 ppd->cpspec->ibcddrctrl |=
2664 (((u64)(ppd->link_width_enabled-1) & maskr) <<
2665 lsb);
2666 qib_write_kreg(dd, kr_ibcddrctrl,
2667 ppd->cpspec->ibcddrctrl);
2668 qib_write_kreg(dd, kr_scratch, 0);
2669 spin_lock_irqsave(&ppd->lflags_lock, flags);
2670 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
2671 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2672 }
2673 goto bail;
2674
2675 case QIB_IB_CFG_HRTBT:
2676 if (val > IBA7220_IBC_HRTBT_MASK) {
2677 ret = -EINVAL;
2678 goto bail;
2679 }
2680 lsb = IBA7220_IBC_HRTBT_SHIFT;
2681 maskr = IBA7220_IBC_HRTBT_MASK;
2682 break;
2683
2684 default:
2685 ret = -EINVAL;
2686 goto bail;
2687 }
2688 ppd->cpspec->ibcddrctrl &= ~(maskr << lsb);
2689 ppd->cpspec->ibcddrctrl |= (((u64) val & maskr) << lsb);
2690 qib_write_kreg(dd, kr_ibcddrctrl, ppd->cpspec->ibcddrctrl);
2691 qib_write_kreg(dd, kr_scratch, 0);
2692 if (setforce) {
2693 spin_lock_irqsave(&ppd->lflags_lock, flags);
2694 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
2695 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2696 }
2697bail:
2698 return ret;
2699}
2700
2701static int qib_7220_set_loopback(struct qib_pportdata *ppd, const char *what)
2702{
2703 int ret = 0;
2704 u64 val, ddr;
2705
2706 if (!strncmp(what, "ibc", 3)) {
2707 ppd->cpspec->ibcctrl |= SYM_MASK(IBCCtrl, Loopback);
2708 val = 0;
2709 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
2710 ppd->dd->unit, ppd->port);
2711 } else if (!strncmp(what, "off", 3)) {
2712 ppd->cpspec->ibcctrl &= ~SYM_MASK(IBCCtrl, Loopback);
2713
2714 val = IBA7220_IBC_HRTBT_MASK << IBA7220_IBC_HRTBT_SHIFT;
2715 qib_devinfo(ppd->dd->pcidev,
2716 "Disabling IB%u:%u IBC loopback (normal)\n",
2717 ppd->dd->unit, ppd->port);
2718 } else
2719 ret = -EINVAL;
2720 if (!ret) {
2721 qib_write_kreg(ppd->dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2722 ddr = ppd->cpspec->ibcddrctrl & ~(IBA7220_IBC_HRTBT_MASK
2723 << IBA7220_IBC_HRTBT_SHIFT);
2724 ppd->cpspec->ibcddrctrl = ddr | val;
2725 qib_write_kreg(ppd->dd, kr_ibcddrctrl,
2726 ppd->cpspec->ibcddrctrl);
2727 qib_write_kreg(ppd->dd, kr_scratch, 0);
2728 }
2729 return ret;
2730}
2731
2732static void qib_update_7220_usrhead(struct qib_ctxtdata *rcd, u64 hd,
2733 u32 updegr, u32 egrhd, u32 npkts)
2734{
2735 if (updegr)
2736 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
2737 mmiowb();
2738 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
2739 mmiowb();
2740}
2741
2742static u32 qib_7220_hdrqempty(struct qib_ctxtdata *rcd)
2743{
2744 u32 head, tail;
2745
2746 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
2747 if (rcd->rcvhdrtail_kvaddr)
2748 tail = qib_get_rcvhdrtail(rcd);
2749 else
2750 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
2751 return head == tail;
2752}
2753
2754
2755
2756
2757
2758
2759
2760
2761static void rcvctrl_7220_mod(struct qib_pportdata *ppd, unsigned int op,
2762 int ctxt)
2763{
2764 struct qib_devdata *dd = ppd->dd;
2765 u64 mask, val;
2766 unsigned long flags;
2767
2768 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2769 if (op & QIB_RCVCTRL_TAILUPD_ENB)
2770 dd->rcvctrl |= (1ULL << IBA7220_R_TAILUPD_SHIFT);
2771 if (op & QIB_RCVCTRL_TAILUPD_DIS)
2772 dd->rcvctrl &= ~(1ULL << IBA7220_R_TAILUPD_SHIFT);
2773 if (op & QIB_RCVCTRL_PKEY_ENB)
2774 dd->rcvctrl &= ~(1ULL << IBA7220_R_PKEY_DIS_SHIFT);
2775 if (op & QIB_RCVCTRL_PKEY_DIS)
2776 dd->rcvctrl |= (1ULL << IBA7220_R_PKEY_DIS_SHIFT);
2777 if (ctxt < 0)
2778 mask = (1ULL << dd->ctxtcnt) - 1;
2779 else
2780 mask = (1ULL << ctxt);
2781 if (op & QIB_RCVCTRL_CTXT_ENB) {
2782
2783 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable));
2784 if (!(dd->flags & QIB_NODMA_RTAIL))
2785 dd->rcvctrl |= 1ULL << IBA7220_R_TAILUPD_SHIFT;
2786
2787 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2788 dd->rcd[ctxt]->rcvhdrqtailaddr_phys);
2789 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2790 dd->rcd[ctxt]->rcvhdrq_phys);
2791 dd->rcd[ctxt]->seq_cnt = 1;
2792 }
2793 if (op & QIB_RCVCTRL_CTXT_DIS)
2794 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable));
2795 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
2796 dd->rcvctrl |= (mask << IBA7220_R_INTRAVAIL_SHIFT);
2797 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
2798 dd->rcvctrl &= ~(mask << IBA7220_R_INTRAVAIL_SHIFT);
2799 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2800 if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && dd->rhdrhead_intr_off) {
2801
2802 val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) |
2803 dd->rhdrhead_intr_off;
2804 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2805 }
2806 if (op & QIB_RCVCTRL_CTXT_ENB) {
2807
2808
2809
2810
2811
2812
2813 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
2814 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
2815
2816 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
2817 dd->rcd[ctxt]->head = val;
2818
2819 if (ctxt < dd->first_user_ctxt)
2820 val |= dd->rhdrhead_intr_off;
2821 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2822 }
2823 if (op & QIB_RCVCTRL_CTXT_DIS) {
2824 if (ctxt >= 0) {
2825 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt, 0);
2826 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt, 0);
2827 } else {
2828 unsigned i;
2829
2830 for (i = 0; i < dd->cfgctxts; i++) {
2831 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr,
2832 i, 0);
2833 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, i, 0);
2834 }
2835 }
2836 }
2837 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2838}
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848static void sendctrl_7220_mod(struct qib_pportdata *ppd, u32 op)
2849{
2850 struct qib_devdata *dd = ppd->dd;
2851 u64 tmp_dd_sendctrl;
2852 unsigned long flags;
2853
2854 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2855
2856
2857 if (op & QIB_SENDCTRL_CLEAR)
2858 dd->sendctrl = 0;
2859 if (op & QIB_SENDCTRL_SEND_DIS)
2860 dd->sendctrl &= ~SYM_MASK(SendCtrl, SPioEnable);
2861 else if (op & QIB_SENDCTRL_SEND_ENB) {
2862 dd->sendctrl |= SYM_MASK(SendCtrl, SPioEnable);
2863 if (dd->flags & QIB_USE_SPCL_TRIG)
2864 dd->sendctrl |= SYM_MASK(SendCtrl,
2865 SSpecialTriggerEn);
2866 }
2867 if (op & QIB_SENDCTRL_AVAIL_DIS)
2868 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
2869 else if (op & QIB_SENDCTRL_AVAIL_ENB)
2870 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
2871
2872 if (op & QIB_SENDCTRL_DISARM_ALL) {
2873 u32 i, last;
2874
2875 tmp_dd_sendctrl = dd->sendctrl;
2876
2877
2878
2879
2880 last = dd->piobcnt2k + dd->piobcnt4k;
2881 tmp_dd_sendctrl &=
2882 ~(SYM_MASK(SendCtrl, SPioEnable) |
2883 SYM_MASK(SendCtrl, SendBufAvailUpd));
2884 for (i = 0; i < last; i++) {
2885 qib_write_kreg(dd, kr_sendctrl,
2886 tmp_dd_sendctrl |
2887 SYM_MASK(SendCtrl, Disarm) | i);
2888 qib_write_kreg(dd, kr_scratch, 0);
2889 }
2890 }
2891
2892 tmp_dd_sendctrl = dd->sendctrl;
2893
2894 if (op & QIB_SENDCTRL_FLUSH)
2895 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Abort);
2896 if (op & QIB_SENDCTRL_DISARM)
2897 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
2898 ((op & QIB_7220_SendCtrl_DisarmPIOBuf_RMASK) <<
2899 SYM_LSB(SendCtrl, DisarmPIOBuf));
2900 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
2901 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
2902 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
2903
2904 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
2905 qib_write_kreg(dd, kr_scratch, 0);
2906
2907 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
2908 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2909 qib_write_kreg(dd, kr_scratch, 0);
2910 }
2911
2912 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2913
2914 if (op & QIB_SENDCTRL_FLUSH) {
2915 u32 v;
2916
2917
2918
2919
2920
2921
2922 v = qib_read_kreg32(dd, kr_scratch);
2923 qib_write_kreg(dd, kr_scratch, v);
2924 v = qib_read_kreg32(dd, kr_scratch);
2925 qib_write_kreg(dd, kr_scratch, v);
2926 qib_read_kreg32(dd, kr_scratch);
2927 }
2928}
2929
2930
2931
2932
2933
2934
2935static u64 qib_portcntr_7220(struct qib_pportdata *ppd, u32 reg)
2936{
2937 u64 ret = 0ULL;
2938 struct qib_devdata *dd = ppd->dd;
2939 u16 creg;
2940
2941 static const u16 xlator[] = {
2942 [QIBPORTCNTR_PKTSEND] = cr_pktsend,
2943 [QIBPORTCNTR_WORDSEND] = cr_wordsend,
2944 [QIBPORTCNTR_PSXMITDATA] = cr_psxmitdatacount,
2945 [QIBPORTCNTR_PSXMITPKTS] = cr_psxmitpktscount,
2946 [QIBPORTCNTR_PSXMITWAIT] = cr_psxmitwaitcount,
2947 [QIBPORTCNTR_SENDSTALL] = cr_sendstall,
2948 [QIBPORTCNTR_PKTRCV] = cr_pktrcv,
2949 [QIBPORTCNTR_PSRCVDATA] = cr_psrcvdatacount,
2950 [QIBPORTCNTR_PSRCVPKTS] = cr_psrcvpktscount,
2951 [QIBPORTCNTR_RCVEBP] = cr_rcvebp,
2952 [QIBPORTCNTR_RCVOVFL] = cr_rcvovfl,
2953 [QIBPORTCNTR_WORDRCV] = cr_wordrcv,
2954 [QIBPORTCNTR_RXDROPPKT] = cr_rxdroppkt,
2955 [QIBPORTCNTR_RXLOCALPHYERR] = cr_rxotherlocalphyerr,
2956 [QIBPORTCNTR_RXVLERR] = cr_rxvlerr,
2957 [QIBPORTCNTR_ERRICRC] = cr_erricrc,
2958 [QIBPORTCNTR_ERRVCRC] = cr_errvcrc,
2959 [QIBPORTCNTR_ERRLPCRC] = cr_errlpcrc,
2960 [QIBPORTCNTR_BADFORMAT] = cr_badformat,
2961 [QIBPORTCNTR_ERR_RLEN] = cr_err_rlen,
2962 [QIBPORTCNTR_IBSYMBOLERR] = cr_ibsymbolerr,
2963 [QIBPORTCNTR_INVALIDRLEN] = cr_invalidrlen,
2964 [QIBPORTCNTR_UNSUPVL] = cr_txunsupvl,
2965 [QIBPORTCNTR_EXCESSBUFOVFL] = cr_excessbufferovfl,
2966 [QIBPORTCNTR_ERRLINK] = cr_errlink,
2967 [QIBPORTCNTR_IBLINKDOWN] = cr_iblinkdown,
2968 [QIBPORTCNTR_IBLINKERRRECOV] = cr_iblinkerrrecov,
2969 [QIBPORTCNTR_LLI] = cr_locallinkintegrityerr,
2970 [QIBPORTCNTR_PSINTERVAL] = cr_psinterval,
2971 [QIBPORTCNTR_PSSTART] = cr_psstart,
2972 [QIBPORTCNTR_PSSTAT] = cr_psstat,
2973 [QIBPORTCNTR_VL15PKTDROP] = cr_vl15droppedpkt,
2974 [QIBPORTCNTR_ERRPKEY] = cr_errpkey,
2975 [QIBPORTCNTR_KHDROVFL] = 0xffff,
2976 };
2977
2978 if (reg >= ARRAY_SIZE(xlator)) {
2979 qib_devinfo(ppd->dd->pcidev,
2980 "Unimplemented portcounter %u\n", reg);
2981 goto done;
2982 }
2983 creg = xlator[reg];
2984
2985 if (reg == QIBPORTCNTR_KHDROVFL) {
2986 int i;
2987
2988
2989 for (i = 0; i < dd->first_user_ctxt; i++)
2990 ret += read_7220_creg32(dd, cr_portovfl + i);
2991 }
2992 if (creg == 0xffff)
2993 goto done;
2994
2995
2996
2997
2998
2999 if ((creg == cr_wordsend || creg == cr_wordrcv ||
3000 creg == cr_pktsend || creg == cr_pktrcv))
3001 ret = read_7220_creg(dd, creg);
3002 else
3003 ret = read_7220_creg32(dd, creg);
3004 if (creg == cr_ibsymbolerr) {
3005 if (dd->pport->cpspec->ibdeltainprog)
3006 ret -= ret - ppd->cpspec->ibsymsnap;
3007 ret -= dd->pport->cpspec->ibsymdelta;
3008 } else if (creg == cr_iblinkerrrecov) {
3009 if (dd->pport->cpspec->ibdeltainprog)
3010 ret -= ret - ppd->cpspec->iblnkerrsnap;
3011 ret -= dd->pport->cpspec->iblnkerrdelta;
3012 }
3013done:
3014 return ret;
3015}
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030static const char cntr7220names[] =
3031 "Interrupts\n"
3032 "HostBusStall\n"
3033 "E RxTIDFull\n"
3034 "RxTIDInvalid\n"
3035 "Ctxt0EgrOvfl\n"
3036 "Ctxt1EgrOvfl\n"
3037 "Ctxt2EgrOvfl\n"
3038 "Ctxt3EgrOvfl\n"
3039 "Ctxt4EgrOvfl\n"
3040 "Ctxt5EgrOvfl\n"
3041 "Ctxt6EgrOvfl\n"
3042 "Ctxt7EgrOvfl\n"
3043 "Ctxt8EgrOvfl\n"
3044 "Ctxt9EgrOvfl\n"
3045 "Ctx10EgrOvfl\n"
3046 "Ctx11EgrOvfl\n"
3047 "Ctx12EgrOvfl\n"
3048 "Ctx13EgrOvfl\n"
3049 "Ctx14EgrOvfl\n"
3050 "Ctx15EgrOvfl\n"
3051 "Ctx16EgrOvfl\n";
3052
3053static const size_t cntr7220indices[] = {
3054 cr_lbint,
3055 cr_lbflowstall,
3056 cr_errtidfull,
3057 cr_errtidvalid,
3058 cr_portovfl + 0,
3059 cr_portovfl + 1,
3060 cr_portovfl + 2,
3061 cr_portovfl + 3,
3062 cr_portovfl + 4,
3063 cr_portovfl + 5,
3064 cr_portovfl + 6,
3065 cr_portovfl + 7,
3066 cr_portovfl + 8,
3067 cr_portovfl + 9,
3068 cr_portovfl + 10,
3069 cr_portovfl + 11,
3070 cr_portovfl + 12,
3071 cr_portovfl + 13,
3072 cr_portovfl + 14,
3073 cr_portovfl + 15,
3074 cr_portovfl + 16,
3075};
3076
3077
3078
3079
3080
3081
3082static const char portcntr7220names[] =
3083 "TxPkt\n"
3084 "TxFlowPkt\n"
3085 "TxWords\n"
3086 "RxPkt\n"
3087 "RxFlowPkt\n"
3088 "RxWords\n"
3089 "TxFlowStall\n"
3090 "TxDmaDesc\n"
3091 "E RxDlidFltr\n"
3092 "IBStatusChng\n"
3093 "IBLinkDown\n"
3094 "IBLnkRecov\n"
3095 "IBRxLinkErr\n"
3096 "IBSymbolErr\n"
3097 "RxLLIErr\n"
3098 "RxBadFormat\n"
3099 "RxBadLen\n"
3100 "RxBufOvrfl\n"
3101 "RxEBP\n"
3102 "RxFlowCtlErr\n"
3103 "RxICRCerr\n"
3104 "RxLPCRCerr\n"
3105 "RxVCRCerr\n"
3106 "RxInvalLen\n"
3107 "RxInvalPKey\n"
3108 "RxPktDropped\n"
3109 "TxBadLength\n"
3110 "TxDropped\n"
3111 "TxInvalLen\n"
3112 "TxUnderrun\n"
3113 "TxUnsupVL\n"
3114 "RxLclPhyErr\n"
3115 "RxVL15Drop\n"
3116 "RxVlErr\n"
3117 "XcessBufOvfl\n"
3118 ;
3119
3120#define _PORT_VIRT_FLAG 0x8000
3121static const size_t portcntr7220indices[] = {
3122 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
3123 cr_pktsendflow,
3124 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
3125 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
3126 cr_pktrcvflowctrl,
3127 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
3128 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
3129 cr_txsdmadesc,
3130 cr_rxdlidfltr,
3131 cr_ibstatuschange,
3132 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
3133 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
3134 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
3135 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
3136 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
3137 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
3138 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
3139 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
3140 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
3141 cr_rcvflowctrl_err,
3142 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
3143 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
3144 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
3145 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
3146 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
3147 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
3148 cr_invalidslen,
3149 cr_senddropped,
3150 cr_errslen,
3151 cr_sendunderrun,
3152 cr_txunsupvl,
3153 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
3154 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
3155 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
3156 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
3157};
3158
3159
3160static void init_7220_cntrnames(struct qib_devdata *dd)
3161{
3162 int i, j = 0;
3163 char *s;
3164
3165 for (i = 0, s = (char *)cntr7220names; s && j <= dd->cfgctxts;
3166 i++) {
3167
3168 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
3169 j = 1;
3170 s = strchr(s + 1, '\n');
3171 if (s && j)
3172 j++;
3173 }
3174 dd->cspec->ncntrs = i;
3175 if (!s)
3176
3177 dd->cspec->cntrnamelen = sizeof(cntr7220names) - 1;
3178 else
3179 dd->cspec->cntrnamelen = 1 + s - cntr7220names;
3180 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
3181 * sizeof(u64), GFP_KERNEL);
3182 if (!dd->cspec->cntrs)
3183 qib_dev_err(dd, "Failed allocation for counters\n");
3184
3185 for (i = 0, s = (char *)portcntr7220names; s; i++)
3186 s = strchr(s + 1, '\n');
3187 dd->cspec->nportcntrs = i - 1;
3188 dd->cspec->portcntrnamelen = sizeof(portcntr7220names) - 1;
3189 dd->cspec->portcntrs = kmalloc(dd->cspec->nportcntrs
3190 * sizeof(u64), GFP_KERNEL);
3191 if (!dd->cspec->portcntrs)
3192 qib_dev_err(dd, "Failed allocation for portcounters\n");
3193}
3194
3195static u32 qib_read_7220cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
3196 u64 **cntrp)
3197{
3198 u32 ret;
3199
3200 if (!dd->cspec->cntrs) {
3201 ret = 0;
3202 goto done;
3203 }
3204
3205 if (namep) {
3206 *namep = (char *)cntr7220names;
3207 ret = dd->cspec->cntrnamelen;
3208 if (pos >= ret)
3209 ret = 0;
3210 } else {
3211 u64 *cntr = dd->cspec->cntrs;
3212 int i;
3213
3214 ret = dd->cspec->ncntrs * sizeof(u64);
3215 if (!cntr || pos >= ret) {
3216
3217 ret = 0;
3218 goto done;
3219 }
3220
3221 *cntrp = cntr;
3222 for (i = 0; i < dd->cspec->ncntrs; i++)
3223 *cntr++ = read_7220_creg32(dd, cntr7220indices[i]);
3224 }
3225done:
3226 return ret;
3227}
3228
3229static u32 qib_read_7220portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
3230 char **namep, u64 **cntrp)
3231{
3232 u32 ret;
3233
3234 if (!dd->cspec->portcntrs) {
3235 ret = 0;
3236 goto done;
3237 }
3238 if (namep) {
3239 *namep = (char *)portcntr7220names;
3240 ret = dd->cspec->portcntrnamelen;
3241 if (pos >= ret)
3242 ret = 0;
3243 } else {
3244 u64 *cntr = dd->cspec->portcntrs;
3245 struct qib_pportdata *ppd = &dd->pport[port];
3246 int i;
3247
3248 ret = dd->cspec->nportcntrs * sizeof(u64);
3249 if (!cntr || pos >= ret) {
3250
3251 ret = 0;
3252 goto done;
3253 }
3254 *cntrp = cntr;
3255 for (i = 0; i < dd->cspec->nportcntrs; i++) {
3256 if (portcntr7220indices[i] & _PORT_VIRT_FLAG)
3257 *cntr++ = qib_portcntr_7220(ppd,
3258 portcntr7220indices[i] &
3259 ~_PORT_VIRT_FLAG);
3260 else
3261 *cntr++ = read_7220_creg32(dd,
3262 portcntr7220indices[i]);
3263 }
3264 }
3265done:
3266 return ret;
3267}
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277static void qib_get_7220_faststats(unsigned long opaque)
3278{
3279 struct qib_devdata *dd = (struct qib_devdata *) opaque;
3280 struct qib_pportdata *ppd = dd->pport;
3281 unsigned long flags;
3282 u64 traffic_wds;
3283
3284
3285
3286
3287
3288 if (!(dd->flags & QIB_INITTED) || dd->diag_client)
3289
3290 goto done;
3291
3292
3293
3294
3295
3296
3297 traffic_wds = qib_portcntr_7220(ppd, cr_wordsend) +
3298 qib_portcntr_7220(ppd, cr_wordrcv);
3299 spin_lock_irqsave(&dd->eep_st_lock, flags);
3300 traffic_wds -= dd->traffic_wds;
3301 dd->traffic_wds += traffic_wds;
3302 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
3303 atomic_add(5, &dd->active_time);
3304 spin_unlock_irqrestore(&dd->eep_st_lock, flags);
3305done:
3306 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
3307}
3308
3309
3310
3311
3312static int qib_7220_intr_fallback(struct qib_devdata *dd)
3313{
3314 if (!dd->msi_lo)
3315 return 0;
3316
3317 qib_devinfo(dd->pcidev,
3318 "MSI interrupt not detected, trying INTx interrupts\n");
3319 qib_7220_free_irq(dd);
3320 qib_enable_intx(dd->pcidev);
3321
3322
3323
3324
3325
3326
3327 dd->cspec->irq = dd->pcidev->irq;
3328 qib_setup_7220_interrupt(dd);
3329 return 1;
3330}
3331
3332
3333
3334
3335
3336
3337
3338static void qib_7220_xgxs_reset(struct qib_pportdata *ppd)
3339{
3340 u64 val, prev_val;
3341 struct qib_devdata *dd = ppd->dd;
3342
3343 prev_val = qib_read_kreg64(dd, kr_xgxs_cfg);
3344 val = prev_val | QLOGIC_IB_XGXS_RESET;
3345 prev_val &= ~QLOGIC_IB_XGXS_RESET;
3346 qib_write_kreg(dd, kr_control,
3347 dd->control & ~QLOGIC_IB_C_LINKENABLE);
3348 qib_write_kreg(dd, kr_xgxs_cfg, val);
3349 qib_read_kreg32(dd, kr_scratch);
3350 qib_write_kreg(dd, kr_xgxs_cfg, prev_val);
3351 qib_write_kreg(dd, kr_control, dd->control);
3352}
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369static u32 __iomem *get_7220_link_buf(struct qib_pportdata *ppd, u32 *bnum)
3370{
3371 u32 __iomem *buf;
3372 u32 lbuf = ppd->dd->cspec->lastbuf_for_pio;
3373 int do_cleanup;
3374 unsigned long flags;
3375
3376
3377
3378
3379
3380 sendctrl_7220_mod(ppd->dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
3381 qib_read_kreg64(ppd->dd, kr_scratch);
3382 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3383 if (buf)
3384 goto done;
3385
3386 spin_lock_irqsave(&ppd->sdma_lock, flags);
3387 if (ppd->sdma_state.current_state == qib_sdma_state_s20_idle &&
3388 ppd->sdma_state.current_state != qib_sdma_state_s00_hw_down) {
3389 __qib_sdma_process_event(ppd, qib_sdma_event_e00_go_hw_down);
3390 do_cleanup = 0;
3391 } else {
3392 do_cleanup = 1;
3393 qib_7220_sdma_hw_clean_up(ppd);
3394 }
3395 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
3396
3397 if (do_cleanup) {
3398 qib_read_kreg64(ppd->dd, kr_scratch);
3399 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3400 }
3401done:
3402 return buf;
3403}
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413static void autoneg_7220_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
3414 u32 dcnt, u32 *data)
3415{
3416 int i;
3417 u64 pbc;
3418 u32 __iomem *piobuf;
3419 u32 pnum;
3420 struct qib_devdata *dd = ppd->dd;
3421
3422 i = 0;
3423 pbc = 7 + dcnt + 1;
3424 pbc |= PBC_7220_VL15_SEND;
3425 while (!(piobuf = get_7220_link_buf(ppd, &pnum))) {
3426 if (i++ > 5)
3427 return;
3428 udelay(2);
3429 }
3430 sendctrl_7220_mod(dd->pport, QIB_SENDCTRL_DISARM_BUF(pnum));
3431 writeq(pbc, piobuf);
3432 qib_flush_wc();
3433 qib_pio_copy(piobuf + 2, hdr, 7);
3434 qib_pio_copy(piobuf + 9, data, dcnt);
3435 if (dd->flags & QIB_USE_SPCL_TRIG) {
3436 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
3437
3438 qib_flush_wc();
3439 __raw_writel(0xaebecede, piobuf + spcl_off);
3440 }
3441 qib_flush_wc();
3442 qib_sendbuf_done(dd, pnum);
3443}
3444
3445
3446
3447
3448static void autoneg_7220_send(struct qib_pportdata *ppd, int which)
3449{
3450 struct qib_devdata *dd = ppd->dd;
3451 static u32 swapped;
3452 u32 dw, i, hcnt, dcnt, *data;
3453 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
3454 static u32 madpayload_start[0x40] = {
3455 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
3456 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
3457 0x1, 0x1388, 0x15e, 0x1,
3458 };
3459 static u32 madpayload_done[0x40] = {
3460 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
3461 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
3462 0x40000001, 0x1388, 0x15e,
3463 };
3464
3465 dcnt = ARRAY_SIZE(madpayload_start);
3466 hcnt = ARRAY_SIZE(hdr);
3467 if (!swapped) {
3468
3469 for (i = 0; i < hcnt; i++) {
3470 dw = (__force u32) cpu_to_be32(hdr[i]);
3471 hdr[i] = dw;
3472 }
3473 for (i = 0; i < dcnt; i++) {
3474 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
3475 madpayload_start[i] = dw;
3476 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
3477 madpayload_done[i] = dw;
3478 }
3479 swapped = 1;
3480 }
3481
3482 data = which ? madpayload_done : madpayload_start;
3483
3484 autoneg_7220_sendpkt(ppd, hdr, dcnt, data);
3485 qib_read_kreg64(dd, kr_scratch);
3486 udelay(2);
3487 autoneg_7220_sendpkt(ppd, hdr, dcnt, data);
3488 qib_read_kreg64(dd, kr_scratch);
3489 udelay(2);
3490}
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506static void set_7220_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
3507{
3508 ppd->cpspec->ibcddrctrl &= ~(IBA7220_IBC_SPEED_AUTONEG_MASK |
3509 IBA7220_IBC_IBTA_1_2_MASK);
3510
3511 if (speed == (QIB_IB_SDR | QIB_IB_DDR))
3512 ppd->cpspec->ibcddrctrl |= IBA7220_IBC_SPEED_AUTONEG_MASK |
3513 IBA7220_IBC_IBTA_1_2_MASK;
3514 else
3515 ppd->cpspec->ibcddrctrl |= speed == QIB_IB_DDR ?
3516 IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
3517
3518 qib_write_kreg(ppd->dd, kr_ibcddrctrl, ppd->cpspec->ibcddrctrl);
3519 qib_write_kreg(ppd->dd, kr_scratch, 0);
3520}
3521
3522
3523
3524
3525
3526
3527
3528static void try_7220_autoneg(struct qib_pportdata *ppd)
3529{
3530 unsigned long flags;
3531
3532
3533
3534
3535
3536
3537 qib_write_kreg(ppd->dd, kr_ncmodectrl, 0x3b9dc07);
3538
3539 spin_lock_irqsave(&ppd->lflags_lock, flags);
3540 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
3541 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3542 autoneg_7220_send(ppd, 0);
3543 set_7220_ibspeed_fast(ppd, QIB_IB_DDR);
3544
3545 toggle_7220_rclkrls(ppd->dd);
3546
3547 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
3548 msecs_to_jiffies(2));
3549}
3550
3551
3552
3553
3554
3555static void autoneg_7220_work(struct work_struct *work)
3556{
3557 struct qib_pportdata *ppd;
3558 struct qib_devdata *dd;
3559 u64 startms;
3560 u32 i;
3561 unsigned long flags;
3562
3563 ppd = &container_of(work, struct qib_chippport_specific,
3564 autoneg_work.work)->pportdata;
3565 dd = ppd->dd;
3566
3567 startms = jiffies_to_msecs(jiffies);
3568
3569
3570
3571
3572
3573 for (i = 0; i < 25; i++) {
3574 if (SYM_FIELD(ppd->lastibcstat, IBCStatus, LinkTrainingState)
3575 == IB_7220_LT_STATE_POLLQUIET) {
3576 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
3577 break;
3578 }
3579 udelay(100);
3580 }
3581
3582 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
3583 goto done;
3584
3585
3586 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
3587 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
3588 msecs_to_jiffies(90)))
3589 goto done;
3590
3591 toggle_7220_rclkrls(dd);
3592
3593
3594 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
3595 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
3596 msecs_to_jiffies(1700)))
3597 goto done;
3598
3599 set_7220_ibspeed_fast(ppd, QIB_IB_SDR);
3600 toggle_7220_rclkrls(dd);
3601
3602
3603
3604
3605
3606 wait_event_timeout(ppd->cpspec->autoneg_wait,
3607 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
3608 msecs_to_jiffies(250));
3609done:
3610 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
3611 spin_lock_irqsave(&ppd->lflags_lock, flags);
3612 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
3613 if (dd->cspec->autoneg_tries == AUTONEG_TRIES) {
3614 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
3615 dd->cspec->autoneg_tries = 0;
3616 }
3617 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3618 set_7220_ibspeed_fast(ppd, ppd->link_speed_enabled);
3619 }
3620}
3621
3622static u32 qib_7220_iblink_state(u64 ibcs)
3623{
3624 u32 state = (u32)SYM_FIELD(ibcs, IBCStatus, LinkState);
3625
3626 switch (state) {
3627 case IB_7220_L_STATE_INIT:
3628 state = IB_PORT_INIT;
3629 break;
3630 case IB_7220_L_STATE_ARM:
3631 state = IB_PORT_ARMED;
3632 break;
3633 case IB_7220_L_STATE_ACTIVE:
3634
3635 case IB_7220_L_STATE_ACT_DEFER:
3636 state = IB_PORT_ACTIVE;
3637 break;
3638 default:
3639 case IB_7220_L_STATE_DOWN:
3640 state = IB_PORT_DOWN;
3641 break;
3642 }
3643 return state;
3644}
3645
3646
3647static u8 qib_7220_phys_portstate(u64 ibcs)
3648{
3649 u8 state = (u8)SYM_FIELD(ibcs, IBCStatus, LinkTrainingState);
3650 return qib_7220_physportstate[state];
3651}
3652
3653static int qib_7220_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
3654{
3655 int ret = 0, symadj = 0;
3656 struct qib_devdata *dd = ppd->dd;
3657 unsigned long flags;
3658
3659 spin_lock_irqsave(&ppd->lflags_lock, flags);
3660 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
3661 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3662
3663 if (!ibup) {
3664
3665
3666
3667
3668
3669 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
3670 QIBL_IB_AUTONEG_INPROG)))
3671 set_7220_ibspeed_fast(ppd, ppd->link_speed_enabled);
3672 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
3673 qib_sd7220_presets(dd);
3674 qib_cancel_sends(ppd);
3675 spin_lock_irqsave(&ppd->sdma_lock, flags);
3676 if (__qib_sdma_running(ppd))
3677 __qib_sdma_process_event(ppd,
3678 qib_sdma_event_e70_go_idle);
3679 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
3680 }
3681
3682 set_7220_relock_poll(dd, ibup);
3683 } else {
3684 if (qib_compat_ddr_negotiate &&
3685 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
3686 QIBL_IB_AUTONEG_INPROG)) &&
3687 ppd->link_speed_active == QIB_IB_SDR &&
3688 (ppd->link_speed_enabled & (QIB_IB_DDR | QIB_IB_SDR)) ==
3689 (QIB_IB_DDR | QIB_IB_SDR) &&
3690 dd->cspec->autoneg_tries < AUTONEG_TRIES) {
3691
3692 ++dd->cspec->autoneg_tries;
3693 if (!ppd->cpspec->ibdeltainprog) {
3694 ppd->cpspec->ibdeltainprog = 1;
3695 ppd->cpspec->ibsymsnap = read_7220_creg32(dd,
3696 cr_ibsymbolerr);
3697 ppd->cpspec->iblnkerrsnap = read_7220_creg32(dd,
3698 cr_iblinkerrrecov);
3699 }
3700 try_7220_autoneg(ppd);
3701 ret = 1;
3702 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
3703 ppd->link_speed_active == QIB_IB_SDR) {
3704 autoneg_7220_send(ppd, 1);
3705 set_7220_ibspeed_fast(ppd, QIB_IB_DDR);
3706 udelay(2);
3707 toggle_7220_rclkrls(dd);
3708 ret = 1;
3709 } else {
3710 if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
3711 (ppd->link_speed_active & QIB_IB_DDR)) {
3712 spin_lock_irqsave(&ppd->lflags_lock, flags);
3713 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
3714 QIBL_IB_AUTONEG_FAILED);
3715 spin_unlock_irqrestore(&ppd->lflags_lock,
3716 flags);
3717 dd->cspec->autoneg_tries = 0;
3718
3719 set_7220_ibspeed_fast(ppd,
3720 ppd->link_speed_enabled);
3721 wake_up(&ppd->cpspec->autoneg_wait);
3722 symadj = 1;
3723 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
3724
3725
3726
3727
3728
3729
3730 spin_lock_irqsave(&ppd->lflags_lock, flags);
3731 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3732 spin_unlock_irqrestore(&ppd->lflags_lock,
3733 flags);
3734 ppd->cpspec->ibcddrctrl |=
3735 IBA7220_IBC_IBTA_1_2_MASK;
3736 qib_write_kreg(dd, kr_ncmodectrl, 0);
3737 symadj = 1;
3738 }
3739 }
3740
3741 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
3742 symadj = 1;
3743
3744 if (!ret) {
3745 ppd->delay_mult = rate_to_delay
3746 [(ibcs >> IBA7220_LINKSPEED_SHIFT) & 1]
3747 [(ibcs >> IBA7220_LINKWIDTH_SHIFT) & 1];
3748
3749 set_7220_relock_poll(dd, ibup);
3750 spin_lock_irqsave(&ppd->sdma_lock, flags);
3751
3752
3753
3754
3755
3756 if (ppd->sdma_state.current_state !=
3757 qib_sdma_state_s20_idle)
3758 __qib_sdma_process_event(ppd,
3759 qib_sdma_event_e00_go_hw_down);
3760 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
3761 }
3762 }
3763
3764 if (symadj) {
3765 if (ppd->cpspec->ibdeltainprog) {
3766 ppd->cpspec->ibdeltainprog = 0;
3767 ppd->cpspec->ibsymdelta += read_7220_creg32(ppd->dd,
3768 cr_ibsymbolerr) - ppd->cpspec->ibsymsnap;
3769 ppd->cpspec->iblnkerrdelta += read_7220_creg32(ppd->dd,
3770 cr_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
3771 }
3772 } else if (!ibup && qib_compat_ddr_negotiate &&
3773 !ppd->cpspec->ibdeltainprog &&
3774 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
3775 ppd->cpspec->ibdeltainprog = 1;
3776 ppd->cpspec->ibsymsnap = read_7220_creg32(ppd->dd,
3777 cr_ibsymbolerr);
3778 ppd->cpspec->iblnkerrsnap = read_7220_creg32(ppd->dd,
3779 cr_iblinkerrrecov);
3780 }
3781
3782 if (!ret)
3783 qib_setup_7220_setextled(ppd, ibup);
3784 return ret;
3785}
3786
3787
3788
3789
3790
3791
3792
3793
3794static int gpio_7220_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
3795{
3796 u64 read_val, new_out;
3797 unsigned long flags;
3798
3799 if (mask) {
3800
3801 dir &= mask;
3802 out &= mask;
3803 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
3804 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
3805 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
3806 new_out = (dd->cspec->gpio_out & ~mask) | out;
3807
3808 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
3809 qib_write_kreg(dd, kr_gpio_out, new_out);
3810 dd->cspec->gpio_out = new_out;
3811 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
3812 }
3813
3814
3815
3816
3817
3818
3819
3820
3821 read_val = qib_read_kreg64(dd, kr_extstatus);
3822 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
3823}
3824
3825
3826
3827
3828
3829
3830static void get_7220_chip_params(struct qib_devdata *dd)
3831{
3832 u64 val;
3833 u32 piobufs;
3834 int mtu;
3835
3836 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
3837
3838 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
3839 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
3840 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
3841 dd->palign = qib_read_kreg32(dd, kr_palign);
3842 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
3843 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
3844
3845 val = qib_read_kreg64(dd, kr_sendpiosize);
3846 dd->piosize2k = val & ~0U;
3847 dd->piosize4k = val >> 32;
3848
3849 mtu = ib_mtu_enum_to_int(qib_ibmtu);
3850 if (mtu == -1)
3851 mtu = QIB_DEFAULT_MTU;
3852 dd->pport->ibmtu = (u32)mtu;
3853
3854 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
3855 dd->piobcnt2k = val & ~0U;
3856 dd->piobcnt4k = val >> 32;
3857
3858 dd->pio2kbase = (u32 __iomem *)
3859 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
3860 if (dd->piobcnt4k) {
3861 dd->pio4kbase = (u32 __iomem *)
3862 ((char __iomem *) dd->kregbase +
3863 (dd->piobufbase >> 32));
3864
3865
3866
3867
3868
3869 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
3870 }
3871
3872 piobufs = dd->piobcnt4k + dd->piobcnt2k;
3873
3874 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
3875 (sizeof(u64) * BITS_PER_BYTE / 2);
3876}
3877
3878
3879
3880
3881
3882
3883static void set_7220_baseaddrs(struct qib_devdata *dd)
3884{
3885 u32 cregbase;
3886
3887 cregbase = qib_read_kreg32(dd, kr_counterregbase);
3888 dd->cspec->cregbase = (u64 __iomem *)
3889 ((char __iomem *) dd->kregbase + cregbase);
3890
3891 dd->egrtidbase = (u64 __iomem *)
3892 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
3893}
3894
3895
3896#define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl, SendIntBufAvail) | \
3897 SYM_MASK(SendCtrl, SPioEnable) | \
3898 SYM_MASK(SendCtrl, SSpecialTriggerEn) | \
3899 SYM_MASK(SendCtrl, SendBufAvailUpd) | \
3900 SYM_MASK(SendCtrl, AvailUpdThld) | \
3901 SYM_MASK(SendCtrl, SDmaEnable) | \
3902 SYM_MASK(SendCtrl, SDmaIntEnable) | \
3903 SYM_MASK(SendCtrl, SDmaHalt) | \
3904 SYM_MASK(SendCtrl, SDmaSingleDescriptor))
3905
3906static int sendctrl_hook(struct qib_devdata *dd,
3907 const struct diag_observer *op,
3908 u32 offs, u64 *data, u64 mask, int only_32)
3909{
3910 unsigned long flags;
3911 unsigned idx = offs / sizeof(u64);
3912 u64 local_data, all_bits;
3913
3914 if (idx != kr_sendctrl) {
3915 qib_dev_err(dd, "SendCtrl Hook called with offs %X, %s-bit\n",
3916 offs, only_32 ? "32" : "64");
3917 return 0;
3918 }
3919
3920 all_bits = ~0ULL;
3921 if (only_32)
3922 all_bits >>= 32;
3923 spin_lock_irqsave(&dd->sendctrl_lock, flags);
3924 if ((mask & all_bits) != all_bits) {
3925
3926
3927
3928
3929
3930
3931
3932 if (only_32)
3933 local_data = (u64)qib_read_kreg32(dd, idx);
3934 else
3935 local_data = qib_read_kreg64(dd, idx);
3936 qib_dev_err(dd, "Sendctrl -> %X, Shad -> %X\n",
3937 (u32)local_data, (u32)dd->sendctrl);
3938 if ((local_data & SENDCTRL_SHADOWED) !=
3939 (dd->sendctrl & SENDCTRL_SHADOWED))
3940 qib_dev_err(dd, "Sendctrl read: %X shadow is %X\n",
3941 (u32)local_data, (u32) dd->sendctrl);
3942 *data = (local_data & ~mask) | (*data & mask);
3943 }
3944 if (mask) {
3945
3946
3947
3948
3949 u64 sval, tval;
3950
3951
3952
3953
3954
3955 sval = (dd->sendctrl & ~mask);
3956 sval |= *data & SENDCTRL_SHADOWED & mask;
3957 dd->sendctrl = sval;
3958 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
3959 qib_dev_err(dd, "Sendctrl <- %X, Shad <- %X\n",
3960 (u32)tval, (u32)sval);
3961 qib_write_kreg(dd, kr_sendctrl, tval);
3962 qib_write_kreg(dd, kr_scratch, 0Ull);
3963 }
3964 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
3965
3966 return only_32 ? 4 : 8;
3967}
3968
3969static const struct diag_observer sendctrl_observer = {
3970 sendctrl_hook, kr_sendctrl * sizeof(u64),
3971 kr_sendctrl * sizeof(u64)
3972};
3973
3974
3975
3976
3977
3978
3979static int qib_late_7220_initreg(struct qib_devdata *dd)
3980{
3981 int ret = 0;
3982 u64 val;
3983
3984 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
3985 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
3986 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
3987 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
3988 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
3989 if (val != dd->pioavailregs_phys) {
3990 qib_dev_err(dd,
3991 "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n",
3992 (unsigned long) dd->pioavailregs_phys,
3993 (unsigned long long) val);
3994 ret = -EINVAL;
3995 }
3996 qib_register_observer(dd, &sendctrl_observer);
3997 return ret;
3998}
3999
4000static int qib_init_7220_variables(struct qib_devdata *dd)
4001{
4002 struct qib_chippport_specific *cpspec;
4003 struct qib_pportdata *ppd;
4004 int ret = 0;
4005 u32 sbufs, updthresh;
4006
4007 cpspec = (struct qib_chippport_specific *)(dd + 1);
4008 ppd = &cpspec->pportdata;
4009 dd->pport = ppd;
4010 dd->num_pports = 1;
4011
4012 dd->cspec = (struct qib_chip_specific *)(cpspec + dd->num_pports);
4013 ppd->cpspec = cpspec;
4014
4015 spin_lock_init(&dd->cspec->sdepb_lock);
4016 spin_lock_init(&dd->cspec->rcvmod_lock);
4017 spin_lock_init(&dd->cspec->gpio_lock);
4018
4019
4020 dd->revision = readq(&dd->kregbase[kr_revision]);
4021
4022 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
4023 qib_dev_err(dd,
4024 "Revision register read failure, giving up initialization\n");
4025 ret = -ENODEV;
4026 goto bail;
4027 }
4028 dd->flags |= QIB_PRESENT;
4029
4030 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R,
4031 ChipRevMajor);
4032 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R,
4033 ChipRevMinor);
4034
4035 get_7220_chip_params(dd);
4036 qib_7220_boardname(dd);
4037
4038
4039
4040
4041
4042 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
4043 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
4044 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
4045
4046 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
4047 QIB_NODMA_RTAIL | QIB_HAS_THRESH_UPDATE;
4048 dd->flags |= qib_special_trigger ?
4049 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
4050
4051
4052
4053
4054
4055 dd->eep_st_masks[0].hwerrs_to_log = HWE_MASK(TXEMemParityErr);
4056
4057 dd->eep_st_masks[1].hwerrs_to_log = HWE_MASK(RXEMemParityErr);
4058
4059 dd->eep_st_masks[2].errs_to_log = ERR_MASK(ResetNegated);
4060
4061 init_waitqueue_head(&cpspec->autoneg_wait);
4062 INIT_DELAYED_WORK(&cpspec->autoneg_work, autoneg_7220_work);
4063
4064 qib_init_pportdata(ppd, dd, 0, 1);
4065 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
4066 ppd->link_speed_supported = QIB_IB_SDR | QIB_IB_DDR;
4067
4068 ppd->link_width_enabled = ppd->link_width_supported;
4069 ppd->link_speed_enabled = ppd->link_speed_supported;
4070
4071
4072
4073
4074 ppd->link_width_active = IB_WIDTH_4X;
4075 ppd->link_speed_active = QIB_IB_SDR;
4076 ppd->delay_mult = rate_to_delay[0][1];
4077 ppd->vls_supported = IB_VL_VL0;
4078 ppd->vls_operational = ppd->vls_supported;
4079
4080 if (!qib_mini_init)
4081 qib_write_kreg(dd, kr_rcvbthqp, QIB_KD_QP);
4082
4083 init_timer(&ppd->cpspec->chase_timer);
4084 ppd->cpspec->chase_timer.function = reenable_7220_chase;
4085 ppd->cpspec->chase_timer.data = (unsigned long)ppd;
4086
4087 qib_num_cfg_vls = 1;
4088
4089 dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE;
4090 dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE;
4091 dd->rhf_offset =
4092 dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
4093
4094
4095 ret = ib_mtu_enum_to_int(qib_ibmtu);
4096 dd->rcvegrbufsize = ret != -1 ? max(ret, 2048) : QIB_DEFAULT_MTU;
4097 BUG_ON(!is_power_of_2(dd->rcvegrbufsize));
4098 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
4099
4100 qib_7220_tidtemplate(dd);
4101
4102
4103
4104
4105
4106
4107 dd->rhdrhead_intr_off = 1ULL << 32;
4108
4109
4110 init_timer(&dd->stats_timer);
4111 dd->stats_timer.function = qib_get_7220_faststats;
4112 dd->stats_timer.data = (unsigned long) dd;
4113 dd->stats_timer.expires = jiffies + ACTIVITY_TIMER * HZ;
4114
4115
4116
4117
4118
4119
4120 if (qib_sdma_fetch_arb)
4121 dd->control |= 1 << 4;
4122
4123 dd->ureg_align = 0x10000;
4124
4125 dd->piosize2kmax_dwords = (dd->piosize2k >> 2)-1;
4126 qib_7220_config_ctxts(dd);
4127 qib_set_ctxtcnt(dd);
4128
4129 if (qib_wc_pat) {
4130 ret = init_chip_wc_pat(dd, 0);
4131 if (ret)
4132 goto bail;
4133 }
4134 set_7220_baseaddrs(dd);
4135
4136 ret = 0;
4137 if (qib_mini_init)
4138 goto bail;
4139
4140 ret = qib_create_ctxts(dd);
4141 init_7220_cntrnames(dd);
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153 updthresh = 8U;
4154 if (dd->flags & QIB_HAS_SEND_DMA) {
4155 dd->cspec->sdmabufcnt = dd->piobcnt4k;
4156 sbufs = updthresh > 3 ? updthresh : 3;
4157 } else {
4158 dd->cspec->sdmabufcnt = 0;
4159 sbufs = dd->piobcnt4k;
4160 }
4161
4162 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
4163 dd->cspec->sdmabufcnt;
4164 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
4165 dd->cspec->lastbuf_for_pio--;
4166 dd->last_pio = dd->cspec->lastbuf_for_pio;
4167 dd->pbufsctxt = dd->lastctxt_piobuf /
4168 (dd->cfgctxts - dd->first_user_ctxt);
4169
4170
4171
4172
4173
4174
4175
4176 if ((dd->pbufsctxt - 2) < updthresh)
4177 updthresh = dd->pbufsctxt - 2;
4178
4179 dd->cspec->updthresh_dflt = updthresh;
4180 dd->cspec->updthresh = updthresh;
4181
4182
4183 dd->sendctrl |= (updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
4184 << SYM_LSB(SendCtrl, AvailUpdThld);
4185
4186 dd->psxmitwait_supported = 1;
4187 dd->psxmitwait_check_rate = QIB_7220_PSXMITWAIT_CHECK_RATE;
4188bail:
4189 return ret;
4190}
4191
4192static u32 __iomem *qib_7220_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
4193 u32 *pbufnum)
4194{
4195 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
4196 struct qib_devdata *dd = ppd->dd;
4197 u32 __iomem *buf;
4198
4199 if (((pbc >> 32) & PBC_7220_VL15_SEND_CTRL) &&
4200 !(ppd->lflags & (QIBL_IB_AUTONEG_INPROG | QIBL_LINKACTIVE)))
4201 buf = get_7220_link_buf(ppd, pbufnum);
4202 else {
4203 if ((plen + 1) > dd->piosize2kmax_dwords)
4204 first = dd->piobcnt2k;
4205 else
4206 first = 0;
4207
4208 last = dd->cspec->lastbuf_for_pio;
4209 buf = qib_getsendbuf_range(dd, pbufnum, first, last);
4210 }
4211 return buf;
4212}
4213
4214
4215static void qib_set_cntr_7220_sample(struct qib_pportdata *ppd, u32 intv,
4216 u32 start)
4217{
4218 write_7220_creg(ppd->dd, cr_psinterval, intv);
4219 write_7220_creg(ppd->dd, cr_psstart, start);
4220}
4221
4222
4223
4224
4225
4226
4227
4228
4229static void qib_sdma_update_7220_tail(struct qib_pportdata *ppd, u16 tail)
4230{
4231
4232 wmb();
4233 ppd->sdma_descq_tail = tail;
4234 qib_write_kreg(ppd->dd, kr_senddmatail, tail);
4235}
4236
4237static void qib_sdma_set_7220_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
4238{
4239}
4240
4241static struct sdma_set_state_action sdma_7220_action_table[] = {
4242 [qib_sdma_state_s00_hw_down] = {
4243 .op_enable = 0,
4244 .op_intenable = 0,
4245 .op_halt = 0,
4246 .go_s99_running_tofalse = 1,
4247 },
4248 [qib_sdma_state_s10_hw_start_up_wait] = {
4249 .op_enable = 1,
4250 .op_intenable = 1,
4251 .op_halt = 1,
4252 },
4253 [qib_sdma_state_s20_idle] = {
4254 .op_enable = 1,
4255 .op_intenable = 1,
4256 .op_halt = 1,
4257 },
4258 [qib_sdma_state_s30_sw_clean_up_wait] = {
4259 .op_enable = 0,
4260 .op_intenable = 1,
4261 .op_halt = 0,
4262 },
4263 [qib_sdma_state_s40_hw_clean_up_wait] = {
4264 .op_enable = 1,
4265 .op_intenable = 1,
4266 .op_halt = 1,
4267 },
4268 [qib_sdma_state_s50_hw_halt_wait] = {
4269 .op_enable = 1,
4270 .op_intenable = 1,
4271 .op_halt = 1,
4272 },
4273 [qib_sdma_state_s99_running] = {
4274 .op_enable = 1,
4275 .op_intenable = 1,
4276 .op_halt = 0,
4277 .go_s99_running_totrue = 1,
4278 },
4279};
4280
4281static void qib_7220_sdma_init_early(struct qib_pportdata *ppd)
4282{
4283 ppd->sdma_state.set_state_action = sdma_7220_action_table;
4284}
4285
4286static int init_sdma_7220_regs(struct qib_pportdata *ppd)
4287{
4288 struct qib_devdata *dd = ppd->dd;
4289 unsigned i, n;
4290 u64 senddmabufmask[3] = { 0 };
4291
4292
4293 qib_write_kreg(dd, kr_senddmabase, ppd->sdma_descq_phys);
4294 qib_sdma_7220_setlengen(ppd);
4295 qib_sdma_update_7220_tail(ppd, 0);
4296
4297 qib_write_kreg(dd, kr_senddmaheadaddr, ppd->sdma_head_phys);
4298
4299
4300
4301
4302
4303 n = dd->piobcnt2k + dd->piobcnt4k;
4304 i = n - dd->cspec->sdmabufcnt;
4305
4306 for (; i < n; ++i) {
4307 unsigned word = i / 64;
4308 unsigned bit = i & 63;
4309
4310 BUG_ON(word >= 3);
4311 senddmabufmask[word] |= 1ULL << bit;
4312 }
4313 qib_write_kreg(dd, kr_senddmabufmask0, senddmabufmask[0]);
4314 qib_write_kreg(dd, kr_senddmabufmask1, senddmabufmask[1]);
4315 qib_write_kreg(dd, kr_senddmabufmask2, senddmabufmask[2]);
4316
4317 ppd->sdma_state.first_sendbuf = i;
4318 ppd->sdma_state.last_sendbuf = n;
4319
4320 return 0;
4321}
4322
4323
4324static u16 qib_sdma_7220_gethead(struct qib_pportdata *ppd)
4325{
4326 struct qib_devdata *dd = ppd->dd;
4327 int sane;
4328 int use_dmahead;
4329 u16 swhead;
4330 u16 swtail;
4331 u16 cnt;
4332 u16 hwhead;
4333
4334 use_dmahead = __qib_sdma_running(ppd) &&
4335 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
4336retry:
4337 hwhead = use_dmahead ?
4338 (u16)le64_to_cpu(*ppd->sdma_head_dma) :
4339 (u16)qib_read_kreg32(dd, kr_senddmahead);
4340
4341 swhead = ppd->sdma_descq_head;
4342 swtail = ppd->sdma_descq_tail;
4343 cnt = ppd->sdma_descq_cnt;
4344
4345 if (swhead < swtail) {
4346
4347 sane = (hwhead >= swhead) & (hwhead <= swtail);
4348 } else if (swhead > swtail) {
4349
4350 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
4351 (hwhead <= swtail);
4352 } else {
4353
4354 sane = (hwhead == swhead);
4355 }
4356
4357 if (unlikely(!sane)) {
4358 if (use_dmahead) {
4359
4360 use_dmahead = 0;
4361 goto retry;
4362 }
4363
4364 hwhead = swhead;
4365 }
4366
4367 return hwhead;
4368}
4369
4370static int qib_sdma_7220_busy(struct qib_pportdata *ppd)
4371{
4372 u64 hwstatus = qib_read_kreg64(ppd->dd, kr_senddmastatus);
4373
4374 return (hwstatus & SYM_MASK(SendDmaStatus, ScoreBoardDrainInProg)) ||
4375 (hwstatus & SYM_MASK(SendDmaStatus, AbortInProg)) ||
4376 (hwstatus & SYM_MASK(SendDmaStatus, InternalSDmaEnable)) ||
4377 !(hwstatus & SYM_MASK(SendDmaStatus, ScbEmpty));
4378}
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388static u32 qib_7220_setpbc_control(struct qib_pportdata *ppd, u32 plen,
4389 u8 srate, u8 vl)
4390{
4391 u8 snd_mult = ppd->delay_mult;
4392 u8 rcv_mult = ib_rate_to_delay[srate];
4393 u32 ret = ppd->cpspec->last_delay_mult;
4394
4395 ppd->cpspec->last_delay_mult = (rcv_mult > snd_mult) ?
4396 (plen * (rcv_mult - snd_mult) + 1) >> 1 : 0;
4397
4398
4399 if (vl == 15)
4400 ret |= PBC_7220_VL15_SEND_CTRL;
4401 return ret;
4402}
4403
4404static void qib_7220_initvl15_bufs(struct qib_devdata *dd)
4405{
4406}
4407
4408static void qib_7220_init_ctxt(struct qib_ctxtdata *rcd)
4409{
4410 if (!rcd->ctxt) {
4411 rcd->rcvegrcnt = IBA7220_KRCVEGRCNT;
4412 rcd->rcvegr_tid_base = 0;
4413 } else {
4414 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
4415 rcd->rcvegr_tid_base = IBA7220_KRCVEGRCNT +
4416 (rcd->ctxt - 1) * rcd->rcvegrcnt;
4417 }
4418}
4419
4420static void qib_7220_txchk_change(struct qib_devdata *dd, u32 start,
4421 u32 len, u32 which, struct qib_ctxtdata *rcd)
4422{
4423 int i;
4424 unsigned long flags;
4425
4426 switch (which) {
4427 case TXCHK_CHG_TYPE_KERN:
4428
4429 spin_lock_irqsave(&dd->uctxt_lock, flags);
4430 for (i = dd->first_user_ctxt;
4431 dd->cspec->updthresh != dd->cspec->updthresh_dflt
4432 && i < dd->cfgctxts; i++)
4433 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
4434 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
4435 < dd->cspec->updthresh_dflt)
4436 break;
4437 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
4438 if (i == dd->cfgctxts) {
4439 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4440 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
4441 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
4442 dd->sendctrl |= (dd->cspec->updthresh &
4443 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
4444 SYM_LSB(SendCtrl, AvailUpdThld);
4445 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4446 sendctrl_7220_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
4447 }
4448 break;
4449 case TXCHK_CHG_TYPE_USER:
4450 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4451 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
4452 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
4453 dd->cspec->updthresh = (rcd->piocnt /
4454 rcd->subctxt_cnt) - 1;
4455 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
4456 dd->sendctrl |= (dd->cspec->updthresh &
4457 SYM_RMASK(SendCtrl, AvailUpdThld))
4458 << SYM_LSB(SendCtrl, AvailUpdThld);
4459 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4460 sendctrl_7220_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
4461 } else
4462 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4463 break;
4464 }
4465}
4466
4467static void writescratch(struct qib_devdata *dd, u32 val)
4468{
4469 qib_write_kreg(dd, kr_scratch, val);
4470}
4471
4472#define VALID_TS_RD_REG_MASK 0xBF
4473
4474
4475
4476
4477
4478
4479
4480static int qib_7220_tempsense_rd(struct qib_devdata *dd, int regnum)
4481{
4482 int ret;
4483 u8 rdata;
4484
4485 if (regnum > 7) {
4486 ret = -EINVAL;
4487 goto bail;
4488 }
4489
4490
4491 if (!((1 << regnum) & VALID_TS_RD_REG_MASK)) {
4492 ret = 0;
4493 goto bail;
4494 }
4495
4496 ret = mutex_lock_interruptible(&dd->eep_lock);
4497 if (ret)
4498 goto bail;
4499
4500 ret = qib_twsi_blk_rd(dd, QIB_TWSI_TEMP_DEV, regnum, &rdata, 1);
4501 if (!ret)
4502 ret = rdata;
4503
4504 mutex_unlock(&dd->eep_lock);
4505
4506
4507
4508
4509
4510
4511
4512bail:
4513 return ret;
4514}
4515
4516
4517static int qib_7220_eeprom_wen(struct qib_devdata *dd, int wen)
4518{
4519 return 1;
4520}
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *pdev,
4531 const struct pci_device_id *ent)
4532{
4533 struct qib_devdata *dd;
4534 int ret;
4535 u32 boardid, minwidth;
4536
4537 dd = qib_alloc_devdata(pdev, sizeof(struct qib_chip_specific) +
4538 sizeof(struct qib_chippport_specific));
4539 if (IS_ERR(dd))
4540 goto bail;
4541
4542 dd->f_bringup_serdes = qib_7220_bringup_serdes;
4543 dd->f_cleanup = qib_setup_7220_cleanup;
4544 dd->f_clear_tids = qib_7220_clear_tids;
4545 dd->f_free_irq = qib_7220_free_irq;
4546 dd->f_get_base_info = qib_7220_get_base_info;
4547 dd->f_get_msgheader = qib_7220_get_msgheader;
4548 dd->f_getsendbuf = qib_7220_getsendbuf;
4549 dd->f_gpio_mod = gpio_7220_mod;
4550 dd->f_eeprom_wen = qib_7220_eeprom_wen;
4551 dd->f_hdrqempty = qib_7220_hdrqempty;
4552 dd->f_ib_updown = qib_7220_ib_updown;
4553 dd->f_init_ctxt = qib_7220_init_ctxt;
4554 dd->f_initvl15_bufs = qib_7220_initvl15_bufs;
4555 dd->f_intr_fallback = qib_7220_intr_fallback;
4556 dd->f_late_initreg = qib_late_7220_initreg;
4557 dd->f_setpbc_control = qib_7220_setpbc_control;
4558 dd->f_portcntr = qib_portcntr_7220;
4559 dd->f_put_tid = qib_7220_put_tid;
4560 dd->f_quiet_serdes = qib_7220_quiet_serdes;
4561 dd->f_rcvctrl = rcvctrl_7220_mod;
4562 dd->f_read_cntrs = qib_read_7220cntrs;
4563 dd->f_read_portcntrs = qib_read_7220portcntrs;
4564 dd->f_reset = qib_setup_7220_reset;
4565 dd->f_init_sdma_regs = init_sdma_7220_regs;
4566 dd->f_sdma_busy = qib_sdma_7220_busy;
4567 dd->f_sdma_gethead = qib_sdma_7220_gethead;
4568 dd->f_sdma_sendctrl = qib_7220_sdma_sendctrl;
4569 dd->f_sdma_set_desc_cnt = qib_sdma_set_7220_desc_cnt;
4570 dd->f_sdma_update_tail = qib_sdma_update_7220_tail;
4571 dd->f_sdma_hw_clean_up = qib_7220_sdma_hw_clean_up;
4572 dd->f_sdma_hw_start_up = qib_7220_sdma_hw_start_up;
4573 dd->f_sdma_init_early = qib_7220_sdma_init_early;
4574 dd->f_sendctrl = sendctrl_7220_mod;
4575 dd->f_set_armlaunch = qib_set_7220_armlaunch;
4576 dd->f_set_cntr_sample = qib_set_cntr_7220_sample;
4577 dd->f_iblink_state = qib_7220_iblink_state;
4578 dd->f_ibphys_portstate = qib_7220_phys_portstate;
4579 dd->f_get_ib_cfg = qib_7220_get_ib_cfg;
4580 dd->f_set_ib_cfg = qib_7220_set_ib_cfg;
4581 dd->f_set_ib_loopback = qib_7220_set_loopback;
4582 dd->f_set_intr_state = qib_7220_set_intr_state;
4583 dd->f_setextled = qib_setup_7220_setextled;
4584 dd->f_txchk_change = qib_7220_txchk_change;
4585 dd->f_update_usrhead = qib_update_7220_usrhead;
4586 dd->f_wantpiobuf_intr = qib_wantpiobuf_7220_intr;
4587 dd->f_xgxs_reset = qib_7220_xgxs_reset;
4588 dd->f_writescratch = writescratch;
4589 dd->f_tempsense_rd = qib_7220_tempsense_rd;
4590
4591
4592
4593
4594
4595
4596 ret = qib_pcie_ddinit(dd, pdev, ent);
4597 if (ret < 0)
4598 goto bail_free;
4599
4600
4601 ret = qib_init_7220_variables(dd);
4602 if (ret)
4603 goto bail_cleanup;
4604
4605 if (qib_mini_init)
4606 goto bail;
4607
4608 boardid = SYM_FIELD(dd->revision, Revision,
4609 BoardID);
4610 switch (boardid) {
4611 case 0:
4612 case 2:
4613 case 10:
4614 case 12:
4615 minwidth = 16;
4616 break;
4617 default:
4618 minwidth = 8;
4619 break;
4620 }
4621 if (qib_pcie_params(dd, minwidth, NULL, NULL))
4622 qib_dev_err(dd,
4623 "Failed to setup PCIe or interrupts; continuing anyway\n");
4624
4625
4626 dd->cspec->irq = pdev->irq;
4627
4628 if (qib_read_kreg64(dd, kr_hwerrstatus) &
4629 QLOGIC_IB_HWE_SERDESPLLFAILED)
4630 qib_write_kreg(dd, kr_hwerrclear,
4631 QLOGIC_IB_HWE_SERDESPLLFAILED);
4632
4633
4634 qib_setup_7220_interrupt(dd);
4635 qib_7220_init_hwerrors(dd);
4636
4637
4638 qib_write_kreg(dd, kr_hwdiagctrl, 0);
4639
4640 goto bail;
4641
4642bail_cleanup:
4643 qib_pcie_ddcleanup(dd);
4644bail_free:
4645 qib_free_devdata(dd);
4646 dd = ERR_PTR(ret);
4647bail:
4648 return dd;
4649}
4650