1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39#include <linux/interrupt.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/io.h>
43#include <linux/jiffies.h>
44#include <linux/module.h>
45#include <rdma/ib_verbs.h>
46#include <rdma/ib_smi.h>
47
48#include "qib.h"
49#include "qib_7322_regs.h"
50#include "qib_qsfp.h"
51
52#include "qib_mad.h"
53#include "qib_verbs.h"
54
55#undef pr_fmt
56#define pr_fmt(fmt) QIB_DRV_NAME " " fmt
57
58static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
59static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
60static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
61static irqreturn_t qib_7322intr(int irq, void *data);
62static irqreturn_t qib_7322bufavail(int irq, void *data);
63static irqreturn_t sdma_intr(int irq, void *data);
64static irqreturn_t sdma_idle_intr(int irq, void *data);
65static irqreturn_t sdma_progress_intr(int irq, void *data);
66static irqreturn_t sdma_cleanup_intr(int irq, void *data);
67static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
68 struct qib_ctxtdata *rcd);
69static u8 qib_7322_phys_portstate(u64);
70static u32 qib_7322_iblink_state(u64);
71static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
72 u16 linitcmd);
73static void force_h1(struct qib_pportdata *);
74static void adj_tx_serdes(struct qib_pportdata *);
75static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
76static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
77
78static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
79static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
80static void serdes_7322_los_enable(struct qib_pportdata *, int);
81static int serdes_7322_init_old(struct qib_pportdata *);
82static int serdes_7322_init_new(struct qib_pportdata *);
83
84#define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
85
86
87#define LE2_DEFAULT 5
88#define LE2_5m 4
89#define LE2_QME 0
90
91
92#define IBSD(hw_pidx) (hw_pidx + 2)
93
94
95static const unsigned rcv_int_timeout = 375;
96static const unsigned rcv_int_count = 16;
97static const unsigned sdma_idle_cnt = 64;
98
99
100#define RXEQ_DISABLE_MSECS 2500
101
102
103
104
105
106ushort qib_num_cfg_vls = 2;
107module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
108MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
109
110static ushort qib_chase = 1;
111module_param_named(chase, qib_chase, ushort, S_IRUGO);
112MODULE_PARM_DESC(chase, "Enable state chase handling");
113
114static ushort qib_long_atten = 10;
115module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
116MODULE_PARM_DESC(long_attenuation, \
117 "attenuation cutoff (dB) for long copper cable setup");
118
119static ushort qib_singleport;
120module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
121MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
122
123static ushort qib_krcvq01_no_msi;
124module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO);
125MODULE_PARM_DESC(krcvq01_no_msi, "No MSI for kctx < 2");
126
127
128
129
130static unsigned qib_rcvhdrcnt;
131module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
132MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
133
134static unsigned qib_rcvhdrsize;
135module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
136MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
137
138static unsigned qib_rcvhdrentsize;
139module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
140MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
141
142#define MAX_ATTEN_LEN 64
143
144static char txselect_list[MAX_ATTEN_LEN] = "10";
145static struct kparam_string kp_txselect = {
146 .string = txselect_list,
147 .maxlen = MAX_ATTEN_LEN
148};
149static int setup_txselect(const char *, struct kernel_param *);
150module_param_call(txselect, setup_txselect, param_get_string,
151 &kp_txselect, S_IWUSR | S_IRUGO);
152MODULE_PARM_DESC(txselect, \
153 "Tx serdes indices (for no QSFP or invalid QSFP data)");
154
155#define BOARD_QME7342 5
156#define BOARD_QMH7342 6
157#define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
158 BOARD_QMH7342)
159#define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
160 BOARD_QME7342)
161
162#define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
163
164#define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
165
166#define MASK_ACROSS(lsb, msb) \
167 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
168
169#define SYM_RMASK(regname, fldname) ((u64) \
170 QIB_7322_##regname##_##fldname##_RMASK)
171
172#define SYM_MASK(regname, fldname) ((u64) \
173 QIB_7322_##regname##_##fldname##_RMASK << \
174 QIB_7322_##regname##_##fldname##_LSB)
175
176#define SYM_FIELD(value, regname, fldname) ((u64) \
177 (((value) >> SYM_LSB(regname, fldname)) & \
178 SYM_RMASK(regname, fldname)))
179
180
181#define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
182 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
183
184#define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
185#define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
186#define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
187#define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
188#define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
189
190#define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
191
192
193#define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
194
195
196
197
198
199#define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
200#define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT)
201#define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT)
202#define IBA7322_TID_PA_SHIFT 11U
203
204#define SendIBSLIDAssignMask \
205 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
206#define SendIBSLMCMask \
207 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
208
209#define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
210#define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
211#define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
212#define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
213#define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
214#define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
215
216#define _QIB_GPIO_SDA_NUM 1
217#define _QIB_GPIO_SCL_NUM 0
218#define QIB_EEPROM_WEN_NUM 14
219#define QIB_TWSI_EEPROM_DEV 0xA2
220
221
222#define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
223
224
225#define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
226#define PORT_SPD_CAP_SHIFT 3
227
228
229#define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
230
231
232
233
234
235
236
237#define kr_contextcnt KREG_IDX(ContextCnt)
238#define kr_control KREG_IDX(Control)
239#define kr_counterregbase KREG_IDX(CntrRegBase)
240#define kr_errclear KREG_IDX(ErrClear)
241#define kr_errmask KREG_IDX(ErrMask)
242#define kr_errstatus KREG_IDX(ErrStatus)
243#define kr_extctrl KREG_IDX(EXTCtrl)
244#define kr_extstatus KREG_IDX(EXTStatus)
245#define kr_gpio_clear KREG_IDX(GPIOClear)
246#define kr_gpio_mask KREG_IDX(GPIOMask)
247#define kr_gpio_out KREG_IDX(GPIOOut)
248#define kr_gpio_status KREG_IDX(GPIOStatus)
249#define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
250#define kr_debugportval KREG_IDX(DebugPortValueReg)
251#define kr_fmask KREG_IDX(feature_mask)
252#define kr_act_fmask KREG_IDX(active_feature_mask)
253#define kr_hwerrclear KREG_IDX(HwErrClear)
254#define kr_hwerrmask KREG_IDX(HwErrMask)
255#define kr_hwerrstatus KREG_IDX(HwErrStatus)
256#define kr_intclear KREG_IDX(IntClear)
257#define kr_intmask KREG_IDX(IntMask)
258#define kr_intredirect KREG_IDX(IntRedirect0)
259#define kr_intstatus KREG_IDX(IntStatus)
260#define kr_pagealign KREG_IDX(PageAlign)
261#define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
262#define kr_rcvctrl KREG_IDX(RcvCtrl)
263#define kr_rcvegrbase KREG_IDX(RcvEgrBase)
264#define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
265#define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
266#define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
267#define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
268#define kr_rcvtidbase KREG_IDX(RcvTIDBase)
269#define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
270#define kr_revision KREG_IDX(Revision)
271#define kr_scratch KREG_IDX(Scratch)
272#define kr_sendbuffererror KREG_IDX(SendBufErr0)
273#define kr_sendcheckmask KREG_IDX(SendCheckMask0)
274#define kr_sendctrl KREG_IDX(SendCtrl)
275#define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0)
276#define kr_sendibpktmask KREG_IDX(SendIBPacketMask0)
277#define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
278#define kr_sendpiobufbase KREG_IDX(SendBufBase)
279#define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
280#define kr_sendpiosize KREG_IDX(SendBufSize)
281#define kr_sendregbase KREG_IDX(SendRegBase)
282#define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
283#define kr_userregbase KREG_IDX(UserRegBase)
284#define kr_intgranted KREG_IDX(Int_Granted)
285#define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
286#define kr_intblocked KREG_IDX(IntBlocked)
287#define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
288
289
290
291
292
293#define krp_errclear KREG_IBPORT_IDX(ErrClear)
294#define krp_errmask KREG_IBPORT_IDX(ErrMask)
295#define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
296#define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
297#define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
298#define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
299#define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
300#define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
301#define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
302#define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
303#define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
304#define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
305#define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
306#define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
307#define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
308#define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
309#define krp_psinterval KREG_IBPORT_IDX(PSInterval)
310#define krp_psstart KREG_IBPORT_IDX(PSStart)
311#define krp_psstat KREG_IBPORT_IDX(PSStat)
312#define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
313#define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
314#define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
315#define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
316#define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
317#define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
318#define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
319#define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
320#define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
321#define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
322#define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
323#define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
324#define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
325#define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
326#define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
327#define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
328#define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
329#define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
330#define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
331#define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
332#define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
333#define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
334#define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
335#define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
336#define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
337#define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
338#define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
339#define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
340#define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
341#define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
342#define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
343
344
345
346
347
348#define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
349#define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
350
351
352
353
354
355
356
357
358
359#define NUM_TIDFLOWS_CTXT 0x20
360#define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
361
362
363#define TIDFLOW_ERRBITS ( \
364 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
365 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
366 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
367 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
368
369
370
371
372#define CREG_IDX(regname) \
373((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
374
375#define crp_badformat CREG_IDX(RxVersionErrCnt)
376#define crp_err_rlen CREG_IDX(RxLenErrCnt)
377#define crp_erricrc CREG_IDX(RxICRCErrCnt)
378#define crp_errlink CREG_IDX(RxLinkMalformCnt)
379#define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
380#define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
381#define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
382#define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
383#define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
384#define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
385#define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
386#define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
387#define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
388#define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
389#define crp_pktrcv CREG_IDX(RxDataPktCnt)
390#define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
391#define crp_pktsend CREG_IDX(TxDataPktCnt)
392#define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
393#define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
394#define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
395#define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
396#define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
397#define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
398#define crp_rcvebp CREG_IDX(RxEBPCnt)
399#define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
400#define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
401#define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
402#define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
403#define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
404#define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
405#define crp_rxvlerr CREG_IDX(RxVlErrCnt)
406#define crp_sendstall CREG_IDX(TxFlowStallCnt)
407#define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
408#define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
409#define crp_txlenerr CREG_IDX(TxLenErrCnt)
410#define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
411#define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
412#define crp_txunderrun CREG_IDX(TxUnderrunCnt)
413#define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
414#define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
415#define crp_wordrcv CREG_IDX(RxDwordCnt)
416#define crp_wordsend CREG_IDX(TxDwordCnt)
417#define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
418
419
420#define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
421 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
422#define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
423#define cr_lbint CREG_DEVIDX(LBIntCnt)
424#define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
425#define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
426#define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
427#define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
428#define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
429
430
431#define NUM_IB_PORTS 2
432
433
434#define NUM_VL15_BUFS NUM_IB_PORTS
435
436
437
438
439
440
441
442#define KCTXT0_EGRCNT 2048
443
444
445#define PBC_PORT_SEL_LSB 26
446#define PBC_PORT_SEL_RMASK 1
447#define PBC_VL_NUM_LSB 27
448#define PBC_VL_NUM_RMASK 7
449#define PBC_7322_VL15_SEND (1ULL << 63)
450#define PBC_7322_VL15_SEND_CTRL (1ULL << 31)
451
452static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
453 [IB_RATE_2_5_GBPS] = 16,
454 [IB_RATE_5_GBPS] = 8,
455 [IB_RATE_10_GBPS] = 4,
456 [IB_RATE_20_GBPS] = 2,
457 [IB_RATE_30_GBPS] = 2,
458 [IB_RATE_40_GBPS] = 1
459};
460
461#define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
462#define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
463
464
465#define IB_7322_LT_STATE_DISABLED 0x00
466#define IB_7322_LT_STATE_LINKUP 0x01
467#define IB_7322_LT_STATE_POLLACTIVE 0x02
468#define IB_7322_LT_STATE_POLLQUIET 0x03
469#define IB_7322_LT_STATE_SLEEPDELAY 0x04
470#define IB_7322_LT_STATE_SLEEPQUIET 0x05
471#define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
472#define IB_7322_LT_STATE_CFGRCVFCFG 0x09
473#define IB_7322_LT_STATE_CFGWAITRMT 0x0a
474#define IB_7322_LT_STATE_CFGIDLE 0x0b
475#define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
476#define IB_7322_LT_STATE_TXREVLANES 0x0d
477#define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
478#define IB_7322_LT_STATE_RECOVERIDLE 0x0f
479#define IB_7322_LT_STATE_CFGENH 0x10
480#define IB_7322_LT_STATE_CFGTEST 0x11
481#define IB_7322_LT_STATE_CFGWAITRMTTEST 0x12
482#define IB_7322_LT_STATE_CFGWAITENH 0x13
483
484
485#define IB_7322_L_STATE_DOWN 0x0
486#define IB_7322_L_STATE_INIT 0x1
487#define IB_7322_L_STATE_ARM 0x2
488#define IB_7322_L_STATE_ACTIVE 0x3
489#define IB_7322_L_STATE_ACT_DEFER 0x4
490
491static const u8 qib_7322_physportstate[0x20] = {
492 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
493 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
494 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
495 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
496 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
497 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
498 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
499 [IB_7322_LT_STATE_CFGRCVFCFG] =
500 IB_PHYSPORTSTATE_CFG_TRAIN,
501 [IB_7322_LT_STATE_CFGWAITRMT] =
502 IB_PHYSPORTSTATE_CFG_TRAIN,
503 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
504 [IB_7322_LT_STATE_RECOVERRETRAIN] =
505 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
506 [IB_7322_LT_STATE_RECOVERWAITRMT] =
507 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
508 [IB_7322_LT_STATE_RECOVERIDLE] =
509 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
510 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
511 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
512 [IB_7322_LT_STATE_CFGWAITRMTTEST] =
513 IB_PHYSPORTSTATE_CFG_TRAIN,
514 [IB_7322_LT_STATE_CFGWAITENH] =
515 IB_PHYSPORTSTATE_CFG_WAIT_ENH,
516 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
517 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
518 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
519 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
520};
521
522struct qib_chip_specific {
523 u64 __iomem *cregbase;
524 u64 *cntrs;
525 spinlock_t rcvmod_lock;
526 spinlock_t gpio_lock;
527 u64 main_int_mask;
528 u64 int_enable_mask;
529 u64 errormask;
530 u64 hwerrmask;
531 u64 gpio_out;
532 u64 gpio_mask;
533 u64 extctrl;
534 u32 ncntrs;
535 u32 nportcntrs;
536 u32 cntrnamelen;
537 u32 portcntrnamelen;
538 u32 numctxts;
539 u32 rcvegrcnt;
540 u32 updthresh;
541 u32 updthresh_dflt;
542 u32 r1;
543 int irq;
544 u32 num_msix_entries;
545 u32 sdmabufcnt;
546 u32 lastbuf_for_pio;
547 u32 stay_in_freeze;
548 u32 recovery_ports_initted;
549 struct qib_msix_entry *msix_entries;
550 unsigned long *sendchkenable;
551 unsigned long *sendgrhchk;
552 unsigned long *sendibchk;
553 u32 rcvavail_timeout[18];
554 char emsgbuf[128];
555};
556
557
558struct txdds_ent {
559 u8 amp;
560 u8 pre;
561 u8 main;
562 u8 post;
563};
564
565struct vendor_txdds_ent {
566 u8 oui[QSFP_VOUI_LEN];
567 u8 *partnum;
568 struct txdds_ent sdr;
569 struct txdds_ent ddr;
570 struct txdds_ent qdr;
571};
572
573static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
574
575#define TXDDS_TABLE_SZ 16
576#define TXDDS_EXTRA_SZ 13
577#define TXDDS_MFG_SZ 2
578#define SERDES_CHANS 4
579
580#define H1_FORCE_VAL 8
581#define H1_FORCE_QME 1
582#define H1_FORCE_QMH 7
583
584
585#define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
586 + ((spd) * 2))
587
588#define QDR_DFE_DISABLE_DELAY 4000
589#define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL
590#define QDR_STATIC_ADAPT_DOWN_R1 0ULL
591#define QDR_STATIC_ADAPT_INIT 0xffffffffffULL
592#define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL
593
594struct qib_chippport_specific {
595 u64 __iomem *kpregbase;
596 u64 __iomem *cpregbase;
597 u64 *portcntrs;
598 struct qib_pportdata *ppd;
599 wait_queue_head_t autoneg_wait;
600 struct delayed_work autoneg_work;
601 struct delayed_work ipg_work;
602 struct timer_list chase_timer;
603
604
605
606
607
608
609
610
611 u64 ibdeltainprog;
612 u64 ibsymdelta;
613 u64 ibsymsnap;
614 u64 iblnkerrdelta;
615 u64 iblnkerrsnap;
616 u64 iblnkdownsnap;
617 u64 iblnkdowndelta;
618 u64 ibmalfdelta;
619 u64 ibmalfsnap;
620 u64 ibcctrl_a;
621 u64 ibcctrl_b;
622 unsigned long qdr_dfe_time;
623 unsigned long chase_end;
624 u32 autoneg_tries;
625 u32 recovery_init;
626 u32 qdr_dfe_on;
627 u32 qdr_reforce;
628
629
630
631
632 u8 h1_val;
633 u8 no_eep;
634 u8 ipg_tries;
635 u8 ibmalfusesnap;
636 struct qib_qsfp_data qsfp_data;
637 char epmsgbuf[192];
638};
639
640static struct {
641 const char *name;
642 irq_handler_t handler;
643 int lsb;
644 int port;
645} irq_table[] = {
646 { "", qib_7322intr, -1, 0 },
647 { " (buf avail)", qib_7322bufavail,
648 SYM_LSB(IntStatus, SendBufAvail), 0 },
649 { " (sdma 0)", sdma_intr,
650 SYM_LSB(IntStatus, SDmaInt_0), 1 },
651 { " (sdma 1)", sdma_intr,
652 SYM_LSB(IntStatus, SDmaInt_1), 2 },
653 { " (sdmaI 0)", sdma_idle_intr,
654 SYM_LSB(IntStatus, SDmaIdleInt_0), 1 },
655 { " (sdmaI 1)", sdma_idle_intr,
656 SYM_LSB(IntStatus, SDmaIdleInt_1), 2 },
657 { " (sdmaP 0)", sdma_progress_intr,
658 SYM_LSB(IntStatus, SDmaProgressInt_0), 1 },
659 { " (sdmaP 1)", sdma_progress_intr,
660 SYM_LSB(IntStatus, SDmaProgressInt_1), 2 },
661 { " (sdmaC 0)", sdma_cleanup_intr,
662 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1 },
663 { " (sdmaC 1)", sdma_cleanup_intr,
664 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 },
665};
666
667
668#define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
669
670#define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
671
672#define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
673#define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
674
675#define QLOGIC_IB_IBCC_LINKCMD_DOWN 1
676#define QLOGIC_IB_IBCC_LINKCMD_ARMED 2
677#define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3
678
679#define BLOB_7322_IBCHG 0x101
680
681static inline void qib_write_kreg(const struct qib_devdata *dd,
682 const u32 regno, u64 value);
683static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
684static void write_7322_initregs(struct qib_devdata *);
685static void write_7322_init_portregs(struct qib_pportdata *);
686static void setup_7322_link_recovery(struct qib_pportdata *, u32);
687static void check_7322_rxe_status(struct qib_pportdata *);
688static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
689
690
691
692
693
694
695
696
697
698
699
700static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
701 enum qib_ureg regno, int ctxt)
702{
703 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
704 return 0;
705 return readl(regno + (u64 __iomem *)(
706 (dd->ureg_align * ctxt) + (dd->userbase ?
707 (char __iomem *)dd->userbase :
708 (char __iomem *)dd->kregbase + dd->uregbase)));
709}
710
711
712
713
714
715
716
717
718
719
720
721static inline u64 qib_read_ureg(const struct qib_devdata *dd,
722 enum qib_ureg regno, int ctxt)
723{
724
725 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
726 return 0;
727 return readq(regno + (u64 __iomem *)(
728 (dd->ureg_align * ctxt) + (dd->userbase ?
729 (char __iomem *)dd->userbase :
730 (char __iomem *)dd->kregbase + dd->uregbase)));
731}
732
733
734
735
736
737
738
739
740
741
742static inline void qib_write_ureg(const struct qib_devdata *dd,
743 enum qib_ureg regno, u64 value, int ctxt)
744{
745 u64 __iomem *ubase;
746 if (dd->userbase)
747 ubase = (u64 __iomem *)
748 ((char __iomem *) dd->userbase +
749 dd->ureg_align * ctxt);
750 else
751 ubase = (u64 __iomem *)
752 (dd->uregbase +
753 (char __iomem *) dd->kregbase +
754 dd->ureg_align * ctxt);
755
756 if (dd->kregbase && (dd->flags & QIB_PRESENT))
757 writeq(value, &ubase[regno]);
758}
759
760static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
761 const u32 regno)
762{
763 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
764 return -1;
765 return readl((u32 __iomem *) &dd->kregbase[regno]);
766}
767
768static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
769 const u32 regno)
770{
771 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
772 return -1;
773 return readq(&dd->kregbase[regno]);
774}
775
776static inline void qib_write_kreg(const struct qib_devdata *dd,
777 const u32 regno, u64 value)
778{
779 if (dd->kregbase && (dd->flags & QIB_PRESENT))
780 writeq(value, &dd->kregbase[regno]);
781}
782
783
784
785
786
787static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
788 const u16 regno)
789{
790 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
791 return 0ULL;
792 return readq(&ppd->cpspec->kpregbase[regno]);
793}
794
795static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
796 const u16 regno, u64 value)
797{
798 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
799 (ppd->dd->flags & QIB_PRESENT))
800 writeq(value, &ppd->cpspec->kpregbase[regno]);
801}
802
803
804
805
806
807
808
809
810static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
811 const u16 regno, unsigned ctxt,
812 u64 value)
813{
814 qib_write_kreg(dd, regno + ctxt, value);
815}
816
817static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
818{
819 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
820 return 0;
821 return readq(&dd->cspec->cregbase[regno]);
822
823
824}
825
826static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
827{
828 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
829 return 0;
830 return readl(&dd->cspec->cregbase[regno]);
831
832
833}
834
835static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
836 u16 regno, u64 value)
837{
838 if (ppd->cpspec && ppd->cpspec->cpregbase &&
839 (ppd->dd->flags & QIB_PRESENT))
840 writeq(value, &ppd->cpspec->cpregbase[regno]);
841}
842
843static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
844 u16 regno)
845{
846 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
847 !(ppd->dd->flags & QIB_PRESENT))
848 return 0;
849 return readq(&ppd->cpspec->cpregbase[regno]);
850}
851
852static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
853 u16 regno)
854{
855 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
856 !(ppd->dd->flags & QIB_PRESENT))
857 return 0;
858 return readl(&ppd->cpspec->cpregbase[regno]);
859}
860
861
862#define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
863#define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
864
865
866#define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
867#define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
868#define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
869#define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
870#define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
871#define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
872#define QIB_I_C_ERROR INT_MASK(Err)
873
874#define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
875#define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
876#define QIB_I_GPIO INT_MASK(AssertGPIO)
877#define QIB_I_P_SDMAINT(pidx) \
878 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
879 INT_MASK_P(SDmaProgress, pidx) | \
880 INT_MASK_PM(SDmaCleanupDone, pidx))
881
882
883#define QIB_I_P_BITSEXTANT(pidx) \
884 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
885 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
886 INT_MASK_P(SDmaProgress, pidx) | \
887 INT_MASK_PM(SDmaCleanupDone, pidx))
888
889
890
891#define QIB_I_C_BITSEXTANT \
892 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
893 QIB_I_SPIOSENT | \
894 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
895
896#define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
897 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
898
899
900
901
902#define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
903#define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
904#define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
905#define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
906#define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
907#define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
908#define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
909#define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
910#define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
911#define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
912#define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
913#define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
914#define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
915#define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
916#define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
917#define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
918#define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
919#define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
920#define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
921#define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
922#define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
923#define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
924#define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
925#define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
926#define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
927#define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
928#define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
929#define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
930
931#define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
932#define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
933#define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
934#define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
935#define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
936#define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
937#define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
938#define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
939#define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
940#define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
941#define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
942
943
944#define QIB_E_RESET ERR_MASK(ResetNegated)
945#define QIB_E_HARDWARE ERR_MASK(HardwareErr)
946#define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
947
948
949
950
951
952
953
954
955
956#define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
957#define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
958#define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
959#define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
960#define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
961#define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
962#define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
963#define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
964
965
966
967
968
969
970
971
972
973
974#define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
975#define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
976#define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
977
978
979
980
981
982#define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
983 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
984 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
985 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
986 QIB_E_P_REBP)
987
988
989#define QIB_E_P_RPKTERRS (\
990 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
991 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
992 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
993 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
994 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
995 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
996
997
998
999
1000
1001
1002#define QIB_E_P_SPKTERRS (\
1003 QIB_E_P_SUNEXP_PKTNUM |\
1004 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1005 QIB_E_P_SMAXPKTLEN |\
1006 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1007 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
1008 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
1009
1010#define QIB_E_SPKTERRS ( \
1011 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1012 ERR_MASK_N(SendUnsupportedVLErr) | \
1013 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1014
1015#define QIB_E_P_SDMAERRS ( \
1016 QIB_E_P_SDMAHALT | \
1017 QIB_E_P_SDMADESCADDRMISALIGN | \
1018 QIB_E_P_SDMAUNEXPDATA | \
1019 QIB_E_P_SDMAMISSINGDW | \
1020 QIB_E_P_SDMADWEN | \
1021 QIB_E_P_SDMARPYTAG | \
1022 QIB_E_P_SDMA1STDESC | \
1023 QIB_E_P_SDMABASE | \
1024 QIB_E_P_SDMATAILOUTOFBOUND | \
1025 QIB_E_P_SDMAOUTOFBOUND | \
1026 QIB_E_P_SDMAGENMISMATCH)
1027
1028
1029
1030
1031
1032
1033#define QIB_E_P_BITSEXTANT ( \
1034 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1035 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1036 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1037 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1038 )
1039
1040
1041
1042
1043
1044
1045
1046
1047#define QIB_E_P_LINK_PKTERRS (\
1048 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1049 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1050 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1051 QIB_E_P_RUNEXPCHAR)
1052
1053
1054
1055
1056
1057
1058#define QIB_E_C_BITSEXTANT (\
1059 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1060 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1061 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1062
1063
1064#define E_SPKT_ERRS_IGNORE 0
1065
1066#define QIB_EXTS_MEMBIST_DISABLED \
1067 SYM_MASK(EXTStatus, MemBISTDisabled)
1068#define QIB_EXTS_MEMBIST_ENDTEST \
1069 SYM_MASK(EXTStatus, MemBISTEndTest)
1070
1071#define QIB_E_SPIOARMLAUNCH \
1072 ERR_MASK(SendArmLaunchErr)
1073
1074#define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1075#define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1076
1077
1078
1079
1080
1081
1082
1083#define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1084#define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1085#define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1086#define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1087#define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1088#define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1089 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1090#define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1091
1092#define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1093#define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1094
1095#define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1096#define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1097#define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1098
1099#define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1100#define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1101#define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1102 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1103#define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1104 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1105#define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1106
1107#define IBA7322_REDIRECT_VEC_PER_REG 12
1108
1109#define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1110#define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1111#define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1112#define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1113#define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1114
1115#define AUTONEG_TRIES 3
1116
1117#define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1118 .msg = #fldname , .sz = sizeof(#fldname) }
1119#define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1120 fldname##Mask##_##port), .msg = #fldname , .sz = sizeof(#fldname) }
1121static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1122 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1123 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1124 HWE_AUTO(PCIESerdesPClkNotDetect),
1125 HWE_AUTO(PowerOnBISTFailed),
1126 HWE_AUTO(TempsenseTholdReached),
1127 HWE_AUTO(MemoryErr),
1128 HWE_AUTO(PCIeBusParityErr),
1129 HWE_AUTO(PcieCplTimeout),
1130 HWE_AUTO(PciePoisonedTLP),
1131 HWE_AUTO_P(SDmaMemReadErr, 1),
1132 HWE_AUTO_P(SDmaMemReadErr, 0),
1133 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1134 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
1135 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1136 HWE_AUTO(statusValidNoEop),
1137 HWE_AUTO(LATriggered),
1138 { .mask = 0, .sz = 0 }
1139};
1140
1141#define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1142 .msg = #fldname, .sz = sizeof(#fldname) }
1143#define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1144 .msg = #fldname, .sz = sizeof(#fldname) }
1145static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
1146 E_AUTO(RcvEgrFullErr),
1147 E_AUTO(RcvHdrFullErr),
1148 E_AUTO(ResetNegated),
1149 E_AUTO(HardwareErr),
1150 E_AUTO(InvalidAddrErr),
1151 E_AUTO(SDmaVL15Err),
1152 E_AUTO(SBufVL15MisUseErr),
1153 E_AUTO(InvalidEEPCmd),
1154 E_AUTO(RcvContextShareErr),
1155 E_AUTO(SendVLMismatchErr),
1156 E_AUTO(SendArmLaunchErr),
1157 E_AUTO(SendSpecialTriggerErr),
1158 E_AUTO(SDmaWrongPortErr),
1159 E_AUTO(SDmaBufMaskDuplicateErr),
1160 { .mask = 0, .sz = 0 }
1161};
1162
1163static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1164 E_P_AUTO(IBStatusChanged),
1165 E_P_AUTO(SHeadersErr),
1166 E_P_AUTO(VL15BufMisuseErr),
1167
1168
1169
1170 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted",
1171 .sz = 11},
1172 E_P_AUTO(SDmaDescAddrMisalignErr),
1173 E_P_AUTO(SDmaUnexpDataErr),
1174 E_P_AUTO(SDmaMissingDwErr),
1175 E_P_AUTO(SDmaDwEnErr),
1176 E_P_AUTO(SDmaRpyTagErr),
1177 E_P_AUTO(SDma1stDescErr),
1178 E_P_AUTO(SDmaBaseErr),
1179 E_P_AUTO(SDmaTailOutOfBoundErr),
1180 E_P_AUTO(SDmaOutOfBoundErr),
1181 E_P_AUTO(SDmaGenMismatchErr),
1182 E_P_AUTO(SendBufMisuseErr),
1183 E_P_AUTO(SendUnsupportedVLErr),
1184 E_P_AUTO(SendUnexpectedPktNumErr),
1185 E_P_AUTO(SendDroppedDataPktErr),
1186 E_P_AUTO(SendDroppedSmpPktErr),
1187 E_P_AUTO(SendPktLenErr),
1188 E_P_AUTO(SendUnderRunErr),
1189 E_P_AUTO(SendMaxPktLenErr),
1190 E_P_AUTO(SendMinPktLenErr),
1191 E_P_AUTO(RcvIBLostLinkErr),
1192 E_P_AUTO(RcvHdrErr),
1193 E_P_AUTO(RcvHdrLenErr),
1194 E_P_AUTO(RcvBadTidErr),
1195 E_P_AUTO(RcvBadVersionErr),
1196 E_P_AUTO(RcvIBFlowErr),
1197 E_P_AUTO(RcvEBPErr),
1198 E_P_AUTO(RcvUnsupportedVLErr),
1199 E_P_AUTO(RcvUnexpectedCharErr),
1200 E_P_AUTO(RcvShortPktLenErr),
1201 E_P_AUTO(RcvLongPktLenErr),
1202 E_P_AUTO(RcvMaxPktLenErr),
1203 E_P_AUTO(RcvMinPktLenErr),
1204 E_P_AUTO(RcvICRCErr),
1205 E_P_AUTO(RcvVCRCErr),
1206 E_P_AUTO(RcvFormatErr),
1207 { .mask = 0, .sz = 0 }
1208};
1209
1210
1211
1212
1213
1214#define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1215 .msg = #fldname, .sz = sizeof(#fldname) }
1216
1217#define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1218 SYM_LSB(IntMask, fldname##Mask##_0), \
1219 SYM_LSB(IntMask, fldname##Mask##_1)), \
1220 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1221
1222#define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1223 SYM_LSB(IntMask, fldname##Mask##_1), \
1224 SYM_LSB(IntMask, fldname##Mask##_0)), \
1225 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1226
1227
1228
1229
1230#define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1231 SYM_LSB(IntMask, fldname##0IntMask), \
1232 SYM_LSB(IntMask, fldname##17IntMask)), \
1233 .msg = #fldname "_C", .sz = sizeof(#fldname "_C") }
1234
1235static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = {
1236 INTR_AUTO_P(SDmaInt),
1237 INTR_AUTO_P(SDmaProgressInt),
1238 INTR_AUTO_P(SDmaIdleInt),
1239 INTR_AUTO_P(SDmaCleanupDone),
1240 INTR_AUTO_C(RcvUrg),
1241 INTR_AUTO_P(ErrInt),
1242 INTR_AUTO(ErrInt),
1243 INTR_AUTO(AssertGPIOInt),
1244 INTR_AUTO_P(SendDoneInt),
1245 INTR_AUTO(SendBufAvailInt),
1246 INTR_AUTO_C(RcvAvail),
1247 { .mask = 0, .sz = 0 }
1248};
1249
1250#define TXSYMPTOM_AUTO_P(fldname) \
1251 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \
1252 .msg = #fldname, .sz = sizeof(#fldname) }
1253static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1254 TXSYMPTOM_AUTO_P(NonKeyPacket),
1255 TXSYMPTOM_AUTO_P(GRHFail),
1256 TXSYMPTOM_AUTO_P(PkeyFail),
1257 TXSYMPTOM_AUTO_P(QPFail),
1258 TXSYMPTOM_AUTO_P(SLIDFail),
1259 TXSYMPTOM_AUTO_P(RawIPV6),
1260 TXSYMPTOM_AUTO_P(PacketTooSmall),
1261 { .mask = 0, .sz = 0 }
1262};
1263
1264#define IBA7322_HDRHEAD_PKTINT_SHIFT 32
1265
1266
1267
1268
1269
1270
1271static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1272{
1273 struct qib_devdata *dd = ppd->dd;
1274 u32 i;
1275 int any;
1276 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1277 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1278 unsigned long sbuf[4];
1279
1280
1281
1282
1283
1284 any = 0;
1285 for (i = 0; i < regcnt; ++i) {
1286 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1287 if (sbuf[i]) {
1288 any = 1;
1289 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1290 }
1291 }
1292
1293 if (any)
1294 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1295}
1296
1297
1298
1299
1300static void err_decode(char *msg, size_t len, u64 errs,
1301 const struct qib_hwerror_msgs *msp)
1302{
1303 u64 these, lmask;
1304 int took, multi, n = 0;
1305
1306 while (errs && msp && msp->mask) {
1307 multi = (msp->mask & (msp->mask - 1));
1308 while (errs & msp->mask) {
1309 these = (errs & msp->mask);
1310 lmask = (these & (these - 1)) ^ these;
1311 if (len) {
1312 if (n++) {
1313
1314 *msg++ = ',';
1315 len--;
1316 }
1317 BUG_ON(!msp->sz);
1318
1319 took = min_t(size_t, msp->sz - (size_t)1, len);
1320 memcpy(msg, msp->msg, took);
1321 len -= took;
1322 msg += took;
1323 if (len)
1324 *msg = '\0';
1325 }
1326 errs &= ~lmask;
1327 if (len && multi) {
1328
1329 int idx = -1;
1330
1331 while (lmask & msp->mask) {
1332 ++idx;
1333 lmask >>= 1;
1334 }
1335 took = scnprintf(msg, len, "_%d", idx);
1336 len -= took;
1337 msg += took;
1338 }
1339 }
1340 ++msp;
1341 }
1342
1343 if (len && errs)
1344 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1345 (unsigned long long) errs);
1346}
1347
1348
1349static void flush_fifo(struct qib_pportdata *ppd)
1350{
1351 struct qib_devdata *dd = ppd->dd;
1352 u32 __iomem *piobuf;
1353 u32 bufn;
1354 u32 *hdr;
1355 u64 pbc;
1356 const unsigned hdrwords = 7;
1357 static struct qib_ib_header ibhdr = {
1358 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1359 .lrh[1] = IB_LID_PERMISSIVE,
1360 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1361 .lrh[3] = IB_LID_PERMISSIVE,
1362 .u.oth.bth[0] = cpu_to_be32(
1363 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1364 .u.oth.bth[1] = cpu_to_be32(0),
1365 .u.oth.bth[2] = cpu_to_be32(0),
1366 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1367 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1368 };
1369
1370
1371
1372
1373
1374 pbc = PBC_7322_VL15_SEND |
1375 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1376 (hdrwords + SIZE_OF_CRC);
1377 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1378 if (!piobuf)
1379 return;
1380 writeq(pbc, piobuf);
1381 hdr = (u32 *) &ibhdr;
1382 if (dd->flags & QIB_PIO_FLUSH_WC) {
1383 qib_flush_wc();
1384 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1385 qib_flush_wc();
1386 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1387 qib_flush_wc();
1388 } else
1389 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1390 qib_sendbuf_done(dd, bufn);
1391}
1392
1393
1394
1395
1396static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1397{
1398 struct qib_devdata *dd = ppd->dd;
1399 u64 set_sendctrl = 0;
1400 u64 clr_sendctrl = 0;
1401
1402 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1403 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1404 else
1405 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1406
1407 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1408 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1409 else
1410 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1411
1412 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1413 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1414 else
1415 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1416
1417 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1418 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1419 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1420 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1421 else
1422 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1423 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1424 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1425
1426 spin_lock(&dd->sendctrl_lock);
1427
1428
1429 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1430 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1431 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1432 qib_write_kreg(dd, kr_scratch, 0);
1433 }
1434
1435 ppd->p_sendctrl |= set_sendctrl;
1436 ppd->p_sendctrl &= ~clr_sendctrl;
1437
1438 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1439 qib_write_kreg_port(ppd, krp_sendctrl,
1440 ppd->p_sendctrl |
1441 SYM_MASK(SendCtrl_0, SDmaCleanup));
1442 else
1443 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1444 qib_write_kreg(dd, kr_scratch, 0);
1445
1446 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1447 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1448 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1449 qib_write_kreg(dd, kr_scratch, 0);
1450 }
1451
1452 spin_unlock(&dd->sendctrl_lock);
1453
1454 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1455 flush_fifo(ppd);
1456}
1457
1458static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1459{
1460 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1461}
1462
1463static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1464{
1465
1466
1467
1468
1469
1470 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1471 qib_write_kreg_port(ppd, krp_senddmalengen,
1472 ppd->sdma_descq_cnt |
1473 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1474}
1475
1476
1477
1478
1479static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1480{
1481
1482 wmb();
1483 ppd->sdma_descq_tail = tail;
1484 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1485}
1486
1487
1488
1489
1490static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1491{
1492
1493
1494
1495
1496
1497
1498 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1499
1500 qib_sdma_7322_setlengen(ppd);
1501 qib_sdma_update_7322_tail(ppd, 0);
1502 ppd->sdma_head_dma[0] = 0;
1503 qib_7322_sdma_sendctrl(ppd,
1504 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1505}
1506
1507#define DISABLES_SDMA ( \
1508 QIB_E_P_SDMAHALT | \
1509 QIB_E_P_SDMADESCADDRMISALIGN | \
1510 QIB_E_P_SDMAMISSINGDW | \
1511 QIB_E_P_SDMADWEN | \
1512 QIB_E_P_SDMARPYTAG | \
1513 QIB_E_P_SDMA1STDESC | \
1514 QIB_E_P_SDMABASE | \
1515 QIB_E_P_SDMATAILOUTOFBOUND | \
1516 QIB_E_P_SDMAOUTOFBOUND | \
1517 QIB_E_P_SDMAGENMISMATCH)
1518
1519static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1520{
1521 unsigned long flags;
1522 struct qib_devdata *dd = ppd->dd;
1523
1524 errs &= QIB_E_P_SDMAERRS;
1525
1526 if (errs & QIB_E_P_SDMAUNEXPDATA)
1527 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1528 ppd->port);
1529
1530 spin_lock_irqsave(&ppd->sdma_lock, flags);
1531
1532 switch (ppd->sdma_state.current_state) {
1533 case qib_sdma_state_s00_hw_down:
1534 break;
1535
1536 case qib_sdma_state_s10_hw_start_up_wait:
1537 if (errs & QIB_E_P_SDMAHALT)
1538 __qib_sdma_process_event(ppd,
1539 qib_sdma_event_e20_hw_started);
1540 break;
1541
1542 case qib_sdma_state_s20_idle:
1543 break;
1544
1545 case qib_sdma_state_s30_sw_clean_up_wait:
1546 break;
1547
1548 case qib_sdma_state_s40_hw_clean_up_wait:
1549 if (errs & QIB_E_P_SDMAHALT)
1550 __qib_sdma_process_event(ppd,
1551 qib_sdma_event_e50_hw_cleaned);
1552 break;
1553
1554 case qib_sdma_state_s50_hw_halt_wait:
1555 if (errs & QIB_E_P_SDMAHALT)
1556 __qib_sdma_process_event(ppd,
1557 qib_sdma_event_e60_hw_halted);
1558 break;
1559
1560 case qib_sdma_state_s99_running:
1561 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1562 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1563 break;
1564 }
1565
1566 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1567}
1568
1569
1570
1571
1572static noinline void handle_7322_errors(struct qib_devdata *dd)
1573{
1574 char *msg;
1575 u64 iserr = 0;
1576 u64 errs;
1577 u64 mask;
1578 int log_idx;
1579
1580 qib_stats.sps_errints++;
1581 errs = qib_read_kreg64(dd, kr_errstatus);
1582 if (!errs) {
1583 qib_devinfo(dd->pcidev,
1584 "device error interrupt, but no error bits set!\n");
1585 goto done;
1586 }
1587
1588
1589 errs &= dd->cspec->errormask;
1590 msg = dd->cspec->emsgbuf;
1591
1592
1593 if (errs & QIB_E_HARDWARE) {
1594 *msg = '\0';
1595 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1596 } else
1597 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1598 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1599 qib_inc_eeprom_err(dd, log_idx, 1);
1600
1601 if (errs & QIB_E_SPKTERRS) {
1602 qib_disarm_7322_senderrbufs(dd->pport);
1603 qib_stats.sps_txerrs++;
1604 } else if (errs & QIB_E_INVALIDADDR)
1605 qib_stats.sps_txerrs++;
1606 else if (errs & QIB_E_ARMLAUNCH) {
1607 qib_stats.sps_txerrs++;
1608 qib_disarm_7322_senderrbufs(dd->pport);
1609 }
1610 qib_write_kreg(dd, kr_errclear, errs);
1611
1612
1613
1614
1615
1616
1617 mask = QIB_E_HARDWARE;
1618 *msg = '\0';
1619
1620 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask,
1621 qib_7322error_msgs);
1622
1623
1624
1625
1626
1627 if (errs & QIB_E_RESET) {
1628 int pidx;
1629
1630 qib_dev_err(dd,
1631 "Got reset, requires re-init (unload and reload driver)\n");
1632 dd->flags &= ~QIB_INITTED;
1633
1634 *dd->devstatusp |= QIB_STATUS_HWERROR;
1635 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1636 if (dd->pport[pidx].link_speed_supported)
1637 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1638 }
1639
1640 if (*msg && iserr)
1641 qib_dev_err(dd, "%s error\n", msg);
1642
1643
1644
1645
1646
1647
1648
1649
1650 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1651 qib_handle_urcv(dd, ~0U);
1652 if (errs & ERR_MASK(RcvEgrFullErr))
1653 qib_stats.sps_buffull++;
1654 else
1655 qib_stats.sps_hdrfull++;
1656 }
1657
1658done:
1659 return;
1660}
1661
1662static void qib_error_tasklet(unsigned long data)
1663{
1664 struct qib_devdata *dd = (struct qib_devdata *)data;
1665
1666 handle_7322_errors(dd);
1667 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1668}
1669
1670static void reenable_chase(unsigned long opaque)
1671{
1672 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1673
1674 ppd->cpspec->chase_timer.expires = 0;
1675 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1676 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1677}
1678
1679static void disable_chase(struct qib_pportdata *ppd, unsigned long tnow,
1680 u8 ibclt)
1681{
1682 ppd->cpspec->chase_end = 0;
1683
1684 if (!qib_chase)
1685 return;
1686
1687 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1688 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1689 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1690 add_timer(&ppd->cpspec->chase_timer);
1691}
1692
1693static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1694{
1695 u8 ibclt;
1696 unsigned long tnow;
1697
1698 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1699
1700
1701
1702
1703
1704
1705
1706 switch (ibclt) {
1707 case IB_7322_LT_STATE_CFGRCVFCFG:
1708 case IB_7322_LT_STATE_CFGWAITRMT:
1709 case IB_7322_LT_STATE_TXREVLANES:
1710 case IB_7322_LT_STATE_CFGENH:
1711 tnow = jiffies;
1712 if (ppd->cpspec->chase_end &&
1713 time_after(tnow, ppd->cpspec->chase_end))
1714 disable_chase(ppd, tnow, ibclt);
1715 else if (!ppd->cpspec->chase_end)
1716 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1717 break;
1718 default:
1719 ppd->cpspec->chase_end = 0;
1720 break;
1721 }
1722
1723 if (((ibclt >= IB_7322_LT_STATE_CFGTEST &&
1724 ibclt <= IB_7322_LT_STATE_CFGWAITENH) ||
1725 ibclt == IB_7322_LT_STATE_LINKUP) &&
1726 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1727 force_h1(ppd);
1728 ppd->cpspec->qdr_reforce = 1;
1729 if (!ppd->dd->cspec->r1)
1730 serdes_7322_los_enable(ppd, 0);
1731 } else if (ppd->cpspec->qdr_reforce &&
1732 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1733 (ibclt == IB_7322_LT_STATE_CFGENH ||
1734 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1735 ibclt == IB_7322_LT_STATE_LINKUP))
1736 force_h1(ppd);
1737
1738 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1739 ppd->link_speed_enabled == QIB_IB_QDR &&
1740 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1741 ibclt == IB_7322_LT_STATE_CFGENH ||
1742 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1743 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1744 adj_tx_serdes(ppd);
1745
1746 if (ibclt != IB_7322_LT_STATE_LINKUP) {
1747 u8 ltstate = qib_7322_phys_portstate(ibcst);
1748 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
1749 LinkTrainingState);
1750 if (!ppd->dd->cspec->r1 &&
1751 pibclt == IB_7322_LT_STATE_LINKUP &&
1752 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1753 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1754 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1755 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1756
1757
1758 serdes_7322_los_enable(ppd, 1);
1759 if (!ppd->cpspec->qdr_dfe_on &&
1760 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1761 ppd->cpspec->qdr_dfe_on = 1;
1762 ppd->cpspec->qdr_dfe_time = 0;
1763
1764 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1765 ppd->dd->cspec->r1 ?
1766 QDR_STATIC_ADAPT_DOWN_R1 :
1767 QDR_STATIC_ADAPT_DOWN);
1768 pr_info(
1769 "IB%u:%u re-enabled QDR adaptation ibclt %x\n",
1770 ppd->dd->unit, ppd->port, ibclt);
1771 }
1772 }
1773}
1774
1775static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32);
1776
1777
1778
1779
1780
1781
1782static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1783{
1784 char *msg;
1785 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1786 struct qib_devdata *dd = ppd->dd;
1787
1788
1789 fmask = qib_read_kreg64(dd, kr_act_fmask);
1790 if (!fmask)
1791 check_7322_rxe_status(ppd);
1792
1793 errs = qib_read_kreg_port(ppd, krp_errstatus);
1794 if (!errs)
1795 qib_devinfo(dd->pcidev,
1796 "Port%d error interrupt, but no error bits set!\n",
1797 ppd->port);
1798 if (!fmask)
1799 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1800 if (!errs)
1801 goto done;
1802
1803 msg = ppd->cpspec->epmsgbuf;
1804 *msg = '\0';
1805
1806 if (errs & ~QIB_E_P_BITSEXTANT) {
1807 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1808 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1809 if (!*msg)
1810 snprintf(msg, sizeof ppd->cpspec->epmsgbuf,
1811 "no others");
1812 qib_dev_porterr(dd, ppd->port,
1813 "error interrupt with unknown errors 0x%016Lx set (and %s)\n",
1814 (errs & ~QIB_E_P_BITSEXTANT), msg);
1815 *msg = '\0';
1816 }
1817
1818 if (errs & QIB_E_P_SHDR) {
1819 u64 symptom;
1820
1821
1822 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1823 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
1824 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, symptom,
1825 hdrchk_msgs);
1826 *msg = '\0';
1827
1828 }
1829
1830 if (errs & QIB_E_P_SPKTERRS) {
1831 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1832 !(ppd->lflags & QIBL_LINKACTIVE)) {
1833
1834
1835
1836
1837
1838
1839
1840 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1841 (errs & QIB_E_P_LINK_PKTERRS),
1842 qib_7322p_error_msgs);
1843 *msg = '\0';
1844 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1845 }
1846 qib_disarm_7322_senderrbufs(ppd);
1847 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1848 !(ppd->lflags & QIBL_LINKACTIVE)) {
1849
1850
1851
1852
1853
1854
1855
1856 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, errs,
1857 qib_7322p_error_msgs);
1858 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1859 *msg = '\0';
1860 }
1861
1862 qib_write_kreg_port(ppd, krp_errclear, errs);
1863
1864 errs &= ~ignore_this_time;
1865 if (!errs)
1866 goto done;
1867
1868 if (errs & QIB_E_P_RPKTERRS)
1869 qib_stats.sps_rcverrs++;
1870 if (errs & QIB_E_P_SPKTERRS)
1871 qib_stats.sps_txerrs++;
1872
1873 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1874
1875 if (errs & QIB_E_P_SDMAERRS)
1876 sdma_7322_p_errors(ppd, errs);
1877
1878 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1879 u64 ibcs;
1880 u8 ltstate;
1881
1882 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1883 ltstate = qib_7322_phys_portstate(ibcs);
1884
1885 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1886 handle_serdes_issues(ppd, ibcs);
1887 if (!(ppd->cpspec->ibcctrl_a &
1888 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1889
1890
1891
1892
1893
1894 ppd->cpspec->ibcctrl_a |=
1895 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1896 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1897 ppd->cpspec->ibcctrl_a);
1898 }
1899
1900
1901 ppd->link_width_active =
1902 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1903 IB_WIDTH_4X : IB_WIDTH_1X;
1904 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1905 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1906 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1907 QIB_IB_DDR : QIB_IB_SDR;
1908
1909 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1910 IB_PHYSPORTSTATE_DISABLED)
1911 qib_set_ib_7322_lstate(ppd, 0,
1912 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1913 else
1914
1915
1916
1917
1918
1919
1920
1921
1922 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1923 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1924 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1925 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1926 qib_handle_e_ibstatuschanged(ppd, ibcs);
1927 }
1928 if (*msg && iserr)
1929 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1930
1931 if (ppd->state_wanted & ppd->lflags)
1932 wake_up_interruptible(&ppd->state_wait);
1933done:
1934 return;
1935}
1936
1937
1938static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
1939{
1940 if (enable) {
1941 if (dd->flags & QIB_BADINTR)
1942 return;
1943 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
1944
1945 qib_write_kreg(dd, kr_intclear, 0ULL);
1946 if (dd->cspec->num_msix_entries) {
1947
1948 u64 val = qib_read_kreg64(dd, kr_intgranted);
1949 if (val)
1950 qib_write_kreg(dd, kr_intgranted, val);
1951 }
1952 } else
1953 qib_write_kreg(dd, kr_intmask, 0ULL);
1954}
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971static void qib_7322_clear_freeze(struct qib_devdata *dd)
1972{
1973 int pidx;
1974
1975
1976 qib_write_kreg(dd, kr_errmask, 0ULL);
1977
1978 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1979 if (dd->pport[pidx].link_speed_supported)
1980 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
1981 0ULL);
1982
1983
1984 qib_7322_set_intr_state(dd, 0);
1985
1986
1987 qib_write_kreg(dd, kr_control, dd->control);
1988 qib_read_kreg32(dd, kr_scratch);
1989
1990
1991
1992
1993
1994
1995
1996 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1997 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1998 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1999
2000 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
2001 if (!dd->pport[pidx].link_speed_supported)
2002 continue;
2003 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
2004 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
2005 }
2006 qib_7322_set_intr_state(dd, 1);
2007}
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
2022 size_t msgl)
2023{
2024 u64 hwerrs;
2025 u32 ctrl;
2026 int isfatal = 0;
2027
2028 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2029 if (!hwerrs)
2030 goto bail;
2031 if (hwerrs == ~0ULL) {
2032 qib_dev_err(dd,
2033 "Read of hardware error status failed (all bits set); ignoring\n");
2034 goto bail;
2035 }
2036 qib_stats.sps_hwerrs++;
2037
2038
2039 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
2040 ~HWE_MASK(PowerOnBISTFailed));
2041
2042 hwerrs &= dd->cspec->hwerrmask;
2043
2044
2045
2046 if (hwerrs)
2047 qib_devinfo(dd->pcidev,
2048 "Hardware error: hwerr=0x%llx (cleared)\n",
2049 (unsigned long long) hwerrs);
2050
2051 ctrl = qib_read_kreg32(dd, kr_control);
2052 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2053
2054
2055
2056 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2057 dd->cspec->stay_in_freeze) {
2058
2059
2060
2061
2062
2063
2064
2065 if (dd->flags & QIB_INITTED)
2066 isfatal = 1;
2067 } else
2068 qib_7322_clear_freeze(dd);
2069 }
2070
2071 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2072 isfatal = 1;
2073 strlcpy(msg,
2074 "[Memory BIST test failed, InfiniPath hardware unusable]",
2075 msgl);
2076
2077 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2078 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2079 }
2080
2081 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2082
2083
2084
2085 qib_dev_err(dd, "%s hardware error\n", msg);
2086
2087 if (isfatal && !dd->diag_client) {
2088 qib_dev_err(dd,
2089 "Fatal Hardware Error, no longer usable, SN %.16s\n",
2090 dd->serial);
2091
2092
2093
2094
2095 if (dd->freezemsg)
2096 snprintf(dd->freezemsg, dd->freezelen,
2097 "{%s}", msg);
2098 qib_disable_after_error(dd);
2099 }
2100bail:;
2101}
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2114{
2115 int pidx;
2116 u64 extsval;
2117
2118 extsval = qib_read_kreg64(dd, kr_extstatus);
2119 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2120 QIB_EXTS_MEMBIST_ENDTEST)))
2121 qib_dev_err(dd, "MemBIST did not complete!\n");
2122
2123
2124 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2125 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2126
2127
2128 qib_write_kreg(dd, kr_errclear, ~0ULL);
2129
2130 qib_write_kreg(dd, kr_errmask, ~0ULL);
2131 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2132 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2133 if (dd->pport[pidx].link_speed_supported)
2134 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2135 ~0ULL);
2136}
2137
2138
2139
2140
2141
2142
2143
2144static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2145{
2146 if (enable) {
2147 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2148 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2149 } else
2150 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2151 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2152}
2153
2154
2155
2156
2157
2158
2159static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2160 u16 linitcmd)
2161{
2162 u64 mod_wd;
2163 struct qib_devdata *dd = ppd->dd;
2164 unsigned long flags;
2165
2166 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2167
2168
2169
2170
2171
2172
2173
2174 qib_7322_mini_pcs_reset(ppd);
2175 spin_lock_irqsave(&ppd->lflags_lock, flags);
2176 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2177 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2178 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2179
2180
2181
2182
2183
2184 spin_lock_irqsave(&ppd->lflags_lock, flags);
2185 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2186 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2187
2188
2189
2190
2191 ppd->cpspec->ibcctrl_a &=
2192 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2193 }
2194
2195 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2196 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2197
2198 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2199 mod_wd);
2200
2201 qib_write_kreg(dd, kr_scratch, 0);
2202
2203}
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213#define RCV_BUF_UNITSZ 64
2214#define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2215
2216static void set_vls(struct qib_pportdata *ppd)
2217{
2218 int i, numvls, totcred, cred_vl, vl0extra;
2219 struct qib_devdata *dd = ppd->dd;
2220 u64 val;
2221
2222 numvls = qib_num_vls(ppd->vls_operational);
2223
2224
2225
2226
2227
2228
2229
2230
2231 totcred = NUM_RCV_BUF_UNITS(dd);
2232 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2233 totcred -= cred_vl;
2234 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2235 cred_vl = totcred / numvls;
2236 vl0extra = totcred - cred_vl * numvls;
2237 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2238 for (i = 1; i < numvls; i++)
2239 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2240 for (; i < 8; i++)
2241 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2242
2243
2244 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2245 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2246 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2247 qib_write_kreg(dd, kr_scratch, 0ULL);
2248 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2249 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2250
2251 for (i = 0; i < numvls; i++)
2252 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2253 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2254
2255
2256 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2257 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2258 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2259 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2260 qib_write_kreg(dd, kr_scratch, 0ULL);
2261}
2262
2263
2264
2265
2266
2267static int serdes_7322_init(struct qib_pportdata *ppd);
2268
2269
2270
2271
2272
2273static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2274{
2275 struct qib_devdata *dd = ppd->dd;
2276 u64 val, guid, ibc;
2277 unsigned long flags;
2278 int ret = 0;
2279
2280
2281
2282
2283
2284
2285
2286 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2287 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2288 qib_write_kreg(dd, kr_scratch, 0ULL);
2289
2290 if (qib_compat_ddr_negotiate) {
2291 ppd->cpspec->ibdeltainprog = 1;
2292 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2293 crp_ibsymbolerr);
2294 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2295 crp_iblinkerrrecov);
2296 }
2297
2298
2299 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2300
2301
2302
2303
2304
2305 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2306
2307 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2308
2309 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2310
2311
2312
2313
2314 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2315 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2316 ppd->cpspec->ibcctrl_a = ibc;
2317
2318
2319
2320
2321
2322 qib_7322_mini_pcs_reset(ppd);
2323
2324 if (!ppd->cpspec->ibcctrl_b) {
2325 unsigned lse = ppd->link_speed_enabled;
2326
2327
2328
2329
2330
2331 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2332 krp_ibcctrl_b);
2333 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2334 IBA7322_IBC_SPEED_DDR |
2335 IBA7322_IBC_SPEED_SDR |
2336 IBA7322_IBC_WIDTH_AUTONEG |
2337 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2338 if (lse & (lse - 1))
2339 ppd->cpspec->ibcctrl_b |=
2340 (lse << IBA7322_IBC_SPEED_LSB) |
2341 IBA7322_IBC_IBTA_1_2_MASK |
2342 IBA7322_IBC_MAX_SPEED_MASK;
2343 else
2344 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2345 IBA7322_IBC_SPEED_QDR |
2346 IBA7322_IBC_IBTA_1_2_MASK :
2347 (lse == QIB_IB_DDR) ?
2348 IBA7322_IBC_SPEED_DDR :
2349 IBA7322_IBC_SPEED_SDR;
2350 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2351 (IB_WIDTH_1X | IB_WIDTH_4X))
2352 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2353 else
2354 ppd->cpspec->ibcctrl_b |=
2355 ppd->link_width_enabled == IB_WIDTH_4X ?
2356 IBA7322_IBC_WIDTH_4X_ONLY :
2357 IBA7322_IBC_WIDTH_1X_ONLY;
2358
2359
2360 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2361 IBA7322_IBC_HRTBT_MASK);
2362 }
2363 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2364
2365
2366 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2367 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2368 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2369 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2370
2371 serdes_7322_init(ppd);
2372
2373 guid = be64_to_cpu(ppd->guid);
2374 if (!guid) {
2375 if (dd->base_guid)
2376 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2377 ppd->guid = cpu_to_be64(guid);
2378 }
2379
2380 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2381
2382 qib_write_kreg(dd, kr_scratch, 0);
2383
2384
2385 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2386 set_vls(ppd);
2387
2388
2389 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2390 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2391 qib_write_kreg_port(ppd, krp_ibcctrl_a, val);
2392 qib_write_kreg(dd, kr_scratch, 0ULL);
2393
2394 ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd);
2395
2396
2397 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2398 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2399 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2400 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2401
2402
2403 val = qib_read_kreg_port(ppd, krp_errmask);
2404 qib_write_kreg_port(ppd, krp_errmask,
2405 val | ERR_MASK_N(IBStatusChanged));
2406
2407
2408 return ret;
2409}
2410
2411
2412
2413
2414
2415
2416static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2417{
2418 u64 val;
2419 unsigned long flags;
2420
2421 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2422
2423 spin_lock_irqsave(&ppd->lflags_lock, flags);
2424 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2425 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2426 wake_up(&ppd->cpspec->autoneg_wait);
2427 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
2428 if (ppd->dd->cspec->r1)
2429 cancel_delayed_work_sync(&ppd->cpspec->ipg_work);
2430
2431 ppd->cpspec->chase_end = 0;
2432 if (ppd->cpspec->chase_timer.data)
2433 del_timer_sync(&ppd->cpspec->chase_timer);
2434
2435
2436
2437
2438
2439
2440
2441
2442 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2443 qib_7322_mini_pcs_reset(ppd);
2444
2445
2446
2447
2448
2449 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2450 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2451 struct qib_devdata *dd = ppd->dd;
2452 u64 diagc;
2453
2454
2455 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2456 qib_write_kreg(dd, kr_hwdiagctrl,
2457 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2458
2459 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2460 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2461 if (ppd->cpspec->ibdeltainprog)
2462 val -= val - ppd->cpspec->ibsymsnap;
2463 val -= ppd->cpspec->ibsymdelta;
2464 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2465 }
2466 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2467 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2468 if (ppd->cpspec->ibdeltainprog)
2469 val -= val - ppd->cpspec->iblnkerrsnap;
2470 val -= ppd->cpspec->iblnkerrdelta;
2471 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2472 }
2473 if (ppd->cpspec->iblnkdowndelta) {
2474 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2475 val += ppd->cpspec->iblnkdowndelta;
2476 write_7322_creg_port(ppd, crp_iblinkdown, val);
2477 }
2478
2479
2480
2481
2482
2483
2484 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2485 }
2486}
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2511{
2512 struct qib_devdata *dd = ppd->dd;
2513 u64 extctl, ledblink = 0, val;
2514 unsigned long flags;
2515 int yel, grn;
2516
2517
2518
2519
2520
2521 if (dd->diag_client)
2522 return;
2523
2524
2525 if (ppd->led_override) {
2526 grn = (ppd->led_override & QIB_LED_PHYS);
2527 yel = (ppd->led_override & QIB_LED_LOG);
2528 } else if (on) {
2529 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2530 grn = qib_7322_phys_portstate(val) ==
2531 IB_PHYSPORTSTATE_LINKUP;
2532 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2533 } else {
2534 grn = 0;
2535 yel = 0;
2536 }
2537
2538 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2539 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2540 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2541 if (grn) {
2542 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2543
2544
2545
2546
2547
2548 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2549 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2550 }
2551 if (yel)
2552 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2553 dd->cspec->extctrl = extctl;
2554 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2555 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2556
2557 if (ledblink)
2558 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2559}
2560
2561
2562
2563
2564
2565
2566static void qib_7322_nomsix(struct qib_devdata *dd)
2567{
2568 u64 intgranted;
2569 int n;
2570
2571 dd->cspec->main_int_mask = ~0ULL;
2572 n = dd->cspec->num_msix_entries;
2573 if (n) {
2574 int i;
2575
2576 dd->cspec->num_msix_entries = 0;
2577 for (i = 0; i < n; i++) {
2578 irq_set_affinity_hint(
2579 dd->cspec->msix_entries[i].msix.vector, NULL);
2580 free_cpumask_var(dd->cspec->msix_entries[i].mask);
2581 free_irq(dd->cspec->msix_entries[i].msix.vector,
2582 dd->cspec->msix_entries[i].arg);
2583 }
2584 qib_nomsix(dd);
2585 }
2586
2587 intgranted = qib_read_kreg64(dd, kr_intgranted);
2588 if (intgranted)
2589 qib_write_kreg(dd, kr_intgranted, intgranted);
2590}
2591
2592static void qib_7322_free_irq(struct qib_devdata *dd)
2593{
2594 if (dd->cspec->irq) {
2595 free_irq(dd->cspec->irq, dd);
2596 dd->cspec->irq = 0;
2597 }
2598 qib_7322_nomsix(dd);
2599}
2600
2601static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2602{
2603 int i;
2604
2605 qib_7322_free_irq(dd);
2606 kfree(dd->cspec->cntrs);
2607 kfree(dd->cspec->sendchkenable);
2608 kfree(dd->cspec->sendgrhchk);
2609 kfree(dd->cspec->sendibchk);
2610 kfree(dd->cspec->msix_entries);
2611 for (i = 0; i < dd->num_pports; i++) {
2612 unsigned long flags;
2613 u32 mask = QSFP_GPIO_MOD_PRS_N |
2614 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2615
2616 kfree(dd->pport[i].cpspec->portcntrs);
2617 if (dd->flags & QIB_HAS_QSFP) {
2618 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2619 dd->cspec->gpio_mask &= ~mask;
2620 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2621 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2622 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data);
2623 }
2624 if (dd->pport[i].ibport_data.smi_ah)
2625 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah);
2626 }
2627}
2628
2629
2630static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2631{
2632 struct qib_pportdata *ppd0 = &dd->pport[0];
2633 struct qib_pportdata *ppd1 = &dd->pport[1];
2634 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2635 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2636 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2637 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2638
2639 if (intr0)
2640 qib_sdma_intr(ppd0);
2641 if (intr1)
2642 qib_sdma_intr(ppd1);
2643
2644 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2645 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2646 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2647 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2648}
2649
2650
2651
2652
2653static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2654{
2655 unsigned long flags;
2656
2657 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2658 if (needint)
2659 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2660 else
2661 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2662 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2663 qib_write_kreg(dd, kr_scratch, 0ULL);
2664 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2665}
2666
2667
2668
2669
2670
2671
2672static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2673{
2674 u64 kills;
2675 char msg[128];
2676
2677 kills = istat & ~QIB_I_BITSEXTANT;
2678 qib_dev_err(dd,
2679 "Clearing reserved interrupt(s) 0x%016llx: %s\n",
2680 (unsigned long long) kills, msg);
2681 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2682}
2683
2684
2685static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2686{
2687 u32 gpiostatus;
2688 int handled = 0;
2689 int pidx;
2690
2691
2692
2693
2694
2695
2696
2697
2698 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2699
2700
2701
2702
2703
2704
2705
2706 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2707
2708
2709
2710
2711 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2712 ++pidx) {
2713 struct qib_pportdata *ppd;
2714 struct qib_qsfp_data *qd;
2715 u32 mask;
2716 if (!dd->pport[pidx].link_speed_supported)
2717 continue;
2718 mask = QSFP_GPIO_MOD_PRS_N;
2719 ppd = dd->pport + pidx;
2720 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2721 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2722 u64 pins;
2723 qd = &ppd->cpspec->qsfp_data;
2724 gpiostatus &= ~mask;
2725 pins = qib_read_kreg64(dd, kr_extstatus);
2726 pins >>= SYM_LSB(EXTStatus, GPIOIn);
2727 if (!(pins & mask)) {
2728 ++handled;
2729 qd->t_insert = jiffies;
2730 queue_work(ib_wq, &qd->work);
2731 }
2732 }
2733 }
2734
2735 if (gpiostatus && !handled) {
2736 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
2737 u32 gpio_irq = mask & gpiostatus;
2738
2739
2740
2741
2742 dd->cspec->gpio_mask &= ~gpio_irq;
2743 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2744 }
2745}
2746
2747
2748
2749
2750
2751static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
2752{
2753 if (istat & ~QIB_I_BITSEXTANT)
2754 unknown_7322_ibits(dd, istat);
2755 if (istat & QIB_I_GPIO)
2756 unknown_7322_gpio_intr(dd);
2757 if (istat & QIB_I_C_ERROR) {
2758 qib_write_kreg(dd, kr_errmask, 0ULL);
2759 tasklet_schedule(&dd->error_tasklet);
2760 }
2761 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
2762 handle_7322_p_errors(dd->rcd[0]->ppd);
2763 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
2764 handle_7322_p_errors(dd->rcd[1]->ppd);
2765}
2766
2767
2768
2769
2770
2771static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
2772{
2773 struct qib_devdata *dd = rcd->dd;
2774 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
2775
2776
2777
2778
2779
2780 if (npkts < rcv_int_count && timeout > 2)
2781 timeout >>= 1;
2782 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
2783 timeout = min(timeout << 1, rcv_int_timeout);
2784 else
2785 return;
2786
2787 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
2788 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
2789}
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799static irqreturn_t qib_7322intr(int irq, void *data)
2800{
2801 struct qib_devdata *dd = data;
2802 irqreturn_t ret;
2803 u64 istat;
2804 u64 ctxtrbits;
2805 u64 rmask;
2806 unsigned i;
2807 u32 npkts;
2808
2809 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
2810
2811
2812
2813
2814
2815
2816 ret = IRQ_HANDLED;
2817 goto bail;
2818 }
2819
2820 istat = qib_read_kreg64(dd, kr_intstatus);
2821
2822 if (unlikely(istat == ~0ULL)) {
2823 qib_bad_intrstatus(dd);
2824 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
2825
2826 ret = IRQ_NONE;
2827 goto bail;
2828 }
2829
2830 istat &= dd->cspec->main_int_mask;
2831 if (unlikely(!istat)) {
2832
2833 ret = IRQ_NONE;
2834 goto bail;
2835 }
2836
2837 qib_stats.sps_ints++;
2838 if (dd->int_counter != (u32) -1)
2839 dd->int_counter++;
2840
2841
2842 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
2843 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
2844 INT_MASK_P(Err, 1))))
2845 unlikely_7322_intr(dd, istat);
2846
2847
2848
2849
2850
2851
2852
2853 qib_write_kreg(dd, kr_intclear, istat);
2854
2855
2856
2857
2858
2859
2860 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
2861 if (ctxtrbits) {
2862 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
2863 (1ULL << QIB_I_RCVURG_LSB);
2864 for (i = 0; i < dd->first_user_ctxt; i++) {
2865 if (ctxtrbits & rmask) {
2866 ctxtrbits &= ~rmask;
2867 if (dd->rcd[i])
2868 qib_kreceive(dd->rcd[i], NULL, &npkts);
2869 }
2870 rmask <<= 1;
2871 }
2872 if (ctxtrbits) {
2873 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
2874 (ctxtrbits >> QIB_I_RCVURG_LSB);
2875 qib_handle_urcv(dd, ctxtrbits);
2876 }
2877 }
2878
2879 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
2880 sdma_7322_intr(dd, istat);
2881
2882 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2883 qib_ib_piobufavail(dd);
2884
2885 ret = IRQ_HANDLED;
2886bail:
2887 return ret;
2888}
2889
2890
2891
2892
2893static irqreturn_t qib_7322pintr(int irq, void *data)
2894{
2895 struct qib_ctxtdata *rcd = data;
2896 struct qib_devdata *dd = rcd->dd;
2897 u32 npkts;
2898
2899 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2900
2901
2902
2903
2904
2905
2906 return IRQ_HANDLED;
2907
2908 qib_stats.sps_ints++;
2909 if (dd->int_counter != (u32) -1)
2910 dd->int_counter++;
2911
2912
2913 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
2914 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
2915
2916 qib_kreceive(rcd, NULL, &npkts);
2917
2918 return IRQ_HANDLED;
2919}
2920
2921
2922
2923
2924static irqreturn_t qib_7322bufavail(int irq, void *data)
2925{
2926 struct qib_devdata *dd = data;
2927
2928 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2929
2930
2931
2932
2933
2934
2935 return IRQ_HANDLED;
2936
2937 qib_stats.sps_ints++;
2938 if (dd->int_counter != (u32) -1)
2939 dd->int_counter++;
2940
2941
2942 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
2943
2944
2945 if (dd->flags & QIB_INITTED)
2946 qib_ib_piobufavail(dd);
2947 else
2948 qib_wantpiobuf_7322_intr(dd, 0);
2949
2950 return IRQ_HANDLED;
2951}
2952
2953
2954
2955
2956static irqreturn_t sdma_intr(int irq, void *data)
2957{
2958 struct qib_pportdata *ppd = data;
2959 struct qib_devdata *dd = ppd->dd;
2960
2961 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2962
2963
2964
2965
2966
2967
2968 return IRQ_HANDLED;
2969
2970 qib_stats.sps_ints++;
2971 if (dd->int_counter != (u32) -1)
2972 dd->int_counter++;
2973
2974
2975 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2976 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
2977 qib_sdma_intr(ppd);
2978
2979 return IRQ_HANDLED;
2980}
2981
2982
2983
2984
2985static irqreturn_t sdma_idle_intr(int irq, void *data)
2986{
2987 struct qib_pportdata *ppd = data;
2988 struct qib_devdata *dd = ppd->dd;
2989
2990 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2991
2992
2993
2994
2995
2996
2997 return IRQ_HANDLED;
2998
2999 qib_stats.sps_ints++;
3000 if (dd->int_counter != (u32) -1)
3001 dd->int_counter++;
3002
3003
3004 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3005 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
3006 qib_sdma_intr(ppd);
3007
3008 return IRQ_HANDLED;
3009}
3010
3011
3012
3013
3014static irqreturn_t sdma_progress_intr(int irq, void *data)
3015{
3016 struct qib_pportdata *ppd = data;
3017 struct qib_devdata *dd = ppd->dd;
3018
3019 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3020
3021
3022
3023
3024
3025
3026 return IRQ_HANDLED;
3027
3028 qib_stats.sps_ints++;
3029 if (dd->int_counter != (u32) -1)
3030 dd->int_counter++;
3031
3032
3033 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3034 INT_MASK_P(SDmaProgress, 1) :
3035 INT_MASK_P(SDmaProgress, 0));
3036 qib_sdma_intr(ppd);
3037
3038 return IRQ_HANDLED;
3039}
3040
3041
3042
3043
3044static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3045{
3046 struct qib_pportdata *ppd = data;
3047 struct qib_devdata *dd = ppd->dd;
3048
3049 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3050
3051
3052
3053
3054
3055
3056 return IRQ_HANDLED;
3057
3058 qib_stats.sps_ints++;
3059 if (dd->int_counter != (u32) -1)
3060 dd->int_counter++;
3061
3062
3063 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3064 INT_MASK_PM(SDmaCleanupDone, 1) :
3065 INT_MASK_PM(SDmaCleanupDone, 0));
3066 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3067
3068 return IRQ_HANDLED;
3069}
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3080{
3081 int ret, i, msixnum;
3082 u64 redirect[6];
3083 u64 mask;
3084 const struct cpumask *local_mask;
3085 int firstcpu, secondcpu = 0, currrcvcpu = 0;
3086
3087 if (!dd->num_pports)
3088 return;
3089
3090 if (clearpend) {
3091
3092
3093
3094
3095
3096 qib_7322_set_intr_state(dd, 0);
3097
3098
3099 qib_7322_init_hwerrors(dd);
3100
3101
3102 qib_write_kreg(dd, kr_intclear, ~0ULL);
3103
3104
3105 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3106 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3107 }
3108
3109 if (!dd->cspec->num_msix_entries) {
3110
3111try_intx:
3112 if (!dd->pcidev->irq) {
3113 qib_dev_err(dd,
3114 "irq is 0, BIOS error? Interrupts won't work\n");
3115 goto bail;
3116 }
3117 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3118 IRQF_SHARED, QIB_DRV_NAME, dd);
3119 if (ret) {
3120 qib_dev_err(dd,
3121 "Couldn't setup INTx interrupt (irq=%d): %d\n",
3122 dd->pcidev->irq, ret);
3123 goto bail;
3124 }
3125 dd->cspec->irq = dd->pcidev->irq;
3126 dd->cspec->main_int_mask = ~0ULL;
3127 goto bail;
3128 }
3129
3130
3131 memset(redirect, 0, sizeof redirect);
3132 mask = ~0ULL;
3133 msixnum = 0;
3134 local_mask = cpumask_of_pcibus(dd->pcidev->bus);
3135 firstcpu = cpumask_first(local_mask);
3136 if (firstcpu >= nr_cpu_ids ||
3137 cpumask_weight(local_mask) == num_online_cpus()) {
3138 local_mask = topology_core_cpumask(0);
3139 firstcpu = cpumask_first(local_mask);
3140 }
3141 if (firstcpu < nr_cpu_ids) {
3142 secondcpu = cpumask_next(firstcpu, local_mask);
3143 if (secondcpu >= nr_cpu_ids)
3144 secondcpu = firstcpu;
3145 currrcvcpu = secondcpu;
3146 }
3147 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3148 irq_handler_t handler;
3149 void *arg;
3150 u64 val;
3151 int lsb, reg, sh;
3152
3153 dd->cspec->msix_entries[msixnum].
3154 name[sizeof(dd->cspec->msix_entries[msixnum].name) - 1]
3155 = '\0';
3156 if (i < ARRAY_SIZE(irq_table)) {
3157 if (irq_table[i].port) {
3158
3159 if (irq_table[i].port > dd->num_pports)
3160 continue;
3161 arg = dd->pport + irq_table[i].port - 1;
3162 } else
3163 arg = dd;
3164 lsb = irq_table[i].lsb;
3165 handler = irq_table[i].handler;
3166 snprintf(dd->cspec->msix_entries[msixnum].name,
3167 sizeof(dd->cspec->msix_entries[msixnum].name)
3168 - 1,
3169 QIB_DRV_NAME "%d%s", dd->unit,
3170 irq_table[i].name);
3171 } else {
3172 unsigned ctxt;
3173
3174 ctxt = i - ARRAY_SIZE(irq_table);
3175
3176 arg = dd->rcd[ctxt];
3177 if (!arg)
3178 continue;
3179 if (qib_krcvq01_no_msi && ctxt < 2)
3180 continue;
3181 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3182 handler = qib_7322pintr;
3183 snprintf(dd->cspec->msix_entries[msixnum].name,
3184 sizeof(dd->cspec->msix_entries[msixnum].name)
3185 - 1,
3186 QIB_DRV_NAME "%d (kctx)", dd->unit);
3187 }
3188 ret = request_irq(
3189 dd->cspec->msix_entries[msixnum].msix.vector,
3190 handler, 0, dd->cspec->msix_entries[msixnum].name,
3191 arg);
3192 if (ret) {
3193
3194
3195
3196
3197 qib_dev_err(dd,
3198 "Couldn't setup MSIx interrupt (vec=%d, irq=%d): %d\n",
3199 msixnum,
3200 dd->cspec->msix_entries[msixnum].msix.vector,
3201 ret);
3202 qib_7322_nomsix(dd);
3203 goto try_intx;
3204 }
3205 dd->cspec->msix_entries[msixnum].arg = arg;
3206 if (lsb >= 0) {
3207 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3208 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3209 SYM_LSB(IntRedirect0, vec1);
3210 mask &= ~(1ULL << lsb);
3211 redirect[reg] |= ((u64) msixnum) << sh;
3212 }
3213 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3214 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3215 if (firstcpu < nr_cpu_ids &&
3216 zalloc_cpumask_var(
3217 &dd->cspec->msix_entries[msixnum].mask,
3218 GFP_KERNEL)) {
3219 if (handler == qib_7322pintr) {
3220 cpumask_set_cpu(currrcvcpu,
3221 dd->cspec->msix_entries[msixnum].mask);
3222 currrcvcpu = cpumask_next(currrcvcpu,
3223 local_mask);
3224 if (currrcvcpu >= nr_cpu_ids)
3225 currrcvcpu = secondcpu;
3226 } else {
3227 cpumask_set_cpu(firstcpu,
3228 dd->cspec->msix_entries[msixnum].mask);
3229 }
3230 irq_set_affinity_hint(
3231 dd->cspec->msix_entries[msixnum].msix.vector,
3232 dd->cspec->msix_entries[msixnum].mask);
3233 }
3234 msixnum++;
3235 }
3236
3237 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3238 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3239 dd->cspec->main_int_mask = mask;
3240 tasklet_init(&dd->error_tasklet, qib_error_tasklet,
3241 (unsigned long)dd);
3242bail:;
3243}
3244
3245
3246
3247
3248
3249
3250
3251static unsigned qib_7322_boardname(struct qib_devdata *dd)
3252{
3253
3254 char *n;
3255 u32 boardid, namelen;
3256 unsigned features = DUAL_PORT_CAP;
3257
3258 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3259
3260 switch (boardid) {
3261 case 0:
3262 n = "InfiniPath_QLE7342_Emulation";
3263 break;
3264 case 1:
3265 n = "InfiniPath_QLE7340";
3266 dd->flags |= QIB_HAS_QSFP;
3267 features = PORT_SPD_CAP;
3268 break;
3269 case 2:
3270 n = "InfiniPath_QLE7342";
3271 dd->flags |= QIB_HAS_QSFP;
3272 break;
3273 case 3:
3274 n = "InfiniPath_QMI7342";
3275 break;
3276 case 4:
3277 n = "InfiniPath_Unsupported7342";
3278 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3279 features = 0;
3280 break;
3281 case BOARD_QMH7342:
3282 n = "InfiniPath_QMH7342";
3283 features = 0x24;
3284 break;
3285 case BOARD_QME7342:
3286 n = "InfiniPath_QME7342";
3287 break;
3288 case 8:
3289 n = "InfiniPath_QME7362";
3290 dd->flags |= QIB_HAS_QSFP;
3291 break;
3292 case 15:
3293 n = "InfiniPath_QLE7342_TEST";
3294 dd->flags |= QIB_HAS_QSFP;
3295 break;
3296 default:
3297 n = "InfiniPath_QLE73xy_UNKNOWN";
3298 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3299 break;
3300 }
3301 dd->board_atten = 1;
3302
3303 namelen = strlen(n) + 1;
3304 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3305 if (!dd->boardname)
3306 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3307 else
3308 snprintf(dd->boardname, namelen, "%s", n);
3309
3310 snprintf(dd->boardversion, sizeof(dd->boardversion),
3311 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3312 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3313 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
3314 dd->majrev, dd->minrev,
3315 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
3316
3317 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
3318 qib_devinfo(dd->pcidev,
3319 "IB%u: Forced to single port mode by module parameter\n",
3320 dd->unit);
3321 features &= PORT_SPD_CAP;
3322 }
3323
3324 return features;
3325}
3326
3327
3328
3329
3330
3331static int qib_do_7322_reset(struct qib_devdata *dd)
3332{
3333 u64 val;
3334 u64 *msix_vecsave;
3335 int i, msix_entries, ret = 1;
3336 u16 cmdval;
3337 u8 int_line, clinesz;
3338 unsigned long flags;
3339
3340
3341 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3342
3343 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3344
3345 msix_entries = dd->cspec->num_msix_entries;
3346
3347
3348 qib_7322_set_intr_state(dd, 0);
3349
3350 if (msix_entries) {
3351 qib_7322_nomsix(dd);
3352
3353 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3354 sizeof(u64), GFP_KERNEL);
3355 if (!msix_vecsave)
3356 qib_dev_err(dd, "No mem to save MSIx data\n");
3357 } else
3358 msix_vecsave = NULL;
3359
3360
3361
3362
3363
3364
3365
3366
3367 for (i = 0; i < msix_entries; i++) {
3368 u64 vecaddr, vecdata;
3369 vecaddr = qib_read_kreg64(dd, 2 * i +
3370 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3371 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3372 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3373 if (msix_vecsave) {
3374 msix_vecsave[2 * i] = vecaddr;
3375
3376 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3377 }
3378 }
3379
3380 dd->pport->cpspec->ibdeltainprog = 0;
3381 dd->pport->cpspec->ibsymdelta = 0;
3382 dd->pport->cpspec->iblnkerrdelta = 0;
3383 dd->pport->cpspec->ibmalfdelta = 0;
3384 dd->int_counter = 0;
3385
3386
3387
3388
3389
3390
3391 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3392 dd->flags |= QIB_DOING_RESET;
3393 val = dd->control | QLOGIC_IB_C_RESET;
3394 writeq(val, &dd->kregbase[kr_control]);
3395
3396 for (i = 1; i <= 5; i++) {
3397
3398
3399
3400
3401
3402 msleep(1000 + (1 + i) * 3000);
3403
3404 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3405
3406
3407
3408
3409
3410 val = readq(&dd->kregbase[kr_revision]);
3411 if (val == dd->revision)
3412 break;
3413 if (i == 5) {
3414 qib_dev_err(dd,
3415 "Failed to initialize after reset, unusable\n");
3416 ret = 0;
3417 goto bail;
3418 }
3419 }
3420
3421 dd->flags |= QIB_PRESENT;
3422
3423 if (msix_entries) {
3424
3425 for (i = 0; i < msix_entries; i++) {
3426 dd->cspec->msix_entries[i].msix.entry = i;
3427 if (!msix_vecsave || !msix_vecsave[2 * i])
3428 continue;
3429 qib_write_kreg(dd, 2 * i +
3430 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3431 msix_vecsave[2 * i]);
3432 qib_write_kreg(dd, 1 + 2 * i +
3433 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3434 msix_vecsave[1 + 2 * i]);
3435 }
3436 }
3437
3438
3439 for (i = 0; i < dd->num_pports; ++i)
3440 write_7322_init_portregs(&dd->pport[i]);
3441 write_7322_initregs(dd);
3442
3443 if (qib_pcie_params(dd, dd->lbus_width,
3444 &dd->cspec->num_msix_entries,
3445 dd->cspec->msix_entries))
3446 qib_dev_err(dd,
3447 "Reset failed to setup PCIe or interrupts; continuing anyway\n");
3448
3449 qib_setup_7322_interrupt(dd, 1);
3450
3451 for (i = 0; i < dd->num_pports; ++i) {
3452 struct qib_pportdata *ppd = &dd->pport[i];
3453
3454 spin_lock_irqsave(&ppd->lflags_lock, flags);
3455 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3456 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3457 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3458 }
3459
3460bail:
3461 dd->flags &= ~QIB_DOING_RESET;
3462 kfree(msix_vecsave);
3463 return ret;
3464}
3465
3466
3467
3468
3469
3470
3471
3472
3473static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3474 u32 type, unsigned long pa)
3475{
3476 if (!(dd->flags & QIB_PRESENT))
3477 return;
3478 if (pa != dd->tidinvalid) {
3479 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3480
3481
3482 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3483 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3484 pa);
3485 return;
3486 }
3487 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
3488 qib_dev_err(dd,
3489 "Physical page address 0x%lx larger than supported\n",
3490 pa);
3491 return;
3492 }
3493
3494 if (type == RCVHQ_RCV_TYPE_EAGER)
3495 chippa |= dd->tidtemplate;
3496 else
3497 chippa |= IBA7322_TID_SZ_4K;
3498 pa = chippa;
3499 }
3500 writeq(pa, tidptr);
3501 mmiowb();
3502}
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512static void qib_7322_clear_tids(struct qib_devdata *dd,
3513 struct qib_ctxtdata *rcd)
3514{
3515 u64 __iomem *tidbase;
3516 unsigned long tidinv;
3517 u32 ctxt;
3518 int i;
3519
3520 if (!dd->kregbase || !rcd)
3521 return;
3522
3523 ctxt = rcd->ctxt;
3524
3525 tidinv = dd->tidinvalid;
3526 tidbase = (u64 __iomem *)
3527 ((char __iomem *) dd->kregbase +
3528 dd->rcvtidbase +
3529 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3530
3531 for (i = 0; i < dd->rcvtidcnt; i++)
3532 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3533 tidinv);
3534
3535 tidbase = (u64 __iomem *)
3536 ((char __iomem *) dd->kregbase +
3537 dd->rcvegrbase +
3538 rcd->rcvegr_tid_base * sizeof(*tidbase));
3539
3540 for (i = 0; i < rcd->rcvegrcnt; i++)
3541 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3542 tidinv);
3543}
3544
3545
3546
3547
3548
3549
3550
3551static void qib_7322_tidtemplate(struct qib_devdata *dd)
3552{
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562 if (dd->rcvegrbufsize == 2048)
3563 dd->tidtemplate = IBA7322_TID_SZ_2K;
3564 else if (dd->rcvegrbufsize == 4096)
3565 dd->tidtemplate = IBA7322_TID_SZ_4K;
3566 dd->tidinvalid = 0;
3567}
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3579 struct qib_base_info *kinfo)
3580{
3581 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3582 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3583 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3584 if (rcd->dd->cspec->r1)
3585 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3586 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3587 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3588
3589 return 0;
3590}
3591
3592static struct qib_message_header *
3593qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3594{
3595 u32 offset = qib_hdrget_offset(rhf_addr);
3596
3597 return (struct qib_message_header *)
3598 (rhf_addr - dd->rhf_offset + offset);
3599}
3600
3601
3602
3603
3604static void qib_7322_config_ctxts(struct qib_devdata *dd)
3605{
3606 unsigned long flags;
3607 u32 nchipctxts;
3608
3609 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3610 dd->cspec->numctxts = nchipctxts;
3611 if (qib_n_krcv_queues > 1 && dd->num_pports) {
3612 dd->first_user_ctxt = NUM_IB_PORTS +
3613 (qib_n_krcv_queues - 1) * dd->num_pports;
3614 if (dd->first_user_ctxt > nchipctxts)
3615 dd->first_user_ctxt = nchipctxts;
3616 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3617 } else {
3618 dd->first_user_ctxt = NUM_IB_PORTS;
3619 dd->n_krcv_queues = 1;
3620 }
3621
3622 if (!qib_cfgctxts) {
3623 int nctxts = dd->first_user_ctxt + num_online_cpus();
3624
3625 if (nctxts <= 6)
3626 dd->ctxtcnt = 6;
3627 else if (nctxts <= 10)
3628 dd->ctxtcnt = 10;
3629 else if (nctxts <= nchipctxts)
3630 dd->ctxtcnt = nchipctxts;
3631 } else if (qib_cfgctxts < dd->num_pports)
3632 dd->ctxtcnt = dd->num_pports;
3633 else if (qib_cfgctxts <= nchipctxts)
3634 dd->ctxtcnt = qib_cfgctxts;
3635 if (!dd->ctxtcnt)
3636 dd->ctxtcnt = nchipctxts;
3637
3638
3639
3640
3641
3642
3643 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3644 if (dd->ctxtcnt > 10)
3645 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3646 else if (dd->ctxtcnt > 6)
3647 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3648
3649
3650
3651 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3652
3653
3654
3655
3656
3657 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
3658 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3659
3660
3661 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3662 if (qib_rcvhdrcnt)
3663 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
3664 else
3665 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt,
3666 dd->num_pports > 1 ? 1024U : 2048U);
3667}
3668
3669static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
3670{
3671
3672 int lsb, ret = 0;
3673 u64 maskr;
3674
3675 switch (which) {
3676
3677 case QIB_IB_CFG_LWID_ENB:
3678 ret = ppd->link_width_enabled;
3679 goto done;
3680
3681 case QIB_IB_CFG_LWID:
3682 ret = ppd->link_width_active;
3683 goto done;
3684
3685 case QIB_IB_CFG_SPD_ENB:
3686 ret = ppd->link_speed_enabled;
3687 goto done;
3688
3689 case QIB_IB_CFG_SPD:
3690 ret = ppd->link_speed_active;
3691 goto done;
3692
3693 case QIB_IB_CFG_RXPOL_ENB:
3694 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3695 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3696 break;
3697
3698 case QIB_IB_CFG_LREV_ENB:
3699 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3700 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3701 break;
3702
3703 case QIB_IB_CFG_LINKLATENCY:
3704 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
3705 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
3706 goto done;
3707
3708 case QIB_IB_CFG_OP_VLS:
3709 ret = ppd->vls_operational;
3710 goto done;
3711
3712 case QIB_IB_CFG_VL_HIGH_CAP:
3713 ret = 16;
3714 goto done;
3715
3716 case QIB_IB_CFG_VL_LOW_CAP:
3717 ret = 16;
3718 goto done;
3719
3720 case QIB_IB_CFG_OVERRUN_THRESH:
3721 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3722 OverrunThreshold);
3723 goto done;
3724
3725 case QIB_IB_CFG_PHYERR_THRESH:
3726 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3727 PhyerrThreshold);
3728 goto done;
3729
3730 case QIB_IB_CFG_LINKDEFAULT:
3731
3732 ret = (ppd->cpspec->ibcctrl_a &
3733 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
3734 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
3735 goto done;
3736
3737 case QIB_IB_CFG_HRTBT:
3738 lsb = IBA7322_IBC_HRTBT_LSB;
3739 maskr = IBA7322_IBC_HRTBT_RMASK;
3740 break;
3741
3742 case QIB_IB_CFG_PMA_TICKS:
3743
3744
3745
3746
3747 if (ppd->link_speed_active == QIB_IB_QDR)
3748 ret = 3;
3749 else if (ppd->link_speed_active == QIB_IB_DDR)
3750 ret = 1;
3751 else
3752 ret = 0;
3753 goto done;
3754
3755 default:
3756 ret = -EINVAL;
3757 goto done;
3758 }
3759 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
3760done:
3761 return ret;
3762}
3763
3764
3765
3766
3767
3768#define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
3769#define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
3770 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
3771
3772static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
3773{
3774 struct qib_devdata *dd = ppd->dd;
3775 u64 maskr;
3776 int lsb, ret = 0;
3777 u16 lcmd, licmd;
3778 unsigned long flags;
3779
3780 switch (which) {
3781 case QIB_IB_CFG_LIDLMC:
3782
3783
3784
3785
3786 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
3787 maskr = IBA7322_IBC_DLIDLMC_MASK;
3788
3789
3790
3791
3792
3793
3794
3795 qib_write_kreg_port(ppd, krp_sendslid,
3796 val & (val >> 16) & SendIBSLIDAssignMask);
3797 qib_write_kreg_port(ppd, krp_sendslidmask,
3798 (val >> 16) & SendIBSLMCMask);
3799 break;
3800
3801 case QIB_IB_CFG_LWID_ENB:
3802 ppd->link_width_enabled = val;
3803
3804 if (val == IB_WIDTH_1X)
3805 val = 0;
3806 else if (val == IB_WIDTH_4X)
3807 val = 1;
3808 else
3809 val = 3;
3810 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
3811 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
3812 break;
3813
3814 case QIB_IB_CFG_SPD_ENB:
3815
3816
3817
3818
3819
3820
3821
3822 ppd->link_speed_enabled = val;
3823 val <<= IBA7322_IBC_SPEED_LSB;
3824 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
3825 IBA7322_IBC_MAX_SPEED_MASK;
3826 if (val & (val - 1)) {
3827
3828 val |= IBA7322_IBC_IBTA_1_2_MASK |
3829 IBA7322_IBC_MAX_SPEED_MASK;
3830 spin_lock_irqsave(&ppd->lflags_lock, flags);
3831 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3832 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3833 } else if (val & IBA7322_IBC_SPEED_QDR)
3834 val |= IBA7322_IBC_IBTA_1_2_MASK;
3835
3836 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
3837 break;
3838
3839 case QIB_IB_CFG_RXPOL_ENB:
3840 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3841 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3842 break;
3843
3844 case QIB_IB_CFG_LREV_ENB:
3845 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3846 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3847 break;
3848
3849 case QIB_IB_CFG_OVERRUN_THRESH:
3850 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3851 OverrunThreshold);
3852 if (maskr != val) {
3853 ppd->cpspec->ibcctrl_a &=
3854 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
3855 ppd->cpspec->ibcctrl_a |= (u64) val <<
3856 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
3857 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3858 ppd->cpspec->ibcctrl_a);
3859 qib_write_kreg(dd, kr_scratch, 0ULL);
3860 }
3861 goto bail;
3862
3863 case QIB_IB_CFG_PHYERR_THRESH:
3864 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3865 PhyerrThreshold);
3866 if (maskr != val) {
3867 ppd->cpspec->ibcctrl_a &=
3868 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
3869 ppd->cpspec->ibcctrl_a |= (u64) val <<
3870 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
3871 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3872 ppd->cpspec->ibcctrl_a);
3873 qib_write_kreg(dd, kr_scratch, 0ULL);
3874 }
3875 goto bail;
3876
3877 case QIB_IB_CFG_PKEYS:
3878 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
3879 ((u64) ppd->pkeys[2] << 32) |
3880 ((u64) ppd->pkeys[3] << 48);
3881 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
3882 goto bail;
3883
3884 case QIB_IB_CFG_LINKDEFAULT:
3885
3886 if (val == IB_LINKINITCMD_POLL)
3887 ppd->cpspec->ibcctrl_a &=
3888 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3889 else
3890 ppd->cpspec->ibcctrl_a |=
3891 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3892 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
3893 qib_write_kreg(dd, kr_scratch, 0ULL);
3894 goto bail;
3895
3896 case QIB_IB_CFG_MTU:
3897
3898
3899
3900
3901
3902
3903
3904 val = (ppd->ibmaxlen >> 2) + 1;
3905 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
3906 ppd->cpspec->ibcctrl_a |= (u64)val <<
3907 SYM_LSB(IBCCtrlA_0, MaxPktLen);
3908 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3909 ppd->cpspec->ibcctrl_a);
3910 qib_write_kreg(dd, kr_scratch, 0ULL);
3911 goto bail;
3912
3913 case QIB_IB_CFG_LSTATE:
3914 switch (val & 0xffff0000) {
3915 case IB_LINKCMD_DOWN:
3916 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
3917 ppd->cpspec->ibmalfusesnap = 1;
3918 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
3919 crp_errlink);
3920 if (!ppd->cpspec->ibdeltainprog &&
3921 qib_compat_ddr_negotiate) {
3922 ppd->cpspec->ibdeltainprog = 1;
3923 ppd->cpspec->ibsymsnap =
3924 read_7322_creg32_port(ppd,
3925 crp_ibsymbolerr);
3926 ppd->cpspec->iblnkerrsnap =
3927 read_7322_creg32_port(ppd,
3928 crp_iblinkerrrecov);
3929 }
3930 break;
3931
3932 case IB_LINKCMD_ARMED:
3933 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
3934 if (ppd->cpspec->ibmalfusesnap) {
3935 ppd->cpspec->ibmalfusesnap = 0;
3936 ppd->cpspec->ibmalfdelta +=
3937 read_7322_creg32_port(ppd,
3938 crp_errlink) -
3939 ppd->cpspec->ibmalfsnap;
3940 }
3941 break;
3942
3943 case IB_LINKCMD_ACTIVE:
3944 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
3945 break;
3946
3947 default:
3948 ret = -EINVAL;
3949 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
3950 goto bail;
3951 }
3952 switch (val & 0xffff) {
3953 case IB_LINKINITCMD_NOP:
3954 licmd = 0;
3955 break;
3956
3957 case IB_LINKINITCMD_POLL:
3958 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
3959 break;
3960
3961 case IB_LINKINITCMD_SLEEP:
3962 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
3963 break;
3964
3965 case IB_LINKINITCMD_DISABLE:
3966 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
3967 ppd->cpspec->chase_end = 0;
3968
3969
3970
3971
3972 if (ppd->cpspec->chase_timer.expires) {
3973 del_timer_sync(&ppd->cpspec->chase_timer);
3974 ppd->cpspec->chase_timer.expires = 0;
3975 }
3976 break;
3977
3978 default:
3979 ret = -EINVAL;
3980 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
3981 val & 0xffff);
3982 goto bail;
3983 }
3984 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
3985 goto bail;
3986
3987 case QIB_IB_CFG_OP_VLS:
3988 if (ppd->vls_operational != val) {
3989 ppd->vls_operational = val;
3990 set_vls(ppd);
3991 }
3992 goto bail;
3993
3994 case QIB_IB_CFG_VL_HIGH_LIMIT:
3995 qib_write_kreg_port(ppd, krp_highprio_limit, val);
3996 goto bail;
3997
3998 case QIB_IB_CFG_HRTBT:
3999 if (val > 3) {
4000 ret = -EINVAL;
4001 goto bail;
4002 }
4003 lsb = IBA7322_IBC_HRTBT_LSB;
4004 maskr = IBA7322_IBC_HRTBT_RMASK;
4005 break;
4006
4007 case QIB_IB_CFG_PORT:
4008
4009 if (ppd->dd->cspec->r1) {
4010 cancel_delayed_work(&ppd->cpspec->ipg_work);
4011 ppd->cpspec->ipg_tries = 0;
4012 }
4013 goto bail;
4014
4015 default:
4016 ret = -EINVAL;
4017 goto bail;
4018 }
4019 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
4020 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
4021 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4022 qib_write_kreg(dd, kr_scratch, 0);
4023bail:
4024 return ret;
4025}
4026
4027static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
4028{
4029 int ret = 0;
4030 u64 val, ctrlb;
4031
4032
4033 if (!strncmp(what, "ibc", 3)) {
4034 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
4035 Loopback);
4036 val = 0;
4037 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
4038 ppd->dd->unit, ppd->port);
4039 } else if (!strncmp(what, "off", 3)) {
4040 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
4041 Loopback);
4042
4043 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
4044 qib_devinfo(ppd->dd->pcidev,
4045 "Disabling IB%u:%u IBC loopback (normal)\n",
4046 ppd->dd->unit, ppd->port);
4047 } else
4048 ret = -EINVAL;
4049 if (!ret) {
4050 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4051 ppd->cpspec->ibcctrl_a);
4052 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
4053 << IBA7322_IBC_HRTBT_LSB);
4054 ppd->cpspec->ibcctrl_b = ctrlb | val;
4055 qib_write_kreg_port(ppd, krp_ibcctrl_b,
4056 ppd->cpspec->ibcctrl_b);
4057 qib_write_kreg(ppd->dd, kr_scratch, 0);
4058 }
4059 return ret;
4060}
4061
4062static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4063 struct ib_vl_weight_elem *vl)
4064{
4065 unsigned i;
4066
4067 for (i = 0; i < 16; i++, regno++, vl++) {
4068 u32 val = qib_read_kreg_port(ppd, regno);
4069
4070 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
4071 SYM_RMASK(LowPriority0_0, VirtualLane);
4072 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
4073 SYM_RMASK(LowPriority0_0, Weight);
4074 }
4075}
4076
4077static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4078 struct ib_vl_weight_elem *vl)
4079{
4080 unsigned i;
4081
4082 for (i = 0; i < 16; i++, regno++, vl++) {
4083 u64 val;
4084
4085 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
4086 SYM_LSB(LowPriority0_0, VirtualLane)) |
4087 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
4088 SYM_LSB(LowPriority0_0, Weight));
4089 qib_write_kreg_port(ppd, regno, val);
4090 }
4091 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
4092 struct qib_devdata *dd = ppd->dd;
4093 unsigned long flags;
4094
4095 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4096 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4097 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4098 qib_write_kreg(dd, kr_scratch, 0);
4099 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4100 }
4101}
4102
4103static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
4104{
4105 switch (which) {
4106 case QIB_IB_TBL_VL_HIGH_ARB:
4107 get_vl_weights(ppd, krp_highprio_0, t);
4108 break;
4109
4110 case QIB_IB_TBL_VL_LOW_ARB:
4111 get_vl_weights(ppd, krp_lowprio_0, t);
4112 break;
4113
4114 default:
4115 return -EINVAL;
4116 }
4117 return 0;
4118}
4119
4120static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4121{
4122 switch (which) {
4123 case QIB_IB_TBL_VL_HIGH_ARB:
4124 set_vl_weights(ppd, krp_highprio_0, t);
4125 break;
4126
4127 case QIB_IB_TBL_VL_LOW_ARB:
4128 set_vl_weights(ppd, krp_lowprio_0, t);
4129 break;
4130
4131 default:
4132 return -EINVAL;
4133 }
4134 return 0;
4135}
4136
4137static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
4138 u32 updegr, u32 egrhd, u32 npkts)
4139{
4140
4141
4142
4143
4144 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT)
4145 adjust_rcv_timeout(rcd, npkts);
4146 if (updegr)
4147 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
4148 mmiowb();
4149 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4150 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4151 mmiowb();
4152}
4153
4154static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4155{
4156 u32 head, tail;
4157
4158 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4159 if (rcd->rcvhdrtail_kvaddr)
4160 tail = qib_get_rcvhdrtail(rcd);
4161 else
4162 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4163 return head == tail;
4164}
4165
4166#define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4167 QIB_RCVCTRL_CTXT_DIS | \
4168 QIB_RCVCTRL_TIDFLOW_ENB | \
4169 QIB_RCVCTRL_TIDFLOW_DIS | \
4170 QIB_RCVCTRL_TAILUPD_ENB | \
4171 QIB_RCVCTRL_TAILUPD_DIS | \
4172 QIB_RCVCTRL_INTRAVAIL_ENB | \
4173 QIB_RCVCTRL_INTRAVAIL_DIS | \
4174 QIB_RCVCTRL_BP_ENB | \
4175 QIB_RCVCTRL_BP_DIS)
4176
4177#define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4178 QIB_RCVCTRL_CTXT_DIS | \
4179 QIB_RCVCTRL_PKEY_DIS | \
4180 QIB_RCVCTRL_PKEY_ENB)
4181
4182
4183
4184
4185
4186
4187
4188
4189static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4190 int ctxt)
4191{
4192 struct qib_devdata *dd = ppd->dd;
4193 struct qib_ctxtdata *rcd;
4194 u64 mask, val;
4195 unsigned long flags;
4196
4197 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4198
4199 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4200 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4201 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4202 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4203 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4204 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4205 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4206 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4207 if (op & QIB_RCVCTRL_PKEY_ENB)
4208 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4209 if (op & QIB_RCVCTRL_PKEY_DIS)
4210 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4211 if (ctxt < 0) {
4212 mask = (1ULL << dd->ctxtcnt) - 1;
4213 rcd = NULL;
4214 } else {
4215 mask = (1ULL << ctxt);
4216 rcd = dd->rcd[ctxt];
4217 }
4218 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4219 ppd->p_rcvctrl |=
4220 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4221 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4222 op |= QIB_RCVCTRL_TAILUPD_ENB;
4223 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4224 }
4225
4226 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4227 rcd->rcvhdrqtailaddr_phys);
4228 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4229 rcd->rcvhdrq_phys);
4230 rcd->seq_cnt = 1;
4231 }
4232 if (op & QIB_RCVCTRL_CTXT_DIS)
4233 ppd->p_rcvctrl &=
4234 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4235 if (op & QIB_RCVCTRL_BP_ENB)
4236 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4237 if (op & QIB_RCVCTRL_BP_DIS)
4238 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4239 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4240 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4241 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4242 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4243
4244
4245
4246
4247
4248 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4249 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4250 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4251 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4252 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4253
4254
4255
4256
4257
4258
4259 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4260 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4261
4262
4263 (void) qib_read_kreg32(dd, kr_scratch);
4264 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4265 dd->rcd[ctxt]->head = val;
4266
4267 if (ctxt < dd->first_user_ctxt)
4268 val |= dd->rhdrhead_intr_off;
4269 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4270 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4271 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4272
4273 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4274 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4275 }
4276 if (op & QIB_RCVCTRL_CTXT_DIS) {
4277 unsigned f;
4278
4279
4280 if (ctxt >= 0) {
4281 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4282 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4283 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4284 qib_write_ureg(dd, ur_rcvflowtable + f,
4285 TIDFLOW_ERRBITS, ctxt);
4286 } else {
4287 unsigned i;
4288
4289 for (i = 0; i < dd->cfgctxts; i++) {
4290 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4291 i, 0);
4292 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4293 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4294 qib_write_ureg(dd, ur_rcvflowtable + f,
4295 TIDFLOW_ERRBITS, i);
4296 }
4297 }
4298 }
4299 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4300}
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314#define SENDCTRL_COMMON_MODS (\
4315 QIB_SENDCTRL_CLEAR | \
4316 QIB_SENDCTRL_AVAIL_DIS | \
4317 QIB_SENDCTRL_AVAIL_ENB | \
4318 QIB_SENDCTRL_AVAIL_BLIP | \
4319 QIB_SENDCTRL_DISARM | \
4320 QIB_SENDCTRL_DISARM_ALL | \
4321 QIB_SENDCTRL_SEND_ENB)
4322
4323#define SENDCTRL_PORT_MODS (\
4324 QIB_SENDCTRL_CLEAR | \
4325 QIB_SENDCTRL_SEND_ENB | \
4326 QIB_SENDCTRL_SEND_DIS | \
4327 QIB_SENDCTRL_FLUSH)
4328
4329static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4330{
4331 struct qib_devdata *dd = ppd->dd;
4332 u64 tmp_dd_sendctrl;
4333 unsigned long flags;
4334
4335 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4336
4337
4338 if (op & QIB_SENDCTRL_CLEAR)
4339 dd->sendctrl = 0;
4340 if (op & QIB_SENDCTRL_AVAIL_DIS)
4341 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4342 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4343 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4344 if (dd->flags & QIB_USE_SPCL_TRIG)
4345 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4346 }
4347
4348
4349 if (op & QIB_SENDCTRL_SEND_DIS)
4350 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4351 else if (op & QIB_SENDCTRL_SEND_ENB)
4352 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4353
4354 if (op & QIB_SENDCTRL_DISARM_ALL) {
4355 u32 i, last;
4356
4357 tmp_dd_sendctrl = dd->sendctrl;
4358 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4359
4360
4361
4362
4363 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4364 for (i = 0; i < last; i++) {
4365 qib_write_kreg(dd, kr_sendctrl,
4366 tmp_dd_sendctrl |
4367 SYM_MASK(SendCtrl, Disarm) | i);
4368 qib_write_kreg(dd, kr_scratch, 0);
4369 }
4370 }
4371
4372 if (op & QIB_SENDCTRL_FLUSH) {
4373 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4374
4375
4376
4377
4378
4379 tmp_ppd_sendctrl |=
4380 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4381 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4382 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4383 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4384 qib_write_kreg(dd, kr_scratch, 0);
4385 }
4386
4387 tmp_dd_sendctrl = dd->sendctrl;
4388
4389 if (op & QIB_SENDCTRL_DISARM)
4390 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4391 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4392 SYM_LSB(SendCtrl, DisarmSendBuf));
4393 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4394 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4395 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4396
4397 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4398 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4399 qib_write_kreg(dd, kr_scratch, 0);
4400 }
4401
4402 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4403 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4404 qib_write_kreg(dd, kr_scratch, 0);
4405 }
4406
4407 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4408 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4409 qib_write_kreg(dd, kr_scratch, 0);
4410 }
4411
4412 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4413
4414 if (op & QIB_SENDCTRL_FLUSH) {
4415 u32 v;
4416
4417
4418
4419
4420
4421
4422 v = qib_read_kreg32(dd, kr_scratch);
4423 qib_write_kreg(dd, kr_scratch, v);
4424 v = qib_read_kreg32(dd, kr_scratch);
4425 qib_write_kreg(dd, kr_scratch, v);
4426 qib_read_kreg32(dd, kr_scratch);
4427 }
4428}
4429
4430#define _PORT_VIRT_FLAG 0x8000U
4431#define _PORT_64BIT_FLAG 0x10000U
4432#define _PORT_CNTR_IDXMASK 0x7fffU
4433
4434
4435
4436
4437
4438
4439static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4440{
4441 struct qib_devdata *dd = ppd->dd;
4442 u64 ret = 0ULL;
4443 u16 creg;
4444
4445 static const u32 xlator[] = {
4446 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4447 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4448 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4449 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4450 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4451 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4452 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4453 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4454 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4455 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4456 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4457 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4458 [QIBPORTCNTR_RXDROPPKT] = 0xffff,
4459 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4460 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4461 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4462 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4463 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4464 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4465 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4466 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4467 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4468 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4469 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4470 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4471 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4472 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4473 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4474 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4475 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4476
4477
4478
4479
4480
4481 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4482 [QIBPORTCNTR_PSSTART] = krp_psstart,
4483 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4484
4485 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4486 };
4487
4488 if (reg >= ARRAY_SIZE(xlator)) {
4489 qib_devinfo(ppd->dd->pcidev,
4490 "Unimplemented portcounter %u\n", reg);
4491 goto done;
4492 }
4493 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4494
4495
4496 if (reg == QIBPORTCNTR_KHDROVFL) {
4497 int i;
4498
4499
4500 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4501 struct qib_ctxtdata *rcd = dd->rcd[i];
4502
4503 if (!rcd || rcd->ppd != ppd)
4504 continue;
4505 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4506 }
4507 goto done;
4508 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4509
4510
4511
4512
4513
4514 goto done;
4515 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4516 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4517
4518 ret = qib_read_kreg_port(ppd, creg);
4519 goto done;
4520 }
4521
4522
4523
4524
4525
4526 if (xlator[reg] & _PORT_64BIT_FLAG)
4527 ret = read_7322_creg_port(ppd, creg);
4528 else
4529 ret = read_7322_creg32_port(ppd, creg);
4530 if (creg == crp_ibsymbolerr) {
4531 if (ppd->cpspec->ibdeltainprog)
4532 ret -= ret - ppd->cpspec->ibsymsnap;
4533 ret -= ppd->cpspec->ibsymdelta;
4534 } else if (creg == crp_iblinkerrrecov) {
4535 if (ppd->cpspec->ibdeltainprog)
4536 ret -= ret - ppd->cpspec->iblnkerrsnap;
4537 ret -= ppd->cpspec->iblnkerrdelta;
4538 } else if (creg == crp_errlink)
4539 ret -= ppd->cpspec->ibmalfdelta;
4540 else if (creg == crp_iblinkdown)
4541 ret += ppd->cpspec->iblnkdowndelta;
4542done:
4543 return ret;
4544}
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559static const char cntr7322names[] =
4560 "Interrupts\n"
4561 "HostBusStall\n"
4562 "E RxTIDFull\n"
4563 "RxTIDInvalid\n"
4564 "RxTIDFloDrop\n"
4565 "Ctxt0EgrOvfl\n"
4566 "Ctxt1EgrOvfl\n"
4567 "Ctxt2EgrOvfl\n"
4568 "Ctxt3EgrOvfl\n"
4569 "Ctxt4EgrOvfl\n"
4570 "Ctxt5EgrOvfl\n"
4571 "Ctxt6EgrOvfl\n"
4572 "Ctxt7EgrOvfl\n"
4573 "Ctxt8EgrOvfl\n"
4574 "Ctxt9EgrOvfl\n"
4575 "Ctx10EgrOvfl\n"
4576 "Ctx11EgrOvfl\n"
4577 "Ctx12EgrOvfl\n"
4578 "Ctx13EgrOvfl\n"
4579 "Ctx14EgrOvfl\n"
4580 "Ctx15EgrOvfl\n"
4581 "Ctx16EgrOvfl\n"
4582 "Ctx17EgrOvfl\n"
4583 ;
4584
4585static const u32 cntr7322indices[] = {
4586 cr_lbint | _PORT_64BIT_FLAG,
4587 cr_lbstall | _PORT_64BIT_FLAG,
4588 cr_tidfull,
4589 cr_tidinvalid,
4590 cr_rxtidflowdrop,
4591 cr_base_egrovfl + 0,
4592 cr_base_egrovfl + 1,
4593 cr_base_egrovfl + 2,
4594 cr_base_egrovfl + 3,
4595 cr_base_egrovfl + 4,
4596 cr_base_egrovfl + 5,
4597 cr_base_egrovfl + 6,
4598 cr_base_egrovfl + 7,
4599 cr_base_egrovfl + 8,
4600 cr_base_egrovfl + 9,
4601 cr_base_egrovfl + 10,
4602 cr_base_egrovfl + 11,
4603 cr_base_egrovfl + 12,
4604 cr_base_egrovfl + 13,
4605 cr_base_egrovfl + 14,
4606 cr_base_egrovfl + 15,
4607 cr_base_egrovfl + 16,
4608 cr_base_egrovfl + 17,
4609};
4610
4611
4612
4613
4614
4615
4616static const char portcntr7322names[] =
4617 "TxPkt\n"
4618 "TxFlowPkt\n"
4619 "TxWords\n"
4620 "RxPkt\n"
4621 "RxFlowPkt\n"
4622 "RxWords\n"
4623 "TxFlowStall\n"
4624 "TxDmaDesc\n"
4625 "E RxDlidFltr\n"
4626 "IBStatusChng\n"
4627 "IBLinkDown\n"
4628 "IBLnkRecov\n"
4629 "IBRxLinkErr\n"
4630 "IBSymbolErr\n"
4631 "RxLLIErr\n"
4632 "RxBadFormat\n"
4633 "RxBadLen\n"
4634 "RxBufOvrfl\n"
4635 "RxEBP\n"
4636 "RxFlowCtlErr\n"
4637 "RxICRCerr\n"
4638 "RxLPCRCerr\n"
4639 "RxVCRCerr\n"
4640 "RxInvalLen\n"
4641 "RxInvalPKey\n"
4642 "RxPktDropped\n"
4643 "TxBadLength\n"
4644 "TxDropped\n"
4645 "TxInvalLen\n"
4646 "TxUnderrun\n"
4647 "TxUnsupVL\n"
4648 "RxLclPhyErr\n"
4649 "RxVL15Drop\n"
4650 "RxVlErr\n"
4651 "XcessBufOvfl\n"
4652 "RxQPBadCtxt\n"
4653 "TXBadHeader\n"
4654 ;
4655
4656static const u32 portcntr7322indices[] = {
4657 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
4658 crp_pktsendflow,
4659 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
4660 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
4661 crp_pktrcvflowctrl,
4662 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
4663 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
4664 crp_txsdmadesc | _PORT_64BIT_FLAG,
4665 crp_rxdlidfltr,
4666 crp_ibstatuschange,
4667 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
4668 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
4669 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
4670 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
4671 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
4672 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
4673 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
4674 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
4675 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
4676 crp_rcvflowctrlviol,
4677 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
4678 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
4679 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
4680 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
4681 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
4682 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
4683 crp_txminmaxlenerr,
4684 crp_txdroppedpkt,
4685 crp_txlenerr,
4686 crp_txunderrun,
4687 crp_txunsupvl,
4688 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
4689 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
4690 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
4691 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
4692 crp_rxqpinvalidctxt,
4693 crp_txhdrerr,
4694};
4695
4696
4697static void init_7322_cntrnames(struct qib_devdata *dd)
4698{
4699 int i, j = 0;
4700 char *s;
4701
4702 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
4703 i++) {
4704
4705 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
4706 j = 1;
4707 s = strchr(s + 1, '\n');
4708 if (s && j)
4709 j++;
4710 }
4711 dd->cspec->ncntrs = i;
4712 if (!s)
4713
4714 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
4715 else
4716 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
4717 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
4718 * sizeof(u64), GFP_KERNEL);
4719 if (!dd->cspec->cntrs)
4720 qib_dev_err(dd, "Failed allocation for counters\n");
4721
4722 for (i = 0, s = (char *)portcntr7322names; s; i++)
4723 s = strchr(s + 1, '\n');
4724 dd->cspec->nportcntrs = i - 1;
4725 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
4726 for (i = 0; i < dd->num_pports; ++i) {
4727 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
4728 * sizeof(u64), GFP_KERNEL);
4729 if (!dd->pport[i].cpspec->portcntrs)
4730 qib_dev_err(dd,
4731 "Failed allocation for portcounters\n");
4732 }
4733}
4734
4735static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
4736 u64 **cntrp)
4737{
4738 u32 ret;
4739
4740 if (namep) {
4741 ret = dd->cspec->cntrnamelen;
4742 if (pos >= ret)
4743 ret = 0;
4744 else
4745 *namep = (char *) cntr7322names;
4746 } else {
4747 u64 *cntr = dd->cspec->cntrs;
4748 int i;
4749
4750 ret = dd->cspec->ncntrs * sizeof(u64);
4751 if (!cntr || pos >= ret) {
4752
4753 ret = 0;
4754 goto done;
4755 }
4756 *cntrp = cntr;
4757 for (i = 0; i < dd->cspec->ncntrs; i++)
4758 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
4759 *cntr++ = read_7322_creg(dd,
4760 cntr7322indices[i] &
4761 _PORT_CNTR_IDXMASK);
4762 else
4763 *cntr++ = read_7322_creg32(dd,
4764 cntr7322indices[i]);
4765 }
4766done:
4767 return ret;
4768}
4769
4770static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
4771 char **namep, u64 **cntrp)
4772{
4773 u32 ret;
4774
4775 if (namep) {
4776 ret = dd->cspec->portcntrnamelen;
4777 if (pos >= ret)
4778 ret = 0;
4779 else
4780 *namep = (char *)portcntr7322names;
4781 } else {
4782 struct qib_pportdata *ppd = &dd->pport[port];
4783 u64 *cntr = ppd->cpspec->portcntrs;
4784 int i;
4785
4786 ret = dd->cspec->nportcntrs * sizeof(u64);
4787 if (!cntr || pos >= ret) {
4788
4789 ret = 0;
4790 goto done;
4791 }
4792 *cntrp = cntr;
4793 for (i = 0; i < dd->cspec->nportcntrs; i++) {
4794 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
4795 *cntr++ = qib_portcntr_7322(ppd,
4796 portcntr7322indices[i] &
4797 _PORT_CNTR_IDXMASK);
4798 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
4799 *cntr++ = read_7322_creg_port(ppd,
4800 portcntr7322indices[i] &
4801 _PORT_CNTR_IDXMASK);
4802 else
4803 *cntr++ = read_7322_creg32_port(ppd,
4804 portcntr7322indices[i]);
4805 }
4806 }
4807done:
4808 return ret;
4809}
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822static void qib_get_7322_faststats(unsigned long opaque)
4823{
4824 struct qib_devdata *dd = (struct qib_devdata *) opaque;
4825 struct qib_pportdata *ppd;
4826 unsigned long flags;
4827 u64 traffic_wds;
4828 int pidx;
4829
4830 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
4831 ppd = dd->pport + pidx;
4832
4833
4834
4835
4836
4837
4838 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
4839 || dd->diag_client)
4840 continue;
4841
4842
4843
4844
4845
4846
4847 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
4848 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
4849 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
4850 traffic_wds -= ppd->dd->traffic_wds;
4851 ppd->dd->traffic_wds += traffic_wds;
4852 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
4853 atomic_add(ACTIVITY_TIMER, &ppd->dd->active_time);
4854 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
4855 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
4856 QIB_IB_QDR) &&
4857 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
4858 QIBL_LINKACTIVE)) &&
4859 ppd->cpspec->qdr_dfe_time &&
4860 time_is_before_jiffies(ppd->cpspec->qdr_dfe_time)) {
4861 ppd->cpspec->qdr_dfe_on = 0;
4862
4863 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
4864 ppd->dd->cspec->r1 ?
4865 QDR_STATIC_ADAPT_INIT_R1 :
4866 QDR_STATIC_ADAPT_INIT);
4867 force_h1(ppd);
4868 }
4869 }
4870 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
4871}
4872
4873
4874
4875
4876static int qib_7322_intr_fallback(struct qib_devdata *dd)
4877{
4878 if (!dd->cspec->num_msix_entries)
4879 return 0;
4880
4881 qib_devinfo(dd->pcidev,
4882 "MSIx interrupt not detected, trying INTx interrupts\n");
4883 qib_7322_nomsix(dd);
4884 qib_enable_intx(dd->pcidev);
4885 qib_setup_7322_interrupt(dd, 0);
4886 return 1;
4887}
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
4899{
4900 u64 val;
4901 struct qib_devdata *dd = ppd->dd;
4902 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
4903 SYM_MASK(IBPCSConfig_0, xcv_treset) |
4904 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
4905
4906 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
4907 qib_write_kreg(dd, kr_hwerrmask,
4908 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
4909 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4910 ppd->cpspec->ibcctrl_a &
4911 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
4912
4913 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
4914 qib_read_kreg32(dd, kr_scratch);
4915 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
4916 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4917 qib_write_kreg(dd, kr_scratch, 0ULL);
4918 qib_write_kreg(dd, kr_hwerrclear,
4919 SYM_MASK(HwErrClear, statusValidNoEopClear));
4920 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
4921}
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
4932 u32 dcnt, u32 *data)
4933{
4934 int i;
4935 u64 pbc;
4936 u32 __iomem *piobuf;
4937 u32 pnum, control, len;
4938 struct qib_devdata *dd = ppd->dd;
4939
4940 i = 0;
4941 len = 7 + dcnt + 1;
4942 control = qib_7322_setpbc_control(ppd, len, 0, 15);
4943 pbc = ((u64) control << 32) | len;
4944 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
4945 if (i++ > 15)
4946 return;
4947 udelay(2);
4948 }
4949
4950 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
4951 writeq(pbc, piobuf);
4952 qib_flush_wc();
4953 qib_pio_copy(piobuf + 2, hdr, 7);
4954 qib_pio_copy(piobuf + 9, data, dcnt);
4955 if (dd->flags & QIB_USE_SPCL_TRIG) {
4956 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
4957
4958 qib_flush_wc();
4959 __raw_writel(0xaebecede, piobuf + spcl_off);
4960 }
4961 qib_flush_wc();
4962 qib_sendbuf_done(dd, pnum);
4963
4964 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
4965}
4966
4967
4968
4969
4970static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
4971{
4972 struct qib_devdata *dd = ppd->dd;
4973 static u32 swapped;
4974 u32 dw, i, hcnt, dcnt, *data;
4975 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
4976 static u32 madpayload_start[0x40] = {
4977 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4978 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4979 0x1, 0x1388, 0x15e, 0x1,
4980 };
4981 static u32 madpayload_done[0x40] = {
4982 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4983 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4984 0x40000001, 0x1388, 0x15e,
4985 };
4986
4987 dcnt = ARRAY_SIZE(madpayload_start);
4988 hcnt = ARRAY_SIZE(hdr);
4989 if (!swapped) {
4990
4991 for (i = 0; i < hcnt; i++) {
4992 dw = (__force u32) cpu_to_be32(hdr[i]);
4993 hdr[i] = dw;
4994 }
4995 for (i = 0; i < dcnt; i++) {
4996 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
4997 madpayload_start[i] = dw;
4998 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
4999 madpayload_done[i] = dw;
5000 }
5001 swapped = 1;
5002 }
5003
5004 data = which ? madpayload_done : madpayload_start;
5005
5006 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
5007 qib_read_kreg64(dd, kr_scratch);
5008 udelay(2);
5009 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
5010 qib_read_kreg64(dd, kr_scratch);
5011 udelay(2);
5012}
5013
5014
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
5029{
5030 u64 newctrlb;
5031 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
5032 IBA7322_IBC_IBTA_1_2_MASK |
5033 IBA7322_IBC_MAX_SPEED_MASK);
5034
5035 if (speed & (speed - 1))
5036 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
5037 IBA7322_IBC_IBTA_1_2_MASK |
5038 IBA7322_IBC_MAX_SPEED_MASK;
5039 else
5040 newctrlb |= speed == QIB_IB_QDR ?
5041 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
5042 ((speed == QIB_IB_DDR ?
5043 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
5044
5045 if (newctrlb == ppd->cpspec->ibcctrl_b)
5046 return;
5047
5048 ppd->cpspec->ibcctrl_b = newctrlb;
5049 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
5050 qib_write_kreg(ppd->dd, kr_scratch, 0);
5051}
5052
5053
5054
5055
5056
5057
5058
5059static void try_7322_autoneg(struct qib_pportdata *ppd)
5060{
5061 unsigned long flags;
5062
5063 spin_lock_irqsave(&ppd->lflags_lock, flags);
5064 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
5065 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5066 qib_autoneg_7322_send(ppd, 0);
5067 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5068 qib_7322_mini_pcs_reset(ppd);
5069
5070 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
5071 msecs_to_jiffies(2));
5072}
5073
5074
5075
5076
5077
5078static void autoneg_7322_work(struct work_struct *work)
5079{
5080 struct qib_pportdata *ppd;
5081 struct qib_devdata *dd;
5082 u64 startms;
5083 u32 i;
5084 unsigned long flags;
5085
5086 ppd = container_of(work, struct qib_chippport_specific,
5087 autoneg_work.work)->ppd;
5088 dd = ppd->dd;
5089
5090 startms = jiffies_to_msecs(jiffies);
5091
5092
5093
5094
5095
5096 for (i = 0; i < 25; i++) {
5097 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
5098 == IB_7322_LT_STATE_POLLQUIET) {
5099 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
5100 break;
5101 }
5102 udelay(100);
5103 }
5104
5105 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
5106 goto done;
5107
5108
5109 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5110 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5111 msecs_to_jiffies(90)))
5112 goto done;
5113 qib_7322_mini_pcs_reset(ppd);
5114
5115
5116 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5117 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5118 msecs_to_jiffies(1700)))
5119 goto done;
5120 qib_7322_mini_pcs_reset(ppd);
5121
5122 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5123
5124
5125
5126
5127
5128 wait_event_timeout(ppd->cpspec->autoneg_wait,
5129 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5130 msecs_to_jiffies(250));
5131done:
5132 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5133 spin_lock_irqsave(&ppd->lflags_lock, flags);
5134 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5135 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5136 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5137 ppd->cpspec->autoneg_tries = 0;
5138 }
5139 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5140 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5141 }
5142}
5143
5144
5145
5146
5147
5148static void try_7322_ipg(struct qib_pportdata *ppd)
5149{
5150 struct qib_ibport *ibp = &ppd->ibport_data;
5151 struct ib_mad_send_buf *send_buf;
5152 struct ib_mad_agent *agent;
5153 struct ib_smp *smp;
5154 unsigned delay;
5155 int ret;
5156
5157 agent = ibp->send_agent;
5158 if (!agent)
5159 goto retry;
5160
5161 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
5162 IB_MGMT_MAD_DATA, GFP_ATOMIC);
5163 if (IS_ERR(send_buf))
5164 goto retry;
5165
5166 if (!ibp->smi_ah) {
5167 struct ib_ah *ah;
5168
5169 ah = qib_create_qp0_ah(ibp, be16_to_cpu(IB_LID_PERMISSIVE));
5170 if (IS_ERR(ah))
5171 ret = PTR_ERR(ah);
5172 else {
5173 send_buf->ah = ah;
5174 ibp->smi_ah = to_iah(ah);
5175 ret = 0;
5176 }
5177 } else {
5178 send_buf->ah = &ibp->smi_ah->ibah;
5179 ret = 0;
5180 }
5181
5182 smp = send_buf->mad;
5183 smp->base_version = IB_MGMT_BASE_VERSION;
5184 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5185 smp->class_version = 1;
5186 smp->method = IB_MGMT_METHOD_SEND;
5187 smp->hop_cnt = 1;
5188 smp->attr_id = QIB_VENDOR_IPG;
5189 smp->attr_mod = 0;
5190
5191 if (!ret)
5192 ret = ib_post_send_mad(send_buf, NULL);
5193 if (ret)
5194 ib_free_send_mad(send_buf);
5195retry:
5196 delay = 2 << ppd->cpspec->ipg_tries;
5197 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work,
5198 msecs_to_jiffies(delay));
5199}
5200
5201
5202
5203
5204
5205static void ipg_7322_work(struct work_struct *work)
5206{
5207 struct qib_pportdata *ppd;
5208
5209 ppd = container_of(work, struct qib_chippport_specific,
5210 ipg_work.work)->ppd;
5211 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5212 && ++ppd->cpspec->ipg_tries <= 10)
5213 try_7322_ipg(ppd);
5214}
5215
5216static u32 qib_7322_iblink_state(u64 ibcs)
5217{
5218 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5219
5220 switch (state) {
5221 case IB_7322_L_STATE_INIT:
5222 state = IB_PORT_INIT;
5223 break;
5224 case IB_7322_L_STATE_ARM:
5225 state = IB_PORT_ARMED;
5226 break;
5227 case IB_7322_L_STATE_ACTIVE:
5228
5229 case IB_7322_L_STATE_ACT_DEFER:
5230 state = IB_PORT_ACTIVE;
5231 break;
5232 default:
5233 case IB_7322_L_STATE_DOWN:
5234 state = IB_PORT_DOWN;
5235 break;
5236 }
5237 return state;
5238}
5239
5240
5241static u8 qib_7322_phys_portstate(u64 ibcs)
5242{
5243 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5244 return qib_7322_physportstate[state];
5245}
5246
5247static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5248{
5249 int ret = 0, symadj = 0;
5250 unsigned long flags;
5251 int mult;
5252
5253 spin_lock_irqsave(&ppd->lflags_lock, flags);
5254 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5255 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5256
5257
5258 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5259 ppd->link_speed_active = QIB_IB_QDR;
5260 mult = 4;
5261 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5262 ppd->link_speed_active = QIB_IB_DDR;
5263 mult = 2;
5264 } else {
5265 ppd->link_speed_active = QIB_IB_SDR;
5266 mult = 1;
5267 }
5268 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5269 ppd->link_width_active = IB_WIDTH_4X;
5270 mult *= 4;
5271 } else
5272 ppd->link_width_active = IB_WIDTH_1X;
5273 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5274
5275 if (!ibup) {
5276 u64 clr;
5277
5278
5279
5280 ppd->cpspec->ipg_tries = 0;
5281 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5282 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5283 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5284 if (clr)
5285 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5286 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5287 QIBL_IB_AUTONEG_INPROG)))
5288 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5289 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5290 struct qib_qsfp_data *qd =
5291 &ppd->cpspec->qsfp_data;
5292
5293 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5294 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5295 reset_tx_deemphasis_override));
5296 qib_cancel_sends(ppd);
5297
5298 qib_7322_mini_pcs_reset(ppd);
5299
5300
5301 if (ppd->dd->flags & QIB_HAS_QSFP) {
5302 qd->t_insert = jiffies;
5303 queue_work(ib_wq, &qd->work);
5304 }
5305 spin_lock_irqsave(&ppd->sdma_lock, flags);
5306 if (__qib_sdma_running(ppd))
5307 __qib_sdma_process_event(ppd,
5308 qib_sdma_event_e70_go_idle);
5309 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5310 }
5311 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5312 if (clr == ppd->cpspec->iblnkdownsnap)
5313 ppd->cpspec->iblnkdowndelta++;
5314 } else {
5315 if (qib_compat_ddr_negotiate &&
5316 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5317 QIBL_IB_AUTONEG_INPROG)) &&
5318 ppd->link_speed_active == QIB_IB_SDR &&
5319 (ppd->link_speed_enabled & QIB_IB_DDR)
5320 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5321
5322 ++ppd->cpspec->autoneg_tries;
5323 if (!ppd->cpspec->ibdeltainprog) {
5324 ppd->cpspec->ibdeltainprog = 1;
5325 ppd->cpspec->ibsymdelta +=
5326 read_7322_creg32_port(ppd,
5327 crp_ibsymbolerr) -
5328 ppd->cpspec->ibsymsnap;
5329 ppd->cpspec->iblnkerrdelta +=
5330 read_7322_creg32_port(ppd,
5331 crp_iblinkerrrecov) -
5332 ppd->cpspec->iblnkerrsnap;
5333 }
5334 try_7322_autoneg(ppd);
5335 ret = 1;
5336 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5337 ppd->link_speed_active == QIB_IB_SDR) {
5338 qib_autoneg_7322_send(ppd, 1);
5339 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5340 qib_7322_mini_pcs_reset(ppd);
5341 udelay(2);
5342 ret = 1;
5343 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5344 (ppd->link_speed_active & QIB_IB_DDR)) {
5345 spin_lock_irqsave(&ppd->lflags_lock, flags);
5346 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5347 QIBL_IB_AUTONEG_FAILED);
5348 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5349 ppd->cpspec->autoneg_tries = 0;
5350
5351 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5352 wake_up(&ppd->cpspec->autoneg_wait);
5353 symadj = 1;
5354 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5355
5356
5357
5358
5359
5360
5361 spin_lock_irqsave(&ppd->lflags_lock, flags);
5362 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5363 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5364 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5365 symadj = 1;
5366 }
5367 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5368 symadj = 1;
5369 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5370 try_7322_ipg(ppd);
5371 if (!ppd->cpspec->recovery_init)
5372 setup_7322_link_recovery(ppd, 0);
5373 ppd->cpspec->qdr_dfe_time = jiffies +
5374 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5375 }
5376 ppd->cpspec->ibmalfusesnap = 0;
5377 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5378 crp_errlink);
5379 }
5380 if (symadj) {
5381 ppd->cpspec->iblnkdownsnap =
5382 read_7322_creg32_port(ppd, crp_iblinkdown);
5383 if (ppd->cpspec->ibdeltainprog) {
5384 ppd->cpspec->ibdeltainprog = 0;
5385 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5386 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5387 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5388 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5389 }
5390 } else if (!ibup && qib_compat_ddr_negotiate &&
5391 !ppd->cpspec->ibdeltainprog &&
5392 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5393 ppd->cpspec->ibdeltainprog = 1;
5394 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5395 crp_ibsymbolerr);
5396 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5397 crp_iblinkerrrecov);
5398 }
5399
5400 if (!ret)
5401 qib_setup_7322_setextled(ppd, ibup);
5402 return ret;
5403}
5404
5405
5406
5407
5408
5409
5410
5411
5412static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5413{
5414 u64 read_val, new_out;
5415 unsigned long flags;
5416
5417 if (mask) {
5418
5419 dir &= mask;
5420 out &= mask;
5421 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5422 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5423 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5424 new_out = (dd->cspec->gpio_out & ~mask) | out;
5425
5426 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5427 qib_write_kreg(dd, kr_gpio_out, new_out);
5428 dd->cspec->gpio_out = new_out;
5429 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5430 }
5431
5432
5433
5434
5435
5436
5437
5438
5439 read_val = qib_read_kreg64(dd, kr_extstatus);
5440 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5441}
5442
5443
5444static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5445{
5446 int prev_wen;
5447 u32 mask;
5448
5449 mask = 1 << QIB_EEPROM_WEN_NUM;
5450 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5451 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5452
5453 return prev_wen & 1;
5454}
5455
5456
5457
5458
5459
5460
5461static void get_7322_chip_params(struct qib_devdata *dd)
5462{
5463 u64 val;
5464 u32 piobufs;
5465 int mtu;
5466
5467 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5468
5469 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5470
5471 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5472 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5473 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5474 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5475 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5476
5477 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5478 dd->piobcnt2k = val & ~0U;
5479 dd->piobcnt4k = val >> 32;
5480 val = qib_read_kreg64(dd, kr_sendpiosize);
5481 dd->piosize2k = val & ~0U;
5482 dd->piosize4k = val >> 32;
5483
5484 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5485 if (mtu == -1)
5486 mtu = QIB_DEFAULT_MTU;
5487 dd->pport[0].ibmtu = (u32)mtu;
5488 dd->pport[1].ibmtu = (u32)mtu;
5489
5490
5491 dd->pio2kbase = (u32 __iomem *)
5492 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5493 dd->pio4kbase = (u32 __iomem *)
5494 ((char __iomem *) dd->kregbase +
5495 (dd->piobufbase >> 32));
5496
5497
5498
5499
5500
5501 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5502
5503 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5504
5505 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5506 (sizeof(u64) * BITS_PER_BYTE / 2);
5507}
5508
5509
5510
5511
5512
5513
5514static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5515{
5516 u32 cregbase;
5517 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5518
5519 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5520 (char __iomem *)dd->kregbase);
5521
5522 dd->egrtidbase = (u64 __iomem *)
5523 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5524
5525
5526 dd->pport[0].cpspec->kpregbase =
5527 (u64 __iomem *)((char __iomem *)dd->kregbase);
5528 dd->pport[1].cpspec->kpregbase =
5529 (u64 __iomem *)(dd->palign +
5530 (char __iomem *)dd->kregbase);
5531 dd->pport[0].cpspec->cpregbase =
5532 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5533 kr_counterregbase) + (char __iomem *)dd->kregbase);
5534 dd->pport[1].cpspec->cpregbase =
5535 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5536 kr_counterregbase) + (char __iomem *)dd->kregbase);
5537}
5538
5539
5540
5541
5542
5543
5544#define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5545 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5546 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5547 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5548 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5549 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5550 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5551
5552static int sendctrl_hook(struct qib_devdata *dd,
5553 const struct diag_observer *op, u32 offs,
5554 u64 *data, u64 mask, int only_32)
5555{
5556 unsigned long flags;
5557 unsigned idx;
5558 unsigned pidx;
5559 struct qib_pportdata *ppd = NULL;
5560 u64 local_data, all_bits;
5561
5562
5563
5564
5565
5566
5567
5568 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5569 u64 __iomem *psptr;
5570 u32 psoffs;
5571
5572 ppd = dd->pport + pidx;
5573 if (!ppd->cpspec->kpregbase)
5574 continue;
5575
5576 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5577 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5578 if (psoffs == offs)
5579 break;
5580 }
5581
5582
5583 if (pidx >= dd->num_pports)
5584 ppd = NULL;
5585
5586
5587 idx = offs / sizeof(u64);
5588
5589 all_bits = ~0ULL;
5590 if (only_32)
5591 all_bits >>= 32;
5592
5593 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5594 if (!ppd || (mask & all_bits) != all_bits) {
5595
5596
5597
5598
5599
5600
5601
5602 if (only_32)
5603 local_data = (u64)qib_read_kreg32(dd, idx);
5604 else
5605 local_data = qib_read_kreg64(dd, idx);
5606 *data = (local_data & ~mask) | (*data & mask);
5607 }
5608 if (mask) {
5609
5610
5611
5612
5613 u64 sval, tval;
5614
5615
5616
5617
5618
5619 if (ppd) {
5620 sval = ppd->p_sendctrl & ~mask;
5621 sval |= *data & SENDCTRL_SHADOWED & mask;
5622 ppd->p_sendctrl = sval;
5623 } else
5624 sval = *data & SENDCTRL_SHADOWED & mask;
5625 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5626 qib_write_kreg(dd, idx, tval);
5627 qib_write_kreg(dd, kr_scratch, 0Ull);
5628 }
5629 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5630 return only_32 ? 4 : 8;
5631}
5632
5633static const struct diag_observer sendctrl_0_observer = {
5634 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5635 KREG_IDX(SendCtrl_0) * sizeof(u64)
5636};
5637
5638static const struct diag_observer sendctrl_1_observer = {
5639 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5640 KREG_IDX(SendCtrl_1) * sizeof(u64)
5641};
5642
5643static ushort sdma_fetch_prio = 8;
5644module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5645MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5646
5647
5648static void init_txdds_table(struct qib_pportdata *ppd, int override);
5649
5650static void qsfp_7322_event(struct work_struct *work)
5651{
5652 struct qib_qsfp_data *qd;
5653 struct qib_pportdata *ppd;
5654 unsigned long pwrup;
5655 unsigned long flags;
5656 int ret;
5657 u32 le2;
5658
5659 qd = container_of(work, struct qib_qsfp_data, work);
5660 ppd = qd->ppd;
5661 pwrup = qd->t_insert +
5662 msecs_to_jiffies(QSFP_PWR_LAG_MSEC - QSFP_MODPRS_LAG_MSEC);
5663
5664
5665 mdelay(QSFP_MODPRS_LAG_MSEC);
5666
5667 if (!qib_qsfp_mod_present(ppd)) {
5668 ppd->cpspec->qsfp_data.modpresent = 0;
5669
5670 qib_set_ib_7322_lstate(ppd, 0,
5671 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
5672 spin_lock_irqsave(&ppd->lflags_lock, flags);
5673 ppd->lflags &= ~QIBL_LINKV;
5674 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5675 } else {
5676
5677
5678
5679
5680
5681 while (1) {
5682 if (time_is_before_jiffies(pwrup))
5683 break;
5684 msleep(20);
5685 }
5686
5687 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
5688
5689
5690
5691
5692
5693
5694
5695 if (!ret && !ppd->dd->cspec->r1) {
5696 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech))
5697 le2 = LE2_QME;
5698 else if (qd->cache.atten[1] >= qib_long_atten &&
5699 QSFP_IS_CU(qd->cache.tech))
5700 le2 = LE2_5m;
5701 else
5702 le2 = LE2_DEFAULT;
5703 } else
5704 le2 = LE2_DEFAULT;
5705 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
5706
5707
5708
5709
5710
5711
5712 init_txdds_table(ppd, 0);
5713
5714
5715
5716
5717 if (!ppd->cpspec->qsfp_data.modpresent &&
5718 (ppd->lflags & (QIBL_LINKV | QIBL_IB_LINK_DISABLED))) {
5719 ppd->cpspec->qsfp_data.modpresent = 1;
5720 qib_set_ib_7322_lstate(ppd, 0,
5721 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
5722 spin_lock_irqsave(&ppd->lflags_lock, flags);
5723 ppd->lflags |= QIBL_LINKV;
5724 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5725 }
5726 }
5727}
5728
5729
5730
5731
5732
5733static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
5734{
5735 unsigned long flags;
5736 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
5737 struct qib_devdata *dd = ppd->dd;
5738 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
5739
5740 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
5741 qd->ppd = ppd;
5742 qib_qsfp_init(qd, qsfp_7322_event);
5743 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5744 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
5745 dd->cspec->gpio_mask |= mod_prs_bit;
5746 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5747 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
5748 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5749}
5750
5751
5752
5753
5754
5755
5756
5757
5758
5759
5760
5761
5762
5763
5764static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
5765{
5766 char *nxt, *str;
5767 u32 pidx, unit, port, deflt, h1;
5768 unsigned long val;
5769 int any = 0, seth1;
5770 int txdds_size;
5771
5772 str = txselect_list;
5773
5774
5775 deflt = simple_strtoul(str, &nxt, 0);
5776 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5777 dd->pport[pidx].cpspec->no_eep = deflt;
5778
5779 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ;
5780 if (IS_QME(dd) || IS_QMH(dd))
5781 txdds_size += TXDDS_MFG_SZ;
5782
5783 while (*nxt && nxt[1]) {
5784 str = ++nxt;
5785 unit = simple_strtoul(str, &nxt, 0);
5786 if (nxt == str || !*nxt || *nxt != ',') {
5787 while (*nxt && *nxt++ != ' ')
5788 ;
5789 continue;
5790 }
5791 str = ++nxt;
5792 port = simple_strtoul(str, &nxt, 0);
5793 if (nxt == str || *nxt != '=') {
5794 while (*nxt && *nxt++ != ' ')
5795 ;
5796 continue;
5797 }
5798 str = ++nxt;
5799 val = simple_strtoul(str, &nxt, 0);
5800 if (nxt == str) {
5801 while (*nxt && *nxt++ != ' ')
5802 ;
5803 continue;
5804 }
5805 if (val >= txdds_size)
5806 continue;
5807 seth1 = 0;
5808 h1 = 0;
5809 if (*nxt == ',' && nxt[1]) {
5810 str = ++nxt;
5811 h1 = (u32)simple_strtoul(str, &nxt, 0);
5812 if (nxt == str)
5813 while (*nxt && *nxt++ != ' ')
5814 ;
5815 else
5816 seth1 = 1;
5817 }
5818 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
5819 ++pidx) {
5820 struct qib_pportdata *ppd = &dd->pport[pidx];
5821
5822 if (ppd->port != port || !ppd->link_speed_supported)
5823 continue;
5824 ppd->cpspec->no_eep = val;
5825 if (seth1)
5826 ppd->cpspec->h1_val = h1;
5827
5828 init_txdds_table(ppd, 1);
5829
5830
5831
5832 if (IS_QMH(dd) || IS_QME(dd))
5833 qib_set_ib_7322_lstate(ppd, 0,
5834 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
5835 any++;
5836 }
5837 if (*nxt == '\n')
5838 break;
5839 }
5840 if (change && !any) {
5841
5842
5843
5844
5845 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5846 if (dd->pport[pidx].link_speed_supported)
5847 init_txdds_table(&dd->pport[pidx], 0);
5848 }
5849}
5850
5851
5852static int setup_txselect(const char *str, struct kernel_param *kp)
5853{
5854 struct qib_devdata *dd;
5855 unsigned long val;
5856 int ret;
5857
5858 if (strlen(str) >= MAX_ATTEN_LEN) {
5859 pr_info("txselect_values string too long\n");
5860 return -ENOSPC;
5861 }
5862 ret = kstrtoul(str, 0, &val);
5863 if (ret || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
5864 TXDDS_MFG_SZ)) {
5865 pr_info("txselect_values must start with a number < %d\n",
5866 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ);
5867 return ret ? ret : -EINVAL;
5868 }
5869
5870 strcpy(txselect_list, str);
5871 list_for_each_entry(dd, &qib_dev_list, list)
5872 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
5873 set_no_qsfp_atten(dd, 1);
5874 return 0;
5875}
5876
5877
5878
5879
5880
5881
5882static int qib_late_7322_initreg(struct qib_devdata *dd)
5883{
5884 int ret = 0, n;
5885 u64 val;
5886
5887 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
5888 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
5889 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
5890 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
5891 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
5892 if (val != dd->pioavailregs_phys) {
5893 qib_dev_err(dd,
5894 "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n",
5895 (unsigned long) dd->pioavailregs_phys,
5896 (unsigned long long) val);
5897 ret = -EINVAL;
5898 }
5899
5900 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
5901 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
5902
5903 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
5904
5905 qib_register_observer(dd, &sendctrl_0_observer);
5906 qib_register_observer(dd, &sendctrl_1_observer);
5907
5908 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
5909 qib_write_kreg(dd, kr_control, dd->control);
5910
5911
5912
5913
5914
5915
5916 set_no_qsfp_atten(dd, 0);
5917 for (n = 0; n < dd->num_pports; ++n) {
5918 struct qib_pportdata *ppd = dd->pport + n;
5919
5920 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
5921 sdma_fetch_prio & 0xf);
5922
5923 if (dd->flags & QIB_HAS_QSFP)
5924 qib_init_7322_qsfp(ppd);
5925 }
5926 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
5927 qib_write_kreg(dd, kr_control, dd->control);
5928
5929 return ret;
5930}
5931
5932
5933#define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
5934 MASK_ACROSS(8, 15))
5935#define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
5936#define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
5937 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
5938 MASK_ACROSS(0, 11))
5939
5940
5941
5942
5943
5944
5945
5946static void write_7322_init_portregs(struct qib_pportdata *ppd)
5947{
5948 u64 val;
5949 int i;
5950
5951 if (!ppd->link_speed_supported) {
5952
5953 for (i = 1; i < 8; i++)
5954 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
5955 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
5956 qib_write_kreg(ppd->dd, kr_scratch, 0);
5957 return;
5958 }
5959
5960
5961
5962
5963
5964 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
5965 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
5966 val |= (u64)(ppd->vls_supported - 1) <<
5967 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
5968 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
5969
5970 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
5971
5972
5973 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
5974 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
5975 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
5976
5977 qib_write_kreg_port(ppd, krp_ncmodectrl,
5978 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
5979
5980
5981
5982
5983
5984 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
5985 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
5986 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
5987 if (ppd->dd->cspec->r1)
5988 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
5989}
5990
5991
5992
5993
5994
5995
5996
5997
5998static void write_7322_initregs(struct qib_devdata *dd)
5999{
6000 struct qib_pportdata *ppd;
6001 int i, pidx;
6002 u64 val;
6003
6004
6005 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
6006
6007 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
6008 unsigned n, regno;
6009 unsigned long flags;
6010
6011 if (dd->n_krcv_queues < 2 ||
6012 !dd->pport[pidx].link_speed_supported)
6013 continue;
6014
6015 ppd = &dd->pport[pidx];
6016
6017
6018 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
6019 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
6020 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
6021
6022
6023 regno = krp_rcvqpmaptable;
6024 val = 0;
6025 if (dd->num_pports > 1)
6026 n = dd->first_user_ctxt / dd->num_pports;
6027 else
6028 n = dd->first_user_ctxt - 1;
6029 for (i = 0; i < 32; ) {
6030 unsigned ctxt;
6031
6032 if (dd->num_pports > 1)
6033 ctxt = (i % n) * dd->num_pports + pidx;
6034 else if (i % n)
6035 ctxt = (i % n) + 1;
6036 else
6037 ctxt = ppd->hw_pidx;
6038 val |= ctxt << (5 * (i % 6));
6039 i++;
6040 if (i % 6 == 0) {
6041 qib_write_kreg_port(ppd, regno, val);
6042 val = 0;
6043 regno++;
6044 }
6045 }
6046 qib_write_kreg_port(ppd, regno, val);
6047 }
6048
6049
6050
6051
6052
6053
6054
6055 for (i = 0; i < dd->first_user_ctxt; i++) {
6056 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
6057 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
6058 }
6059
6060
6061
6062
6063
6064
6065 val = TIDFLOW_ERRBITS;
6066 for (i = 0; i < dd->cfgctxts; i++) {
6067 int flow;
6068 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
6069 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
6070 }
6071
6072
6073
6074
6075
6076
6077 if (dd->num_pports)
6078 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
6079}
6080
6081static int qib_init_7322_variables(struct qib_devdata *dd)
6082{
6083 struct qib_pportdata *ppd;
6084 unsigned features, pidx, sbufcnt;
6085 int ret, mtu;
6086 u32 sbufs, updthresh;
6087
6088
6089 ppd = (struct qib_pportdata *)(dd + 1);
6090 dd->pport = ppd;
6091 ppd[0].dd = dd;
6092 ppd[1].dd = dd;
6093
6094 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
6095
6096 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
6097 ppd[1].cpspec = &ppd[0].cpspec[1];
6098 ppd[0].cpspec->ppd = &ppd[0];
6099 ppd[1].cpspec->ppd = &ppd[1];
6100
6101 spin_lock_init(&dd->cspec->rcvmod_lock);
6102 spin_lock_init(&dd->cspec->gpio_lock);
6103
6104
6105 dd->revision = readq(&dd->kregbase[kr_revision]);
6106
6107 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
6108 qib_dev_err(dd,
6109 "Revision register read failure, giving up initialization\n");
6110 ret = -ENODEV;
6111 goto bail;
6112 }
6113 dd->flags |= QIB_PRESENT;
6114
6115 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
6116 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
6117 dd->cspec->r1 = dd->minrev == 1;
6118
6119 get_7322_chip_params(dd);
6120 features = qib_7322_boardname(dd);
6121
6122
6123 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
6124 NUM_VL15_BUFS + BITS_PER_LONG - 1;
6125 sbufcnt /= BITS_PER_LONG;
6126 dd->cspec->sendchkenable = kmalloc(sbufcnt *
6127 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
6128 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
6129 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
6130 dd->cspec->sendibchk = kmalloc(sbufcnt *
6131 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
6132 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6133 !dd->cspec->sendibchk) {
6134 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
6135 ret = -ENOMEM;
6136 goto bail;
6137 }
6138
6139 ppd = dd->pport;
6140
6141
6142
6143
6144
6145 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
6146 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
6147 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
6148
6149 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
6150 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
6151 QIB_HAS_THRESH_UPDATE |
6152 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
6153 dd->flags |= qib_special_trigger ?
6154 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
6155
6156
6157
6158
6159
6160 qib_7322_set_baseaddrs(dd);
6161
6162 mtu = ib_mtu_enum_to_int(qib_ibmtu);
6163 if (mtu == -1)
6164 mtu = QIB_DEFAULT_MTU;
6165
6166 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6167
6168 dd->cspec->hwerrmask = ~0ULL;
6169
6170
6171 dd->cspec->hwerrmask &=
6172 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
6173 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
6174 HWE_MASK(LATriggered));
6175
6176 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6177 struct qib_chippport_specific *cp = ppd->cpspec;
6178 ppd->link_speed_supported = features & PORT_SPD_CAP;
6179 features >>= PORT_SPD_CAP_SHIFT;
6180 if (!ppd->link_speed_supported) {
6181
6182 dd->skip_kctxt_mask |= 1 << pidx;
6183 if (pidx == 0) {
6184
6185 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6186 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6187 ppd[0] = ppd[1];
6188 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6189 IBSerdesPClkNotDetectMask_0)
6190 | SYM_MASK(HwErrMask,
6191 SDmaMemReadErrMask_0));
6192 dd->cspec->int_enable_mask &= ~(
6193 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6194 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6195 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6196 SYM_MASK(IntMask, SDmaIntMask_0) |
6197 SYM_MASK(IntMask, ErrIntMask_0) |
6198 SYM_MASK(IntMask, SendDoneIntMask_0));
6199 } else {
6200
6201 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6202 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6203 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6204 IBSerdesPClkNotDetectMask_1)
6205 | SYM_MASK(HwErrMask,
6206 SDmaMemReadErrMask_1));
6207 dd->cspec->int_enable_mask &= ~(
6208 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6209 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6210 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6211 SYM_MASK(IntMask, SDmaIntMask_1) |
6212 SYM_MASK(IntMask, ErrIntMask_1) |
6213 SYM_MASK(IntMask, SendDoneIntMask_1));
6214 }
6215 continue;
6216 }
6217
6218 dd->num_pports++;
6219 qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6220
6221 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6222 ppd->link_width_enabled = IB_WIDTH_4X;
6223 ppd->link_speed_enabled = ppd->link_speed_supported;
6224
6225
6226
6227
6228 ppd->link_width_active = IB_WIDTH_4X;
6229 ppd->link_speed_active = QIB_IB_SDR;
6230 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6231 switch (qib_num_cfg_vls) {
6232 case 1:
6233 ppd->vls_supported = IB_VL_VL0;
6234 break;
6235 case 2:
6236 ppd->vls_supported = IB_VL_VL0_1;
6237 break;
6238 default:
6239 qib_devinfo(dd->pcidev,
6240 "Invalid num_vls %u, using 4 VLs\n",
6241 qib_num_cfg_vls);
6242 qib_num_cfg_vls = 4;
6243
6244 case 4:
6245 ppd->vls_supported = IB_VL_VL0_3;
6246 break;
6247 case 8:
6248 if (mtu <= 2048)
6249 ppd->vls_supported = IB_VL_VL0_7;
6250 else {
6251 qib_devinfo(dd->pcidev,
6252 "Invalid num_vls %u for MTU %d "
6253 ", using 4 VLs\n",
6254 qib_num_cfg_vls, mtu);
6255 ppd->vls_supported = IB_VL_VL0_3;
6256 qib_num_cfg_vls = 4;
6257 }
6258 break;
6259 }
6260 ppd->vls_operational = ppd->vls_supported;
6261
6262 init_waitqueue_head(&cp->autoneg_wait);
6263 INIT_DELAYED_WORK(&cp->autoneg_work,
6264 autoneg_7322_work);
6265 if (ppd->dd->cspec->r1)
6266 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6267
6268
6269
6270
6271
6272
6273 if (!(dd->flags & QIB_HAS_QSFP)) {
6274 if (!IS_QMH(dd) && !IS_QME(dd))
6275 qib_devinfo(dd->pcidev,
6276 "IB%u:%u: Unknown mezzanine card type\n",
6277 dd->unit, ppd->port);
6278 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
6279
6280
6281
6282
6283 ppd->cpspec->no_eep = IS_QMH(dd) ?
6284 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
6285 } else
6286 cp->h1_val = H1_FORCE_VAL;
6287
6288
6289 if (!qib_mini_init)
6290 write_7322_init_portregs(ppd);
6291
6292 init_timer(&cp->chase_timer);
6293 cp->chase_timer.function = reenable_chase;
6294 cp->chase_timer.data = (unsigned long)ppd;
6295
6296 ppd++;
6297 }
6298
6299 dd->rcvhdrentsize = qib_rcvhdrentsize ?
6300 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
6301 dd->rcvhdrsize = qib_rcvhdrsize ?
6302 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
6303 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
6304
6305
6306 dd->rcvegrbufsize = max(mtu, 2048);
6307 BUG_ON(!is_power_of_2(dd->rcvegrbufsize));
6308 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
6309
6310 qib_7322_tidtemplate(dd);
6311
6312
6313
6314
6315
6316 dd->rhdrhead_intr_off =
6317 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6318
6319
6320 init_timer(&dd->stats_timer);
6321 dd->stats_timer.function = qib_get_7322_faststats;
6322 dd->stats_timer.data = (unsigned long) dd;
6323
6324 dd->ureg_align = 0x10000;
6325
6326 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6327
6328 qib_7322_config_ctxts(dd);
6329 qib_set_ctxtcnt(dd);
6330
6331 if (qib_wc_pat) {
6332 resource_size_t vl15off;
6333
6334
6335
6336
6337
6338
6339
6340 ret = init_chip_wc_pat(dd, 0);
6341 if (ret)
6342 goto bail;
6343
6344
6345 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6346 dd->piobcnt4k * dd->align4k;
6347 dd->piovl15base = ioremap_nocache(vl15off,
6348 NUM_VL15_BUFS * dd->align4k);
6349 if (!dd->piovl15base) {
6350 ret = -ENOMEM;
6351 goto bail;
6352 }
6353 }
6354 qib_7322_set_baseaddrs(dd);
6355
6356 ret = 0;
6357 if (qib_mini_init)
6358 goto bail;
6359 if (!dd->num_pports) {
6360 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6361 goto bail;
6362 }
6363
6364 write_7322_initregs(dd);
6365 ret = qib_create_ctxts(dd);
6366 init_7322_cntrnames(dd);
6367
6368 updthresh = 8U;
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380 if (dd->flags & QIB_HAS_SEND_DMA) {
6381 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6382 sbufs = updthresh > 3 ? updthresh : 3;
6383 } else {
6384 dd->cspec->sdmabufcnt = 0;
6385 sbufs = dd->piobcnt4k;
6386 }
6387 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6388 dd->cspec->sdmabufcnt;
6389 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6390 dd->cspec->lastbuf_for_pio--;
6391 dd->last_pio = dd->cspec->lastbuf_for_pio;
6392 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6393 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6394
6395
6396
6397
6398
6399
6400
6401 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6402 updthresh = dd->pbufsctxt - 2;
6403 dd->cspec->updthresh_dflt = updthresh;
6404 dd->cspec->updthresh = updthresh;
6405
6406
6407 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6408 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6409 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6410
6411 dd->psxmitwait_supported = 1;
6412 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6413bail:
6414 if (!dd->ctxtcnt)
6415 dd->ctxtcnt = 1;
6416
6417 return ret;
6418}
6419
6420static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6421 u32 *pbufnum)
6422{
6423 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6424 struct qib_devdata *dd = ppd->dd;
6425
6426
6427 if (pbc & PBC_7322_VL15_SEND) {
6428 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6429 last = first;
6430 } else {
6431 if ((plen + 1) > dd->piosize2kmax_dwords)
6432 first = dd->piobcnt2k;
6433 else
6434 first = 0;
6435 last = dd->cspec->lastbuf_for_pio;
6436 }
6437 return qib_getsendbuf_range(dd, pbufnum, first, last);
6438}
6439
6440static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6441 u32 start)
6442{
6443 qib_write_kreg_port(ppd, krp_psinterval, intv);
6444 qib_write_kreg_port(ppd, krp_psstart, start);
6445}
6446
6447
6448
6449
6450static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6451{
6452 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6453}
6454
6455static struct sdma_set_state_action sdma_7322_action_table[] = {
6456 [qib_sdma_state_s00_hw_down] = {
6457 .go_s99_running_tofalse = 1,
6458 .op_enable = 0,
6459 .op_intenable = 0,
6460 .op_halt = 0,
6461 .op_drain = 0,
6462 },
6463 [qib_sdma_state_s10_hw_start_up_wait] = {
6464 .op_enable = 0,
6465 .op_intenable = 1,
6466 .op_halt = 1,
6467 .op_drain = 0,
6468 },
6469 [qib_sdma_state_s20_idle] = {
6470 .op_enable = 1,
6471 .op_intenable = 1,
6472 .op_halt = 1,
6473 .op_drain = 0,
6474 },
6475 [qib_sdma_state_s30_sw_clean_up_wait] = {
6476 .op_enable = 0,
6477 .op_intenable = 1,
6478 .op_halt = 1,
6479 .op_drain = 0,
6480 },
6481 [qib_sdma_state_s40_hw_clean_up_wait] = {
6482 .op_enable = 1,
6483 .op_intenable = 1,
6484 .op_halt = 1,
6485 .op_drain = 0,
6486 },
6487 [qib_sdma_state_s50_hw_halt_wait] = {
6488 .op_enable = 1,
6489 .op_intenable = 1,
6490 .op_halt = 1,
6491 .op_drain = 1,
6492 },
6493 [qib_sdma_state_s99_running] = {
6494 .op_enable = 1,
6495 .op_intenable = 1,
6496 .op_halt = 0,
6497 .op_drain = 0,
6498 .go_s99_running_totrue = 1,
6499 },
6500};
6501
6502static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6503{
6504 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6505}
6506
6507static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6508{
6509 struct qib_devdata *dd = ppd->dd;
6510 unsigned lastbuf, erstbuf;
6511 u64 senddmabufmask[3] = { 0 };
6512 int n, ret = 0;
6513
6514 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6515 qib_sdma_7322_setlengen(ppd);
6516 qib_sdma_update_7322_tail(ppd, 0);
6517 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6518 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6519 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6520
6521 if (dd->num_pports)
6522 n = dd->cspec->sdmabufcnt / dd->num_pports;
6523 else
6524 n = dd->cspec->sdmabufcnt;
6525 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6526 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6527 dd->cspec->sdmabufcnt);
6528 lastbuf = erstbuf + n;
6529
6530 ppd->sdma_state.first_sendbuf = erstbuf;
6531 ppd->sdma_state.last_sendbuf = lastbuf;
6532 for (; erstbuf < lastbuf; ++erstbuf) {
6533 unsigned word = erstbuf / BITS_PER_LONG;
6534 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6535
6536 BUG_ON(word >= 3);
6537 senddmabufmask[word] |= 1ULL << bit;
6538 }
6539 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6540 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6541 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6542 return ret;
6543}
6544
6545
6546static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6547{
6548 struct qib_devdata *dd = ppd->dd;
6549 int sane;
6550 int use_dmahead;
6551 u16 swhead;
6552 u16 swtail;
6553 u16 cnt;
6554 u16 hwhead;
6555
6556 use_dmahead = __qib_sdma_running(ppd) &&
6557 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6558retry:
6559 hwhead = use_dmahead ?
6560 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6561 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6562
6563 swhead = ppd->sdma_descq_head;
6564 swtail = ppd->sdma_descq_tail;
6565 cnt = ppd->sdma_descq_cnt;
6566
6567 if (swhead < swtail)
6568
6569 sane = (hwhead >= swhead) & (hwhead <= swtail);
6570 else if (swhead > swtail)
6571
6572 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
6573 (hwhead <= swtail);
6574 else
6575
6576 sane = (hwhead == swhead);
6577
6578 if (unlikely(!sane)) {
6579 if (use_dmahead) {
6580
6581 use_dmahead = 0;
6582 goto retry;
6583 }
6584
6585 hwhead = swhead;
6586 }
6587
6588 return hwhead;
6589}
6590
6591static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
6592{
6593 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
6594
6595 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
6596 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
6597 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
6598 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
6599}
6600
6601
6602
6603
6604
6605
6606
6607static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
6608 u8 srate, u8 vl)
6609{
6610 u8 snd_mult = ppd->delay_mult;
6611 u8 rcv_mult = ib_rate_to_delay[srate];
6612 u32 ret;
6613
6614 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
6615
6616
6617 if (vl == 15)
6618 ret |= PBC_7322_VL15_SEND_CTRL;
6619 else
6620 ret |= vl << PBC_VL_NUM_LSB;
6621 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
6622
6623 return ret;
6624}
6625
6626
6627
6628
6629
6630
6631
6632
6633static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
6634{
6635 unsigned vl15bufs;
6636
6637 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
6638 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
6639 TXCHK_CHG_TYPE_KERN, NULL);
6640}
6641
6642static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
6643{
6644 if (rcd->ctxt < NUM_IB_PORTS) {
6645 if (rcd->dd->num_pports > 1) {
6646 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
6647 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
6648 } else {
6649 rcd->rcvegrcnt = KCTXT0_EGRCNT;
6650 rcd->rcvegr_tid_base = 0;
6651 }
6652 } else {
6653 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
6654 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
6655 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
6656 }
6657}
6658
6659#define QTXSLEEPS 5000
6660static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
6661 u32 len, u32 which, struct qib_ctxtdata *rcd)
6662{
6663 int i;
6664 const int last = start + len - 1;
6665 const int lastr = last / BITS_PER_LONG;
6666 u32 sleeps = 0;
6667 int wait = rcd != NULL;
6668 unsigned long flags;
6669
6670 while (wait) {
6671 unsigned long shadow;
6672 int cstart, previ = -1;
6673
6674
6675
6676
6677
6678
6679
6680
6681
6682 for (cstart = start; cstart <= last; cstart++) {
6683 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6684 / BITS_PER_LONG;
6685 if (i != previ) {
6686 shadow = (unsigned long)
6687 le64_to_cpu(dd->pioavailregs_dma[i]);
6688 previ = i;
6689 }
6690 if (test_bit(((2 * cstart) +
6691 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6692 % BITS_PER_LONG, &shadow))
6693 break;
6694 }
6695
6696 if (cstart > last)
6697 break;
6698
6699 if (sleeps == QTXSLEEPS)
6700 break;
6701
6702 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6703 sleeps++;
6704 msleep(20);
6705 }
6706
6707 switch (which) {
6708 case TXCHK_CHG_TYPE_DIS1:
6709
6710
6711
6712
6713 for (i = start; i <= last; i++)
6714 clear_bit(i, dd->cspec->sendchkenable);
6715 break;
6716
6717 case TXCHK_CHG_TYPE_ENAB1:
6718
6719
6720
6721
6722
6723
6724 qib_read_kreg32(dd, kr_scratch);
6725 for (i = start; i <= last; i++)
6726 set_bit(i, dd->cspec->sendchkenable);
6727 break;
6728
6729 case TXCHK_CHG_TYPE_KERN:
6730
6731 for (i = start; i <= last; i++) {
6732 set_bit(i, dd->cspec->sendibchk);
6733 clear_bit(i, dd->cspec->sendgrhchk);
6734 }
6735 spin_lock_irqsave(&dd->uctxt_lock, flags);
6736
6737 for (i = dd->first_user_ctxt;
6738 dd->cspec->updthresh != dd->cspec->updthresh_dflt
6739 && i < dd->cfgctxts; i++)
6740 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
6741 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
6742 < dd->cspec->updthresh_dflt)
6743 break;
6744 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
6745 if (i == dd->cfgctxts) {
6746 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6747 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
6748 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6749 dd->sendctrl |= (dd->cspec->updthresh &
6750 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
6751 SYM_LSB(SendCtrl, AvailUpdThld);
6752 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6753 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6754 }
6755 break;
6756
6757 case TXCHK_CHG_TYPE_USER:
6758
6759 for (i = start; i <= last; i++) {
6760 clear_bit(i, dd->cspec->sendibchk);
6761 set_bit(i, dd->cspec->sendgrhchk);
6762 }
6763 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6764 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
6765 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
6766 dd->cspec->updthresh = (rcd->piocnt /
6767 rcd->subctxt_cnt) - 1;
6768 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6769 dd->sendctrl |= (dd->cspec->updthresh &
6770 SYM_RMASK(SendCtrl, AvailUpdThld))
6771 << SYM_LSB(SendCtrl, AvailUpdThld);
6772 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6773 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6774 } else
6775 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6776 break;
6777
6778 default:
6779 break;
6780 }
6781
6782 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
6783 qib_write_kreg(dd, kr_sendcheckmask + i,
6784 dd->cspec->sendchkenable[i]);
6785
6786 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
6787 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
6788 dd->cspec->sendgrhchk[i]);
6789 qib_write_kreg(dd, kr_sendibpktmask + i,
6790 dd->cspec->sendibchk[i]);
6791 }
6792
6793
6794
6795
6796
6797 qib_read_kreg32(dd, kr_scratch);
6798}
6799
6800
6801
6802static void writescratch(struct qib_devdata *dd, u32 val)
6803{
6804 qib_write_kreg(dd, kr_scratch, val);
6805}
6806
6807
6808static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
6809{
6810 return -ENXIO;
6811}
6812
6813
6814
6815
6816
6817
6818
6819
6820
6821
6822
6823
6824struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
6825 const struct pci_device_id *ent)
6826{
6827 struct qib_devdata *dd;
6828 int ret, i;
6829 u32 tabsize, actual_cnt = 0;
6830
6831 dd = qib_alloc_devdata(pdev,
6832 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
6833 sizeof(struct qib_chip_specific) +
6834 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
6835 if (IS_ERR(dd))
6836 goto bail;
6837
6838 dd->f_bringup_serdes = qib_7322_bringup_serdes;
6839 dd->f_cleanup = qib_setup_7322_cleanup;
6840 dd->f_clear_tids = qib_7322_clear_tids;
6841 dd->f_free_irq = qib_7322_free_irq;
6842 dd->f_get_base_info = qib_7322_get_base_info;
6843 dd->f_get_msgheader = qib_7322_get_msgheader;
6844 dd->f_getsendbuf = qib_7322_getsendbuf;
6845 dd->f_gpio_mod = gpio_7322_mod;
6846 dd->f_eeprom_wen = qib_7322_eeprom_wen;
6847 dd->f_hdrqempty = qib_7322_hdrqempty;
6848 dd->f_ib_updown = qib_7322_ib_updown;
6849 dd->f_init_ctxt = qib_7322_init_ctxt;
6850 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
6851 dd->f_intr_fallback = qib_7322_intr_fallback;
6852 dd->f_late_initreg = qib_late_7322_initreg;
6853 dd->f_setpbc_control = qib_7322_setpbc_control;
6854 dd->f_portcntr = qib_portcntr_7322;
6855 dd->f_put_tid = qib_7322_put_tid;
6856 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
6857 dd->f_rcvctrl = rcvctrl_7322_mod;
6858 dd->f_read_cntrs = qib_read_7322cntrs;
6859 dd->f_read_portcntrs = qib_read_7322portcntrs;
6860 dd->f_reset = qib_do_7322_reset;
6861 dd->f_init_sdma_regs = init_sdma_7322_regs;
6862 dd->f_sdma_busy = qib_sdma_7322_busy;
6863 dd->f_sdma_gethead = qib_sdma_7322_gethead;
6864 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
6865 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
6866 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
6867 dd->f_sendctrl = sendctrl_7322_mod;
6868 dd->f_set_armlaunch = qib_set_7322_armlaunch;
6869 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
6870 dd->f_iblink_state = qib_7322_iblink_state;
6871 dd->f_ibphys_portstate = qib_7322_phys_portstate;
6872 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
6873 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
6874 dd->f_set_ib_loopback = qib_7322_set_loopback;
6875 dd->f_get_ib_table = qib_7322_get_ib_table;
6876 dd->f_set_ib_table = qib_7322_set_ib_table;
6877 dd->f_set_intr_state = qib_7322_set_intr_state;
6878 dd->f_setextled = qib_setup_7322_setextled;
6879 dd->f_txchk_change = qib_7322_txchk_change;
6880 dd->f_update_usrhead = qib_update_7322_usrhead;
6881 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
6882 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
6883 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
6884 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
6885 dd->f_sdma_init_early = qib_7322_sdma_init_early;
6886 dd->f_writescratch = writescratch;
6887 dd->f_tempsense_rd = qib_7322_tempsense_rd;
6888
6889
6890
6891
6892
6893
6894 ret = qib_pcie_ddinit(dd, pdev, ent);
6895 if (ret < 0)
6896 goto bail_free;
6897
6898
6899 ret = qib_init_7322_variables(dd);
6900 if (ret)
6901 goto bail_cleanup;
6902
6903 if (qib_mini_init || !dd->num_pports)
6904 goto bail;
6905
6906
6907
6908
6909
6910
6911
6912 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
6913 for (i = 0; i < tabsize; i++)
6914 if ((i < ARRAY_SIZE(irq_table) &&
6915 irq_table[i].port <= dd->num_pports) ||
6916 (i >= ARRAY_SIZE(irq_table) &&
6917 dd->rcd[i - ARRAY_SIZE(irq_table)]))
6918 actual_cnt++;
6919
6920 if (qib_krcvq01_no_msi)
6921 actual_cnt -= dd->num_pports;
6922
6923 tabsize = actual_cnt;
6924 dd->cspec->msix_entries = kmalloc(tabsize *
6925 sizeof(struct qib_msix_entry), GFP_KERNEL);
6926 if (!dd->cspec->msix_entries) {
6927 qib_dev_err(dd, "No memory for MSIx table\n");
6928 tabsize = 0;
6929 }
6930 for (i = 0; i < tabsize; i++)
6931 dd->cspec->msix_entries[i].msix.entry = i;
6932
6933 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
6934 qib_dev_err(dd,
6935 "Failed to setup PCIe or interrupts; continuing anyway\n");
6936
6937 dd->cspec->num_msix_entries = tabsize;
6938
6939
6940 qib_setup_7322_interrupt(dd, 1);
6941
6942
6943 qib_write_kreg(dd, kr_hwdiagctrl, 0);
6944
6945 goto bail;
6946
6947bail_cleanup:
6948 qib_pcie_ddcleanup(dd);
6949bail_free:
6950 qib_free_devdata(dd);
6951 dd = ERR_PTR(ret);
6952bail:
6953 return dd;
6954}
6955
6956
6957
6958
6959
6960
6961
6962
6963#define DDS_ENT_AMP_LSB 14
6964#define DDS_ENT_MAIN_LSB 9
6965#define DDS_ENT_POST_LSB 5
6966#define DDS_ENT_PRE_XTRA_LSB 3
6967#define DDS_ENT_PRE_LSB 0
6968
6969
6970
6971
6972
6973
6974static void set_txdds(struct qib_pportdata *ppd, int ridx,
6975 const struct txdds_ent *tp)
6976{
6977 struct qib_devdata *dd = ppd->dd;
6978 u32 pack_ent;
6979 int regidx;
6980
6981
6982 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
6983
6984
6985
6986
6987
6988 if (ppd->hw_pidx)
6989 regidx += (dd->palign / sizeof(u64));
6990
6991 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
6992 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
6993 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
6994 pack_ent |= tp->post << DDS_ENT_POST_LSB;
6995 qib_write_kreg(dd, regidx, pack_ent);
6996
6997 qib_write_kreg(ppd->dd, kr_scratch, 0);
6998}
6999
7000static const struct vendor_txdds_ent vendor_txdds[] = {
7001 {
7002 { 0x41, 0x50, 0x48 }, "584470002 ",
7003 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
7004 },
7005 {
7006 { 0x41, 0x50, 0x48 }, "584470004 ",
7007 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
7008 },
7009 {
7010 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
7011 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
7012 },
7013 {
7014 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
7015 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
7016 },
7017 {
7018 { 0x00, 0x90, 0x65 }, NULL,
7019 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
7020 },
7021 {
7022 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
7023 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
7024 },
7025 {
7026 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
7027 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
7028 },
7029 {
7030 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
7031 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
7032 },
7033 {
7034 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
7035 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
7036 },
7037 {
7038 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
7039 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
7040 },
7041 {
7042 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
7043 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
7044 },
7045 {
7046 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
7047 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
7048 },
7049 {
7050 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
7051 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
7052 },
7053 {
7054 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
7055 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
7056 },
7057 {
7058 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
7059 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
7060 },
7061 {
7062 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
7063 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
7064 },
7065 {
7066 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
7067 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
7068 },
7069 {
7070 { 0x00, 0x30, 0xB4 }, NULL,
7071 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
7072 },
7073 {
7074 { 0x00, 0x25, 0x63 }, NULL,
7075 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
7076 },
7077 {
7078 { 0x00, 0x09, 0x3A }, "74763-0025 ",
7079 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
7080 },
7081 {
7082 { 0x00, 0x09, 0x3A }, "74757-2201 ",
7083 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
7084 },
7085};
7086
7087static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
7088
7089 { 2, 2, 15, 6 },
7090 { 0, 0, 0, 1 },
7091 { 0, 0, 0, 2 },
7092 { 0, 0, 0, 3 },
7093 { 0, 0, 0, 4 },
7094 { 0, 0, 0, 5 },
7095 { 0, 0, 0, 6 },
7096 { 0, 0, 0, 7 },
7097 { 0, 0, 0, 8 },
7098 { 0, 0, 0, 9 },
7099 { 0, 0, 0, 10 },
7100 { 0, 0, 0, 11 },
7101 { 0, 0, 0, 12 },
7102 { 0, 0, 0, 13 },
7103 { 0, 0, 0, 14 },
7104 { 0, 0, 0, 15 },
7105};
7106
7107static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
7108
7109 { 2, 2, 15, 6 },
7110 { 0, 0, 0, 8 },
7111 { 0, 0, 0, 8 },
7112 { 0, 0, 0, 9 },
7113 { 0, 0, 0, 9 },
7114 { 0, 0, 0, 10 },
7115 { 0, 0, 0, 10 },
7116 { 0, 0, 0, 11 },
7117 { 0, 0, 0, 11 },
7118 { 0, 0, 0, 12 },
7119 { 0, 0, 0, 12 },
7120 { 0, 0, 0, 13 },
7121 { 0, 0, 0, 13 },
7122 { 0, 0, 0, 14 },
7123 { 0, 0, 0, 14 },
7124 { 0, 0, 0, 15 },
7125};
7126
7127static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
7128
7129 { 2, 2, 15, 6 },
7130 { 0, 1, 0, 7 },
7131 { 0, 1, 0, 9 },
7132 { 0, 1, 0, 11 },
7133 { 0, 1, 0, 13 },
7134 { 0, 1, 0, 15 },
7135 { 0, 1, 3, 15 },
7136 { 0, 1, 7, 15 },
7137 { 0, 1, 7, 15 },
7138 { 0, 1, 8, 15 },
7139 { 0, 1, 9, 15 },
7140 { 0, 1, 10, 15 },
7141 { 0, 2, 6, 15 },
7142 { 0, 2, 7, 15 },
7143 { 0, 2, 8, 15 },
7144 { 0, 2, 9, 15 },
7145};
7146
7147
7148
7149
7150
7151
7152
7153static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
7154
7155 { 0, 0, 0, 1 },
7156 { 0, 0, 0, 1 },
7157 { 0, 0, 0, 2 },
7158 { 0, 0, 0, 2 },
7159 { 0, 0, 0, 11 },
7160 { 0, 0, 0, 11 },
7161 { 0, 0, 0, 11 },
7162 { 0, 0, 0, 11 },
7163 { 0, 0, 0, 11 },
7164 { 0, 0, 0, 11 },
7165 { 0, 0, 0, 11 },
7166 { 0, 0, 0, 3 },
7167 { 0, 0, 0, 4 },
7168};
7169
7170static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
7171
7172 { 0, 0, 0, 7 },
7173 { 0, 0, 0, 7 },
7174 { 0, 0, 0, 8 },
7175 { 0, 0, 0, 8 },
7176 { 0, 0, 0, 13 },
7177 { 0, 0, 0, 13 },
7178 { 0, 0, 0, 13 },
7179 { 0, 0, 0, 13 },
7180 { 0, 0, 0, 13 },
7181 { 0, 0, 0, 13 },
7182 { 0, 0, 0, 13 },
7183 { 0, 0, 0, 9 },
7184 { 0, 0, 0, 10 },
7185};
7186
7187static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7188
7189 { 0, 1, 0, 4 },
7190 { 0, 1, 0, 5 },
7191 { 0, 1, 0, 6 },
7192 { 0, 1, 0, 8 },
7193 { 0, 1, 12, 10 },
7194 { 0, 1, 12, 11 },
7195 { 0, 1, 12, 12 },
7196 { 0, 1, 12, 14 },
7197 { 0, 1, 12, 6 },
7198 { 0, 1, 12, 7 },
7199 { 0, 1, 12, 8 },
7200 { 0, 1, 0, 10 },
7201 { 0, 1, 0, 12 },
7202};
7203
7204static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = {
7205
7206 { 0, 0, 0, 0 },
7207 { 0, 0, 0, 6 },
7208};
7209
7210static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7211 unsigned atten)
7212{
7213
7214
7215
7216
7217 if (atten <= 2)
7218 atten = 1;
7219 else if (atten > TXDDS_TABLE_SZ)
7220 atten = TXDDS_TABLE_SZ - 1;
7221 else
7222 atten--;
7223 return txdds + atten;
7224}
7225
7226
7227
7228
7229
7230static void find_best_ent(struct qib_pportdata *ppd,
7231 const struct txdds_ent **sdr_dds,
7232 const struct txdds_ent **ddr_dds,
7233 const struct txdds_ent **qdr_dds, int override)
7234{
7235 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7236 int idx;
7237
7238
7239 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7240 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7241
7242 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7243 (!v->partnum ||
7244 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7245 *sdr_dds = &v->sdr;
7246 *ddr_dds = &v->ddr;
7247 *qdr_dds = &v->qdr;
7248 return;
7249 }
7250 }
7251
7252
7253
7254 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7255 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7256 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7257 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7258 return;
7259 }
7260
7261 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7262 qd->atten[1])) {
7263 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7264 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7265 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7266 return;
7267 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
7268
7269
7270
7271
7272
7273
7274 idx = ppd->cpspec->no_eep;
7275 *sdr_dds = &txdds_sdr[idx];
7276 *ddr_dds = &txdds_ddr[idx];
7277 *qdr_dds = &txdds_qdr[idx];
7278 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7279
7280 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7281 *sdr_dds = &txdds_extra_sdr[idx];
7282 *ddr_dds = &txdds_extra_ddr[idx];
7283 *qdr_dds = &txdds_extra_qdr[idx];
7284 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) &&
7285 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
7286 TXDDS_MFG_SZ)) {
7287 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
7288 pr_info("IB%u:%u use idx %u into txdds_mfg\n",
7289 ppd->dd->unit, ppd->port, idx);
7290 *sdr_dds = &txdds_extra_mfg[idx];
7291 *ddr_dds = &txdds_extra_mfg[idx];
7292 *qdr_dds = &txdds_extra_mfg[idx];
7293 } else {
7294
7295 *sdr_dds = txdds_sdr + qib_long_atten;
7296 *ddr_dds = txdds_ddr + qib_long_atten;
7297 *qdr_dds = txdds_qdr + qib_long_atten;
7298 }
7299}
7300
7301static void init_txdds_table(struct qib_pportdata *ppd, int override)
7302{
7303 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7304 struct txdds_ent *dds;
7305 int idx;
7306 int single_ent = 0;
7307
7308 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7309
7310
7311 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
7312 single_ent = 1;
7313
7314
7315 set_txdds(ppd, 0, sdr_dds);
7316 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7317 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
7318 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7319 QIBL_LINKACTIVE)) {
7320 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7321 QIB_IB_QDR ? qdr_dds :
7322 (ppd->link_speed_active ==
7323 QIB_IB_DDR ? ddr_dds : sdr_dds));
7324 write_tx_serdes_param(ppd, dds);
7325 }
7326
7327
7328 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7329 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7330 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7331 single_ent ? ddr_dds : txdds_ddr + idx);
7332 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7333 single_ent ? qdr_dds : txdds_qdr + idx);
7334 }
7335}
7336
7337#define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7338#define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7339#define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7340#define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7341#define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7342#define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7343#define AHB_TRANS_TRIES 10
7344
7345
7346
7347
7348
7349
7350static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7351 u32 data, u32 mask)
7352{
7353 u32 rd_data, wr_data, sz_mask;
7354 u64 trans, acc, prev_acc;
7355 u32 ret = 0xBAD0BAD;
7356 int tries;
7357
7358 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7359
7360 acc = (quad << 1) | 1;
7361 qib_write_kreg(dd, KR_AHB_ACC, acc);
7362
7363 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7364 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7365 if (trans & AHB_TRANS_RDY)
7366 break;
7367 }
7368 if (tries >= AHB_TRANS_TRIES) {
7369 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7370 goto bail;
7371 }
7372
7373
7374
7375
7376 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7377 wr_data = data & mask & sz_mask;
7378 if ((~mask & sz_mask) != 0) {
7379 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7380 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7381
7382 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7383 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7384 if (trans & AHB_TRANS_RDY)
7385 break;
7386 }
7387 if (tries >= AHB_TRANS_TRIES) {
7388 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7389 AHB_TRANS_TRIES);
7390 goto bail;
7391 }
7392
7393 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7394 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7395 wr_data |= (rd_data & ~mask & sz_mask);
7396 }
7397
7398
7399 if (mask & sz_mask) {
7400 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7401 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7402 trans |= AHB_WR;
7403 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7404
7405 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7406 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7407 if (trans & AHB_TRANS_RDY)
7408 break;
7409 }
7410 if (tries >= AHB_TRANS_TRIES) {
7411 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7412 AHB_TRANS_TRIES);
7413 goto bail;
7414 }
7415 }
7416 ret = wr_data;
7417bail:
7418 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7419 return ret;
7420}
7421
7422static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7423 unsigned mask)
7424{
7425 struct qib_devdata *dd = ppd->dd;
7426 int chan;
7427 u32 rbc;
7428
7429 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7430 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7431 data, mask);
7432 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7433 addr, 0, 0);
7434 }
7435}
7436
7437static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
7438{
7439 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
7440 u8 state = SYM_FIELD(data, IBSerdesCtrl_0, RXLOSEN);
7441
7442 if (enable && !state) {
7443 pr_info("IB%u:%u Turning LOS on\n",
7444 ppd->dd->unit, ppd->port);
7445 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7446 } else if (!enable && state) {
7447 pr_info("IB%u:%u Turning LOS off\n",
7448 ppd->dd->unit, ppd->port);
7449 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7450 }
7451 qib_write_kreg_port(ppd, krp_serdesctrl, data);
7452}
7453
7454static int serdes_7322_init(struct qib_pportdata *ppd)
7455{
7456 int ret = 0;
7457 if (ppd->dd->cspec->r1)
7458 ret = serdes_7322_init_old(ppd);
7459 else
7460 ret = serdes_7322_init_new(ppd);
7461 return ret;
7462}
7463
7464static int serdes_7322_init_old(struct qib_pportdata *ppd)
7465{
7466 u32 le_val;
7467
7468
7469
7470
7471
7472 init_txdds_table(ppd, 0);
7473
7474
7475 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7476 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7477 reset_tx_deemphasis_override));
7478
7479
7480
7481 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7482
7483
7484 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7485
7486 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7487
7488
7489 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7490 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7491
7492
7493 le_val = IS_QME(ppd->dd) ? 0 : 1;
7494 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7495
7496
7497 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7498
7499
7500 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7501
7502
7503
7504 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7505 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7506 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7507 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7508
7509
7510 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7511 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7512 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7513 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7514
7515
7516 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7517
7518
7519 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3));
7520 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10));
7521 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13));
7522
7523 serdes_7322_los_enable(ppd, 1);
7524
7525
7526 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7527
7528
7529 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7530
7531
7532 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7533 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7534
7535
7536
7537
7538
7539 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7540 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7541 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7542 ppd->dd->cspec->r1 ?
7543 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7544 ppd->cpspec->qdr_dfe_on = 1;
7545
7546
7547 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7548
7549
7550 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
7551
7552 if (!ppd->dd->cspec->r1) {
7553 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
7554 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
7555 }
7556
7557
7558 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
7559
7560 return 0;
7561}
7562
7563static int serdes_7322_init_new(struct qib_pportdata *ppd)
7564{
7565 unsigned long tend;
7566 u32 le_val, rxcaldone;
7567 int chan, chan_done = (1 << SERDES_CHANS) - 1;
7568
7569
7570 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7571
7572
7573 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7574 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7575 reset_tx_deemphasis_override));
7576
7577
7578
7579
7580 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
7581
7582 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
7583
7584 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
7585
7586 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
7587
7588 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7589
7590 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
7591
7592 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
7593
7594 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
7595
7596 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
7597
7598 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7599
7600 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
7601
7602 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
7603
7604 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
7605
7606 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
7607
7608 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
7609
7610 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
7611
7612 if (!ppd->dd->cspec->r1) {
7613 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
7614 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
7615 } else {
7616 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
7617 }
7618
7619
7620
7621
7622
7623
7624
7625
7626
7627 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
7628 msleep(20);
7629
7630 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
7631 msleep(20);
7632
7633 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
7634 msleep(20);
7635
7636
7637
7638 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7639 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7640 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7641 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7642
7643
7644 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7645 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7646 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7647 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7648
7649
7650 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7651
7652
7653 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3));
7654 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10));
7655 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13));
7656
7657
7658 serdes_7322_los_enable(ppd, 1);
7659
7660 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7661
7662
7663
7664 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
7665
7666 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
7667 msleep(20);
7668
7669 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
7670 tend = jiffies + msecs_to_jiffies(500);
7671 while (chan_done && !time_is_before_jiffies(tend)) {
7672 msleep(20);
7673 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7674 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7675 (chan + (chan >> 1)),
7676 25, 0, 0);
7677 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
7678 (~chan_done & (1 << chan)) == 0)
7679 chan_done &= ~(1 << chan);
7680 }
7681 }
7682 if (chan_done) {
7683 pr_info("Serdes %d calibration not done after .5 sec: 0x%x\n",
7684 IBSD(ppd->hw_pidx), chan_done);
7685 } else {
7686 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7687 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7688 (chan + (chan >> 1)),
7689 25, 0, 0);
7690 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
7691 pr_info("Serdes %d chan %d calibration failed\n",
7692 IBSD(ppd->hw_pidx), chan);
7693 }
7694 }
7695
7696
7697 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7698 msleep(20);
7699
7700
7701
7702 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7703 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7704
7705 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
7706
7707 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
7708 msleep(20);
7709
7710 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
7711
7712 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7713 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7714
7715 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7716 msleep(20);
7717
7718 ibsd_wr_allchans(ppd, 2, (15 << 5), BMASK(8, 5));
7719
7720 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
7721
7722 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7723
7724 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
7725 msleep(50);
7726
7727
7728
7729
7730 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7731 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7732 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7733 ppd->dd->cspec->r1 ?
7734 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7735 ppd->cpspec->qdr_dfe_on = 1;
7736
7737 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
7738
7739 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
7740 msleep(20);
7741
7742 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
7743
7744 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
7745
7746 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7747
7748 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
7749
7750
7751
7752
7753
7754 init_txdds_table(ppd, 0);
7755
7756 return 0;
7757}
7758
7759
7760
7761static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
7762{
7763 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7764 9, code << 9, 0x3f << 9);
7765}
7766
7767static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
7768 int enable, u32 tapenable)
7769{
7770 if (enable)
7771 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7772 1, 3 << 10, 0x1f << 10);
7773 else
7774 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7775 1, 0, 0x1f << 10);
7776}
7777
7778
7779static void clock_man(struct qib_pportdata *ppd, int chan)
7780{
7781 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7782 4, 0x4000, 0x4000);
7783 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7784 4, 0, 0x4000);
7785 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7786 4, 0x4000, 0x4000);
7787 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7788 4, 0, 0x4000);
7789}
7790
7791
7792
7793
7794
7795
7796static void write_tx_serdes_param(struct qib_pportdata *ppd,
7797 struct txdds_ent *txdds)
7798{
7799 u64 deemph;
7800
7801 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
7802
7803 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
7804 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
7805 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
7806 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
7807
7808 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7809 tx_override_deemphasis_select);
7810 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7811 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7812 txampcntl_d2a);
7813 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7814 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7815 txc0_ena);
7816 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7817 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7818 txcp1_ena);
7819 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7820 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7821 txcn1_ena);
7822 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
7823}
7824
7825
7826
7827
7828
7829
7830static void adj_tx_serdes(struct qib_pportdata *ppd)
7831{
7832 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7833 struct txdds_ent *dds;
7834
7835 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
7836 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
7837 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
7838 ddr_dds : sdr_dds));
7839 write_tx_serdes_param(ppd, dds);
7840}
7841
7842
7843static void force_h1(struct qib_pportdata *ppd)
7844{
7845 int chan;
7846
7847 ppd->cpspec->qdr_reforce = 0;
7848 if (!ppd->dd->cspec->r1)
7849 return;
7850
7851 for (chan = 0; chan < SERDES_CHANS; chan++) {
7852 set_man_mode_h1(ppd, chan, 1, 0);
7853 set_man_code(ppd, chan, ppd->cpspec->h1_val);
7854 clock_man(ppd, chan);
7855 set_man_mode_h1(ppd, chan, 0, 0);
7856 }
7857}
7858
7859#define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
7860#define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
7861
7862#define R_OPCODE_LSB 3
7863#define R_OP_NOP 0
7864#define R_OP_SHIFT 2
7865#define R_OP_UPDATE 3
7866#define R_TDI_LSB 2
7867#define R_TDO_LSB 1
7868#define R_RDY 1
7869
7870static int qib_r_grab(struct qib_devdata *dd)
7871{
7872 u64 val;
7873 val = SJA_EN;
7874 qib_write_kreg(dd, kr_r_access, val);
7875 qib_read_kreg32(dd, kr_scratch);
7876 return 0;
7877}
7878
7879
7880
7881
7882static int qib_r_wait_for_rdy(struct qib_devdata *dd)
7883{
7884 u64 val;
7885 int timeout;
7886 for (timeout = 0; timeout < 100 ; ++timeout) {
7887 val = qib_read_kreg32(dd, kr_r_access);
7888 if (val & R_RDY)
7889 return (val >> R_TDO_LSB) & 1;
7890 }
7891 return -1;
7892}
7893
7894static int qib_r_shift(struct qib_devdata *dd, int bisten,
7895 int len, u8 *inp, u8 *outp)
7896{
7897 u64 valbase, val;
7898 int ret, pos;
7899
7900 valbase = SJA_EN | (bisten << BISTEN_LSB) |
7901 (R_OP_SHIFT << R_OPCODE_LSB);
7902 ret = qib_r_wait_for_rdy(dd);
7903 if (ret < 0)
7904 goto bail;
7905 for (pos = 0; pos < len; ++pos) {
7906 val = valbase;
7907 if (outp) {
7908 outp[pos >> 3] &= ~(1 << (pos & 7));
7909 outp[pos >> 3] |= (ret << (pos & 7));
7910 }
7911 if (inp) {
7912 int tdi = inp[pos >> 3] >> (pos & 7);
7913 val |= ((tdi & 1) << R_TDI_LSB);
7914 }
7915 qib_write_kreg(dd, kr_r_access, val);
7916 qib_read_kreg32(dd, kr_scratch);
7917 ret = qib_r_wait_for_rdy(dd);
7918 if (ret < 0)
7919 break;
7920 }
7921
7922 val = SJA_EN | (bisten << BISTEN_LSB);
7923 qib_write_kreg(dd, kr_r_access, val);
7924 qib_read_kreg32(dd, kr_scratch);
7925 ret = qib_r_wait_for_rdy(dd);
7926
7927 if (ret >= 0)
7928 ret = pos;
7929bail:
7930 return ret;
7931}
7932
7933static int qib_r_update(struct qib_devdata *dd, int bisten)
7934{
7935 u64 val;
7936 int ret;
7937
7938 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
7939 ret = qib_r_wait_for_rdy(dd);
7940 if (ret >= 0) {
7941 qib_write_kreg(dd, kr_r_access, val);
7942 qib_read_kreg32(dd, kr_scratch);
7943 }
7944 return ret;
7945}
7946
7947#define BISTEN_PORT_SEL 15
7948#define LEN_PORT_SEL 625
7949#define BISTEN_AT 17
7950#define LEN_AT 156
7951#define BISTEN_ETM 16
7952#define LEN_ETM 632
7953
7954#define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
7955
7956
7957static u8 reset_at[BIT2BYTE(LEN_AT)] = {
7958 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7959 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7960};
7961static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
7962 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7963 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7964 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
7965 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
7966 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
7967 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
7968 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7969 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
7970};
7971static u8 at[BIT2BYTE(LEN_AT)] = {
7972 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
7973 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7974};
7975
7976
7977static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
7978 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7979 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7980 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7981 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
7982 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7983 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
7984 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
7985 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
7986};
7987
7988
7989static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
7990 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7991 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
7992 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7993 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
7994 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
7995 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
7996 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
7997 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
7998};
7999
8000
8001static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
8002 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
8003 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
8004 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8005 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8006 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
8007 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8008 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8009 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8010};
8011
8012
8013static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
8014 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
8015 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
8016 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
8017 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
8018 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
8019 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
8020 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
8021 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
8022};
8023
8024
8025static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
8026 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
8027 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
8028 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8029 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8030 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
8031 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
8032 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8033 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8034};
8035
8036
8037
8038
8039
8040
8041
8042static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
8043{
8044 u8 *portsel, *etm;
8045 struct qib_devdata *dd = ppd->dd;
8046
8047 if (!ppd->dd->cspec->r1)
8048 return;
8049 if (!both) {
8050 dd->cspec->recovery_ports_initted++;
8051 ppd->cpspec->recovery_init = 1;
8052 }
8053 if (!both && dd->cspec->recovery_ports_initted == 1) {
8054 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
8055 etm = atetm_1port;
8056 } else {
8057 portsel = portsel_2port;
8058 etm = atetm_2port;
8059 }
8060
8061 if (qib_r_grab(dd) < 0 ||
8062 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
8063 qib_r_update(dd, BISTEN_ETM) < 0 ||
8064 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
8065 qib_r_update(dd, BISTEN_AT) < 0 ||
8066 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
8067 portsel, NULL) < 0 ||
8068 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
8069 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
8070 qib_r_update(dd, BISTEN_AT) < 0 ||
8071 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
8072 qib_r_update(dd, BISTEN_ETM) < 0)
8073 qib_dev_err(dd, "Failed IB link recovery setup\n");
8074}
8075
8076static void check_7322_rxe_status(struct qib_pportdata *ppd)
8077{
8078 struct qib_devdata *dd = ppd->dd;
8079 u64 fmask;
8080
8081 if (dd->cspec->recovery_ports_initted != 1)
8082 return;
8083 qib_write_kreg(dd, kr_control, dd->control |
8084 SYM_MASK(Control, FreezeMode));
8085 (void)qib_read_kreg64(dd, kr_scratch);
8086 udelay(3);
8087 fmask = qib_read_kreg64(dd, kr_act_fmask);
8088 if (!fmask) {
8089
8090
8091
8092
8093
8094 ppd->dd->cspec->stay_in_freeze = 1;
8095 qib_7322_set_intr_state(ppd->dd, 0);
8096 qib_write_kreg(dd, kr_fmask, 0ULL);
8097 qib_dev_err(dd, "HCA unusable until powercycled\n");
8098 return;
8099 }
8100
8101 qib_write_kreg(ppd->dd, kr_hwerrclear,
8102 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
8103
8104
8105 qib_write_kreg(dd, kr_control, dd->control);
8106 qib_read_kreg32(dd, kr_scratch);
8107
8108 if (ppd->link_speed_supported) {
8109 ppd->cpspec->ibcctrl_a &=
8110 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
8111 qib_write_kreg_port(ppd, krp_ibcctrl_a,
8112 ppd->cpspec->ibcctrl_a);
8113 qib_read_kreg32(dd, kr_scratch);
8114 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
8115 qib_set_ib_7322_lstate(ppd, 0,
8116 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
8117 }
8118}
8119