LXR linux/drivers/media/dvb-frontends/au8522

   1/*
   2 * Auvitek AU8522 QAM/8VSB demodulator driver and video decoder
   3 *
   4 * Copyright (C) 2009 Devin Heitmueller <dheitmueller@linuxtv.org>
   5 * Copyright (C) 2005-2008 Auvitek International, Ltd.
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License
   9 * As published by the Free Software Foundation; either version 2
  10 * of the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20 * 02110-1301, USA.
  21 */
  22
  23/* Developer notes:
  24 *
  25 * VBI support is not yet working
  26 * Enough is implemented here for CVBS and S-Video inputs, but the actual
  27 *  analog demodulator code isn't implemented (not needed for xc5000 since it
  28 *  has its own demodulator and outputs CVBS)
  29 *
  30 */
  31
  32#include <linux/kernel.h>
  33#include <linux/slab.h>
  34#include <linux/videodev2.h>
  35#include <linux/i2c.h>
  36#include <linux/delay.h>
  37#include <media/v4l2-common.h>
  38#include <media/v4l2-chip-ident.h>
  39#include <media/v4l2-device.h>
  40#include "au8522.h"
  41#include "au8522_priv.h"
  42
  43MODULE_AUTHOR("Devin Heitmueller");
  44MODULE_LICENSE("GPL");
  45
  46static int au8522_analog_debug;
  47
  48
  49module_param_named(analog_debug, au8522_analog_debug, int, 0644);
  50
  51MODULE_PARM_DESC(analog_debug,
  52                 "Analog debugging messages [0=Off (default) 1=On]");
  53
  54struct au8522_register_config {
  55        u16 reg_name;
  56        u8 reg_val[8];
  57};
  58
  59
  60/* Video Decoder Filter Coefficients
  61   The values are as follows from left to right
  62   0="ATV RF" 1="ATV RF13" 2="CVBS" 3="S-Video" 4="PAL" 5=CVBS13" 6="SVideo13"
  63*/
  64static const struct au8522_register_config filter_coef[] = {
  65        {AU8522_FILTER_COEF_R410, {0x25, 0x00, 0x25, 0x25, 0x00, 0x00, 0x00} },
  66        {AU8522_FILTER_COEF_R411, {0x20, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00} },
  67        {AU8522_FILTER_COEF_R412, {0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00} },
  68        {AU8522_FILTER_COEF_R413, {0xe6, 0x00, 0xe6, 0xe6, 0x00, 0x00, 0x00} },
  69        {AU8522_FILTER_COEF_R414, {0x40, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00} },
  70        {AU8522_FILTER_COEF_R415, {0x1b, 0x00, 0x1b, 0x1b, 0x00, 0x00, 0x00} },
  71        {AU8522_FILTER_COEF_R416, {0xc0, 0x00, 0xc0, 0x04, 0x00, 0x00, 0x00} },
  72        {AU8522_FILTER_COEF_R417, {0x04, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00} },
  73        {AU8522_FILTER_COEF_R418, {0x8c, 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x00} },
  74        {AU8522_FILTER_COEF_R419, {0xa0, 0x40, 0xa0, 0xa0, 0x40, 0x40, 0x40} },
  75        {AU8522_FILTER_COEF_R41A, {0x21, 0x09, 0x21, 0x21, 0x09, 0x09, 0x09} },
  76        {AU8522_FILTER_COEF_R41B, {0x6c, 0x38, 0x6c, 0x6c, 0x38, 0x38, 0x38} },
  77        {AU8522_FILTER_COEF_R41C, {0x03, 0xff, 0x03, 0x03, 0xff, 0xff, 0xff} },
  78        {AU8522_FILTER_COEF_R41D, {0xbf, 0xc7, 0xbf, 0xbf, 0xc7, 0xc7, 0xc7} },
  79        {AU8522_FILTER_COEF_R41E, {0xa0, 0xdf, 0xa0, 0xa0, 0xdf, 0xdf, 0xdf} },
  80        {AU8522_FILTER_COEF_R41F, {0x10, 0x06, 0x10, 0x10, 0x06, 0x06, 0x06} },
  81        {AU8522_FILTER_COEF_R420, {0xae, 0x30, 0xae, 0xae, 0x30, 0x30, 0x30} },
  82        {AU8522_FILTER_COEF_R421, {0xc4, 0x01, 0xc4, 0xc4, 0x01, 0x01, 0x01} },
  83        {AU8522_FILTER_COEF_R422, {0x54, 0xdd, 0x54, 0x54, 0xdd, 0xdd, 0xdd} },
  84        {AU8522_FILTER_COEF_R423, {0xd0, 0xaf, 0xd0, 0xd0, 0xaf, 0xaf, 0xaf} },
  85        {AU8522_FILTER_COEF_R424, {0x1c, 0xf7, 0x1c, 0x1c, 0xf7, 0xf7, 0xf7} },
  86        {AU8522_FILTER_COEF_R425, {0x76, 0xdb, 0x76, 0x76, 0xdb, 0xdb, 0xdb} },
  87        {AU8522_FILTER_COEF_R426, {0x61, 0xc0, 0x61, 0x61, 0xc0, 0xc0, 0xc0} },
  88        {AU8522_FILTER_COEF_R427, {0xd1, 0x2f, 0xd1, 0xd1, 0x2f, 0x2f, 0x2f} },
  89        {AU8522_FILTER_COEF_R428, {0x84, 0xd8, 0x84, 0x84, 0xd8, 0xd8, 0xd8} },
  90        {AU8522_FILTER_COEF_R429, {0x06, 0xfb, 0x06, 0x06, 0xfb, 0xfb, 0xfb} },
  91        {AU8522_FILTER_COEF_R42A, {0x21, 0xd5, 0x21, 0x21, 0xd5, 0xd5, 0xd5} },
  92        {AU8522_FILTER_COEF_R42B, {0x0a, 0x3e, 0x0a, 0x0a, 0x3e, 0x3e, 0x3e} },
  93        {AU8522_FILTER_COEF_R42C, {0xe6, 0x15, 0xe6, 0xe6, 0x15, 0x15, 0x15} },
  94        {AU8522_FILTER_COEF_R42D, {0x01, 0x34, 0x01, 0x01, 0x34, 0x34, 0x34} },
  95
  96};
  97#define NUM_FILTER_COEF (sizeof(filter_coef)\
  98                         / sizeof(struct au8522_register_config))
  99
 100
 101/* Registers 0x060b through 0x0652 are the LP Filter coefficients
 102   The values are as follows from left to right
 103   0="SIF" 1="ATVRF/ATVRF13"
 104   Note: the "ATVRF/ATVRF13" mode has never been tested
 105*/
 106static const struct au8522_register_config lpfilter_coef[] = {
 107        {0x060b, {0x21, 0x0b} },
 108        {0x060c, {0xad, 0xad} },
 109        {0x060d, {0x70, 0xf0} },
 110        {0x060e, {0xea, 0xe9} },
 111        {0x060f, {0xdd, 0xdd} },
 112        {0x0610, {0x08, 0x64} },
 113        {0x0611, {0x60, 0x60} },
 114        {0x0612, {0xf8, 0xb2} },
 115        {0x0613, {0x01, 0x02} },
 116        {0x0614, {0xe4, 0xb4} },
 117        {0x0615, {0x19, 0x02} },
 118        {0x0616, {0xae, 0x2e} },
 119        {0x0617, {0xee, 0xc5} },
 120        {0x0618, {0x56, 0x56} },
 121        {0x0619, {0x30, 0x58} },
 122        {0x061a, {0xf9, 0xf8} },
 123        {0x061b, {0x24, 0x64} },
 124        {0x061c, {0x07, 0x07} },
 125        {0x061d, {0x30, 0x30} },
 126        {0x061e, {0xa9, 0xed} },
 127        {0x061f, {0x09, 0x0b} },
 128        {0x0620, {0x42, 0xc2} },
 129        {0x0621, {0x1d, 0x2a} },
 130        {0x0622, {0xd6, 0x56} },
 131        {0x0623, {0x95, 0x8b} },
 132        {0x0624, {0x2b, 0x2b} },
 133        {0x0625, {0x30, 0x24} },
 134        {0x0626, {0x3e, 0x3e} },
 135        {0x0627, {0x62, 0xe2} },
 136        {0x0628, {0xe9, 0xf5} },
 137        {0x0629, {0x99, 0x19} },
 138        {0x062a, {0xd4, 0x11} },
 139        {0x062b, {0x03, 0x04} },
 140        {0x062c, {0xb5, 0x85} },
 141        {0x062d, {0x1e, 0x20} },
 142        {0x062e, {0x2a, 0xea} },
 143        {0x062f, {0xd7, 0xd2} },
 144        {0x0630, {0x15, 0x15} },
 145        {0x0631, {0xa3, 0xa9} },
 146        {0x0632, {0x1f, 0x1f} },
 147        {0x0633, {0xf9, 0xd1} },
 148        {0x0634, {0xc0, 0xc3} },
 149        {0x0635, {0x4d, 0x8d} },
 150        {0x0636, {0x21, 0x31} },
 151        {0x0637, {0x83, 0x83} },
 152        {0x0638, {0x08, 0x8c} },
 153        {0x0639, {0x19, 0x19} },
 154        {0x063a, {0x45, 0xa5} },
 155        {0x063b, {0xef, 0xec} },
 156        {0x063c, {0x8a, 0x8a} },
 157        {0x063d, {0xf4, 0xf6} },
 158        {0x063e, {0x8f, 0x8f} },
 159        {0x063f, {0x44, 0x0c} },
 160        {0x0640, {0xef, 0xf0} },
 161        {0x0641, {0x66, 0x66} },
 162        {0x0642, {0xcc, 0xd2} },
 163        {0x0643, {0x41, 0x41} },
 164        {0x0644, {0x63, 0x93} },
 165        {0x0645, {0x8e, 0x8e} },
 166        {0x0646, {0xa2, 0x42} },
 167        {0x0647, {0x7b, 0x7b} },
 168        {0x0648, {0x04, 0x04} },
 169        {0x0649, {0x00, 0x00} },
 170        {0x064a, {0x40, 0x40} },
 171        {0x064b, {0x8c, 0x98} },
 172        {0x064c, {0x00, 0x00} },
 173        {0x064d, {0x63, 0xc3} },
 174        {0x064e, {0x04, 0x04} },
 175        {0x064f, {0x20, 0x20} },
 176        {0x0650, {0x00, 0x00} },
 177        {0x0651, {0x40, 0x40} },
 178        {0x0652, {0x01, 0x01} },
 179};
 180#define NUM_LPFILTER_COEF (sizeof(lpfilter_coef)\
 181                           / sizeof(struct au8522_register_config))
 182
 183static inline struct au8522_state *to_state(struct v4l2_subdev *sd)
 184{
 185        return container_of(sd, struct au8522_state, sd);
 186}
 187
 188static void setup_vbi(struct au8522_state *state, int aud_input)
 189{
 190        int i;
 191
 192        /* These are set to zero regardless of what mode we're in */
 193        au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H, 0x00);
 194        au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_L_REG018H, 0x00);
 195        au8522_writereg(state, AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H, 0x00);
 196        au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH, 0x00);
 197        au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH, 0x00);
 198        au8522_writereg(state, AU8522_TVDEC_VBI_USER_THRESH1_REG01CH, 0x00);
 199        au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH, 0x00);
 200        au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH, 0x00);
 201        au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H, 0x00);
 202        au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H,
 203                        0x00);
 204        au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H,
 205                        0x00);
 206        au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H,
 207                        0x00);
 208
 209        /* Setup the VBI registers */
 210        for (i = 0x30; i < 0x60; i++)
 211                au8522_writereg(state, i, 0x40);
 212
 213        /* For some reason, every register is 0x40 except register 0x44
 214           (confirmed via the HVR-950q USB capture) */
 215        au8522_writereg(state, 0x44, 0x60);
 216
 217        /* Enable VBI (we always do this regardless of whether the user is
 218           viewing closed caption info) */
 219        au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H,
 220                        AU8522_TVDEC_VBI_CTRL_H_REG017H_CCON);
 221
 222}
 223
 224static void setup_decoder_defaults(struct au8522_state *state, u8 input_mode)
 225{
 226        int i;
 227        int filter_coef_type;
 228
 229        /* Provide reasonable defaults for picture tuning values */
 230        au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
 231        au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
 232        au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
 233        au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
 234        au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
 235        au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
 236        au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
 237
 238        /* Other decoder registers */
 239        au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
 240
 241        if (input_mode == 0x23) {
 242                /* S-Video input mapping */
 243                au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
 244        } else {
 245                /* All other modes (CVBS/ATVRF etc.) */
 246                au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
 247        }
 248
 249        au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
 250                        AU8522_TVDEC_PGA_REG012H_CVBS);
 251        au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
 252                        AU8522_TVDEC_COMB_MODE_REG015H_CVBS);
 253        au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
 254                        AU8522_TVDED_DBG_MODE_REG060H_CVBS);
 255        au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
 256                        AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
 257                        AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
 258                        AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN);
 259        au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
 260                        AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC);
 261        au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
 262                        AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS);
 263        au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
 264                        AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS);
 265        au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
 266                        AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS);
 267        au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
 268                        AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS);
 269        au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
 270                        AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS);
 271        au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
 272                        AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS);
 273        au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
 274                        AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS);
 275        au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
 276                        AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);
 277        au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
 278                        AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);
 279        if (input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 ||
 280            input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24) {
 281                au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
 282                                AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);
 283                au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
 284                                AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);
 285        } else {
 286                au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
 287                                AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
 288                au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
 289                                AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
 290        }
 291        au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
 292                        AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);
 293        au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
 294                        AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS);
 295        au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
 296                        AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS);
 297        au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
 298        au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
 299        au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
 300                        AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS);
 301        au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
 302        au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
 303        au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
 304                        AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS);
 305        au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
 306                        AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS);
 307        au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
 308                        AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS);
 309        au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
 310                        AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS);
 311        au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
 312                        AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS);
 313        au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
 314                        AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS);
 315        au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
 316                        AU8522_TOREGAAGC_REG0E5H_CVBS);
 317        au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
 318
 319        setup_vbi(state, 0);
 320
 321        if (input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 ||
 322            input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24) {
 323                /* Despite what the table says, for the HVR-950q we still need
 324                   to be in CVBS mode for the S-Video input (reason unknown). */
 325                /* filter_coef_type = 3; */
 326                filter_coef_type = 5;
 327        } else {
 328                filter_coef_type = 5;
 329        }
 330
 331        /* Load the Video Decoder Filter Coefficients */
 332        for (i = 0; i < NUM_FILTER_COEF; i++) {
 333                au8522_writereg(state, filter_coef[i].reg_name,
 334                                filter_coef[i].reg_val[filter_coef_type]);
 335        }
 336
 337        /* It's not clear what these registers are for, but they are always
 338           set to the same value regardless of what mode we're in */
 339        au8522_writereg(state, AU8522_REG42EH, 0x87);
 340        au8522_writereg(state, AU8522_REG42FH, 0xa2);
 341        au8522_writereg(state, AU8522_REG430H, 0xbf);
 342        au8522_writereg(state, AU8522_REG431H, 0xcb);
 343        au8522_writereg(state, AU8522_REG432H, 0xa1);
 344        au8522_writereg(state, AU8522_REG433H, 0x41);
 345        au8522_writereg(state, AU8522_REG434H, 0x88);
 346        au8522_writereg(state, AU8522_REG435H, 0xc2);
 347        au8522_writereg(state, AU8522_REG436H, 0x3c);
 348}
 349
 350static void au8522_setup_cvbs_mode(struct au8522_state *state)
 351{
 352        /* here we're going to try the pre-programmed route */
 353        au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
 354                        AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
 355
 356        /* PGA in automatic mode */
 357        au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
 358
 359        /* Enable clamping control */
 360        au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
 361
 362        au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
 363                        AU8522_INPUT_CONTROL_REG081H_CVBS_CH1);
 364
 365        setup_decoder_defaults(state, AU8522_INPUT_CONTROL_REG081H_CVBS_CH1);
 366
 367        au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 368                        AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
 369}
 370
 371static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state)
 372{
 373        /* here we're going to try the pre-programmed route */
 374        au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
 375                        AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
 376
 377        /* It's not clear why we have to have the PGA in automatic mode while
 378           enabling clamp control, but it's what Windows does */
 379        au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
 380
 381        /* Enable clamping control */
 382        au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
 383
 384        /* Disable automatic PGA (since the CVBS is coming from the tuner) */
 385        au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
 386
 387        /* Set input mode to CVBS on channel 4 with SIF audio input enabled */
 388        au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
 389                        AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF);
 390
 391        setup_decoder_defaults(state,
 392                               AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF);
 393
 394        au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 395                        AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
 396}
 397
 398static void au8522_setup_svideo_mode(struct au8522_state *state)
 399{
 400        au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
 401                        AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO);
 402
 403        /* Set input to Y on Channe1, C on Channel 3 */
 404        au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
 405                        AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13);
 406
 407        /* PGA in automatic mode */
 408        au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
 409
 410        /* Enable clamping control */
 411        au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
 412
 413        setup_decoder_defaults(state,
 414                               AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13);
 415
 416        au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 417                        AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
 418}
 419
 420/* ----------------------------------------------------------------------- */
 421
 422static void disable_audio_input(struct au8522_state *state)
 423{
 424        au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
 425        au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
 426        au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
 427
 428        au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
 429        au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
 430
 431        au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 432                        AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO);
 433}
 434
 435/* 0=disable, 1=SIF */
 436static void set_audio_input(struct au8522_state *state, int aud_input)
 437{
 438        int i;
 439
 440        /* Note that this function needs to be used in conjunction with setting
 441           the input routing via register 0x81 */
 442
 443        if (aud_input == AU8522_AUDIO_NONE) {
 444                disable_audio_input(state);
 445                return;
 446        }
 447
 448        if (aud_input != AU8522_AUDIO_SIF) {
 449                /* The caller asked for a mode we don't currently support */
 450                printk(KERN_ERR "Unsupported audio mode requested! mode=%d\n",
 451                       aud_input);
 452                return;
 453        }
 454
 455        /* Load the Audio Decoder Filter Coefficients */
 456        for (i = 0; i < NUM_LPFILTER_COEF; i++) {
 457                au8522_writereg(state, lpfilter_coef[i].reg_name,
 458                                lpfilter_coef[i].reg_val[0]);
 459        }
 460
 461        /* Setup audio */
 462        au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
 463        au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
 464        au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
 465        au8522_writereg(state, AU8522_I2C_CONTROL_REG1_REG091H, 0x80);
 466        au8522_writereg(state, AU8522_I2C_CONTROL_REG0_REG090H, 0x84);
 467        msleep(150);
 468        au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x00);
 469        msleep(1);
 470        au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x9d);
 471        msleep(50);
 472        au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
 473        au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
 474        au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
 475        msleep(80);
 476        au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
 477        au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
 478        au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
 479        au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
 480        msleep(70);
 481        au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
 482        au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
 483        au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
 484}
 485
 486/* ----------------------------------------------------------------------- */
 487
 488static int au8522_s_ctrl(struct v4l2_ctrl *ctrl)
 489{
 490        struct au8522_state *state =
 491                container_of(ctrl->handler, struct au8522_state, hdl);
 492
 493        switch (ctrl->id) {
 494        case V4L2_CID_BRIGHTNESS:
 495                au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
 496                                ctrl->val - 128);
 497                break;
 498        case V4L2_CID_CONTRAST:
 499                au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
 500                                ctrl->val);
 501                break;
 502        case V4L2_CID_SATURATION:
 503                au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
 504                                ctrl->val);
 505                au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
 506                                ctrl->val);
 507                break;
 508        case V4L2_CID_HUE:
 509                au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
 510                                ctrl->val >> 8);
 511                au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
 512                                ctrl->val & 0xFF);
 513                break;
 514        default:
 515                return -EINVAL;
 516        }
 517
 518        return 0;
 519}
 520
 521/* ----------------------------------------------------------------------- */
 522
 523#ifdef CONFIG_VIDEO_ADV_DEBUG
 524static int au8522_g_register(struct v4l2_subdev *sd,
 525                             struct v4l2_dbg_register *reg)
 526{
 527        struct i2c_client *client = v4l2_get_subdevdata(sd);
 528        struct au8522_state *state = to_state(sd);
 529
 530        if (!v4l2_chip_match_i2c_client(client, &reg->match))
 531                return -EINVAL;
 532        if (!capable(CAP_SYS_ADMIN))
 533                return -EPERM;
 534        reg->val = au8522_readreg(state, reg->reg & 0xffff);
 535        return 0;
 536}
 537
 538static int au8522_s_register(struct v4l2_subdev *sd,
 539                             const struct v4l2_dbg_register *reg)
 540{
 541        struct i2c_client *client = v4l2_get_subdevdata(sd);
 542        struct au8522_state *state = to_state(sd);
 543
 544        if (!v4l2_chip_match_i2c_client(client, &reg->match))
 545                return -EINVAL;
 546        if (!capable(CAP_SYS_ADMIN))
 547                return -EPERM;
 548        au8522_writereg(state, reg->reg, reg->val & 0xff);
 549        return 0;
 550}
 551#endif
 552
 553static int au8522_s_stream(struct v4l2_subdev *sd, int enable)
 554{
 555        struct au8522_state *state = to_state(sd);
 556
 557        if (enable) {
 558                au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 559                                0x01);
 560                msleep(1);
 561                au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 562                                AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
 563        } else {
 564                /* This does not completely power down the device
 565                   (it only reduces it from around 140ma to 80ma) */
 566                au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 567                                1 << 5);
 568        }
 569        return 0;
 570}
 571
 572static int au8522_reset(struct v4l2_subdev *sd, u32 val)
 573{
 574        struct au8522_state *state = to_state(sd);
 575
 576        state->operational_mode = AU8522_ANALOG_MODE;
 577
 578        /* Clear out any state associated with the digital side of the
 579           chip, so that when it gets powered back up it won't think
 580           that it is already tuned */
 581        state->current_frequency = 0;
 582
 583        au8522_writereg(state, 0xa4, 1 << 5);
 584
 585        return 0;
 586}
 587
 588static int au8522_s_video_routing(struct v4l2_subdev *sd,
 589                                        u32 input, u32 output, u32 config)
 590{
 591        struct au8522_state *state = to_state(sd);
 592
 593        au8522_reset(sd, 0);
 594
 595        if (input == AU8522_COMPOSITE_CH1) {
 596                au8522_setup_cvbs_mode(state);
 597        } else if (input == AU8522_SVIDEO_CH13) {
 598                au8522_setup_svideo_mode(state);
 599        } else if (input == AU8522_COMPOSITE_CH4_SIF) {
 600                au8522_setup_cvbs_tuner_mode(state);
 601        } else {
 602                printk(KERN_ERR "au8522 mode not currently supported\n");
 603                return -EINVAL;
 604        }
 605        return 0;
 606}
 607
 608static int au8522_s_audio_routing(struct v4l2_subdev *sd,
 609                                        u32 input, u32 output, u32 config)
 610{
 611        struct au8522_state *state = to_state(sd);
 612        set_audio_input(state, input);
 613        return 0;
 614}
 615
 616static int au8522_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
 617{
 618        int val = 0;
 619        struct au8522_state *state = to_state(sd);
 620        u8 lock_status;
 621
 622        /* Interrogate the decoder to see if we are getting a real signal */
 623        lock_status = au8522_readreg(state, 0x00);
 624        if (lock_status == 0xa2)
 625                vt->signal = 0xffff;
 626        else
 627                vt->signal = 0x00;
 628
 629        vt->capability |=
 630                V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
 631                V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
 632
 633        val = V4L2_TUNER_SUB_MONO;
 634        vt->rxsubchans = val;
 635        vt->audmode = V4L2_TUNER_MODE_STEREO;
 636        return 0;
 637}
 638
 639static int au8522_g_chip_ident(struct v4l2_subdev *sd,
 640                               struct v4l2_dbg_chip_ident *chip)
 641{
 642        struct au8522_state *state = to_state(sd);
 643        struct i2c_client *client = v4l2_get_subdevdata(sd);
 644
 645        return v4l2_chip_ident_i2c_client(client, chip, state->id, state->rev);
 646}
 647
 648/* ----------------------------------------------------------------------- */
 649
 650static const struct v4l2_subdev_core_ops au8522_core_ops = {
 651        .log_status = v4l2_ctrl_subdev_log_status,
 652        .g_chip_ident = au8522_g_chip_ident,
 653        .reset = au8522_reset,
 654#ifdef CONFIG_VIDEO_ADV_DEBUG
 655        .g_register = au8522_g_register,
 656        .s_register = au8522_s_register,
 657#endif
 658};
 659
 660static const struct v4l2_subdev_tuner_ops au8522_tuner_ops = {
 661        .g_tuner = au8522_g_tuner,
 662};
 663
 664static const struct v4l2_subdev_audio_ops au8522_audio_ops = {
 665        .s_routing = au8522_s_audio_routing,
 666};
 667
 668static const struct v4l2_subdev_video_ops au8522_video_ops = {
 669        .s_routing = au8522_s_video_routing,
 670        .s_stream = au8522_s_stream,
 671};
 672
 673static const struct v4l2_subdev_ops au8522_ops = {
 674        .core = &au8522_core_ops,
 675        .tuner = &au8522_tuner_ops,
 676        .audio = &au8522_audio_ops,
 677        .video = &au8522_video_ops,
 678};
 679
 680static const struct v4l2_ctrl_ops au8522_ctrl_ops = {
 681        .s_ctrl = au8522_s_ctrl,
 682};
 683
 684/* ----------------------------------------------------------------------- */
 685
 686static int au8522_probe(struct i2c_client *client,
 687                        const struct i2c_device_id *did)
 688{
 689        struct au8522_state *state;
 690        struct v4l2_ctrl_handler *hdl;
 691        struct v4l2_subdev *sd;
 692        int instance;
 693        struct au8522_config *demod_config;
 694
 695        /* Check if the adapter supports the needed features */
 696        if (!i2c_check_functionality(client->adapter,
 697                                     I2C_FUNC_SMBUS_BYTE_DATA)) {
 698                return -EIO;
 699        }
 700
 701        /* allocate memory for the internal state */
 702        instance = au8522_get_state(&state, client->adapter, client->addr);
 703        switch (instance) {
 704        case 0:
 705                printk(KERN_ERR "au8522_decoder allocation failed\n");
 706                return -EIO;
 707        case 1:
 708                /* new demod instance */
 709                printk(KERN_INFO "au8522_decoder creating new instance...\n");
 710                break;
 711        default:
 712                /* existing demod instance */
 713                printk(KERN_INFO "au8522_decoder attach existing instance.\n");
 714                break;
 715        }
 716
 717        demod_config = kzalloc(sizeof(struct au8522_config), GFP_KERNEL);
 718        if (demod_config == NULL) {
 719                if (instance == 1)
 720                        kfree(state);
 721                return -ENOMEM;
 722        }
 723        demod_config->demod_address = 0x8e >> 1;
 724
 725        state->config = demod_config;
 726        state->i2c = client->adapter;
 727
 728        sd = &state->sd;
 729        v4l2_i2c_subdev_init(sd, client, &au8522_ops);
 730
 731        hdl = &state->hdl;
 732        v4l2_ctrl_handler_init(hdl, 4);
 733        v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
 734                        V4L2_CID_BRIGHTNESS, 0, 255, 1, 109);
 735        v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
 736                        V4L2_CID_CONTRAST, 0, 255, 1,
 737                        AU8522_TVDEC_CONTRAST_REG00BH_CVBS);
 738        v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
 739                        V4L2_CID_SATURATION, 0, 255, 1, 128);
 740        v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
 741                        V4L2_CID_HUE, -32768, 32767, 1, 0);
 742        sd->ctrl_handler = hdl;
 743        if (hdl->error) {
 744                int err = hdl->error;
 745
 746                v4l2_ctrl_handler_free(hdl);
 747                kfree(demod_config);
 748                kfree(state);
 749                return err;
 750        }
 751
 752        state->c = client;
 753        state->vid_input = AU8522_COMPOSITE_CH1;
 754        state->aud_input = AU8522_AUDIO_NONE;
 755        state->id = 8522;
 756        state->rev = 0;
 757
 758        /* Jam open the i2c gate to the tuner */
 759        au8522_writereg(state, 0x106, 1);
 760
 761        return 0;
 762}
 763
 764static int au8522_remove(struct i2c_client *client)
 765{
 766        struct v4l2_subdev *sd = i2c_get_clientdata(client);
 767        v4l2_device_unregister_subdev(sd);
 768        v4l2_ctrl_handler_free(sd->ctrl_handler);
 769        au8522_release_state(to_state(sd));
 770        return 0;
 771}
 772
 773static const struct i2c_device_id au8522_id[] = {
 774        {"au8522", 0},
 775        {}
 776};
 777
 778MODULE_DEVICE_TABLE(i2c, au8522_id);
 779
 780static struct i2c_driver au8522_driver = {
 781        .driver = {
 782                .owner  = THIS_MODULE,
 783                .name   = "au8522",
 784        },
 785        .probe          = au8522_probe,
 786        .remove         = au8522_remove,
 787        .id_table       = au8522_id,
 788};
 789
 790module_i2c_driver(au8522_driver);
 791