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22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/delay.h>
25#include <linux/dvb/frontend.h>
26#include <linux/i2c.h>
27#include <linux/slab.h>
28
29#include "dvb_frontend.h"
30
31#include "itd1000.h"
32#include "itd1000_priv.h"
33
34static int debug;
35module_param(debug, int, 0644);
36MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
37
38#define itd_dbg(args...) do { \
39 if (debug) { \
40 printk(KERN_DEBUG "ITD1000: " args);\
41 } \
42} while (0)
43
44#define itd_warn(args...) do { \
45 printk(KERN_WARNING "ITD1000: " args); \
46} while (0)
47
48#define itd_info(args...) do { \
49 printk(KERN_INFO "ITD1000: " args); \
50} while (0)
51
52
53static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len)
54{
55 u8 buf[1+len];
56 struct i2c_msg msg = {
57 .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1
58 };
59 buf[0] = reg;
60 memcpy(&buf[1], v, len);
61
62
63
64 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
65 printk(KERN_WARNING "itd1000 I2C write failed\n");
66 return -EREMOTEIO;
67 }
68 return 0;
69}
70
71static int itd1000_read_reg(struct itd1000_state *state, u8 reg)
72{
73 u8 val;
74 struct i2c_msg msg[2] = {
75 { .addr = state->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 },
76 { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 },
77 };
78
79
80 itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1);
81
82 if (i2c_transfer(state->i2c, msg, 2) != 2) {
83 itd_warn("itd1000 I2C read failed\n");
84 return -EREMOTEIO;
85 }
86 return val;
87}
88
89static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v)
90{
91 int ret = itd1000_write_regs(state, r, &v, 1);
92 state->shadow[r] = v;
93 return ret;
94}
95
96
97static struct {
98 u32 symbol_rate;
99 u8 pgaext : 4;
100 u8 bbgvmin : 4;
101} itd1000_lpf_pga[] = {
102 { 0, 0x8, 0x3 },
103 { 5200000, 0x8, 0x3 },
104 { 12200000, 0x4, 0x3 },
105 { 15400000, 0x2, 0x3 },
106 { 19800000, 0x2, 0x3 },
107 { 21500000, 0x2, 0x3 },
108 { 24500000, 0x2, 0x3 },
109 { 28400000, 0x2, 0x3 },
110 { 33400000, 0x2, 0x3 },
111 { 34400000, 0x1, 0x4 },
112 { 34400000, 0x1, 0x4 },
113 { 38400000, 0x1, 0x4 },
114 { 38400000, 0x1, 0x4 },
115 { 40400000, 0x1, 0x4 },
116 { 45400000, 0x1, 0x4 },
117};
118
119static void itd1000_set_lpf_bw(struct itd1000_state *state, u32 symbol_rate)
120{
121 u8 i;
122 u8 con1 = itd1000_read_reg(state, CON1) & 0xfd;
123 u8 pllfh = itd1000_read_reg(state, PLLFH) & 0x0f;
124 u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0;
125 u8 bw = itd1000_read_reg(state, BW) & 0xf0;
126
127 itd_dbg("symbol_rate = %d\n", symbol_rate);
128
129
130 itd1000_write_reg(state, CON1, con1 | (1 << 1));
131
132 for (i = 0; i < ARRAY_SIZE(itd1000_lpf_pga); i++)
133 if (symbol_rate < itd1000_lpf_pga[i].symbol_rate) {
134 itd_dbg("symrate: index: %d pgaext: %x, bbgvmin: %x\n", i, itd1000_lpf_pga[i].pgaext, itd1000_lpf_pga[i].bbgvmin);
135 itd1000_write_reg(state, PLLFH, pllfh | (itd1000_lpf_pga[i].pgaext << 4));
136 itd1000_write_reg(state, BBGVMIN, bbgvmin | (itd1000_lpf_pga[i].bbgvmin));
137 itd1000_write_reg(state, BW, bw | (i & 0x0f));
138 break;
139 }
140
141 itd1000_write_reg(state, CON1, con1 | (0 << 1));
142}
143
144static struct {
145 u8 vcorg;
146 u32 fmax_rg;
147} itd1000_vcorg[] = {
148 { 1, 920000 },
149 { 2, 971000 },
150 { 3, 1031000 },
151 { 4, 1091000 },
152 { 5, 1171000 },
153 { 6, 1281000 },
154 { 7, 1381000 },
155 { 8, 500000 },
156 { 9, 1451000 },
157 { 10, 1531000 },
158 { 11, 1631000 },
159 { 12, 1741000 },
160 { 13, 1891000 },
161 { 14, 2071000 },
162 { 15, 2250000 },
163};
164
165static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz)
166{
167 u8 i;
168 u8 gvbb_i2c = itd1000_read_reg(state, GVBB_I2C) & 0xbf;
169 u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f;
170 u8 adcout;
171
172
173 itd1000_write_reg(state, GVBB_I2C, gvbb_i2c | (1 << 6));
174
175 for (i = 0; i < ARRAY_SIZE(itd1000_vcorg); i++) {
176 if (freq_khz < itd1000_vcorg[i].fmax_rg) {
177 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | (itd1000_vcorg[i].vcorg << 4));
178 msleep(1);
179
180 adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f;
181
182 itd_dbg("VCO: %dkHz: %d -> ADCOUT: %d %02x\n", freq_khz, itd1000_vcorg[i].vcorg, adcout, vco_chp1_i2c);
183
184 if (adcout > 13) {
185 if (!(itd1000_vcorg[i].vcorg == 7 || itd1000_vcorg[i].vcorg == 15))
186 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg + 1) << 4));
187 } else if (adcout < 2) {
188 if (!(itd1000_vcorg[i].vcorg == 1 || itd1000_vcorg[i].vcorg == 9))
189 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg - 1) << 4));
190 }
191 break;
192 }
193 }
194}
195
196static const struct {
197 u32 freq;
198 u8 values[10];
199} itd1000_fre_values[] = {
200 { 1075000, { 0x59, 0x1d, 0x1c, 0x17, 0x16, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
201 { 1250000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
202 { 1450000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
203 { 1650000, { 0x69, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
204 { 1750000, { 0x69, 0x1e, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
205 { 1850000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
206 { 1900000, { 0x69, 0x1d, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
207 { 1950000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0d, 0x0b, 0x0a } },
208 { 2050000, { 0x69, 0x1e, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0b, 0x0a } },
209 { 2150000, { 0x69, 0x1d, 0x1c, 0x17, 0x15, 0x14, 0x13, 0x0f, 0x0e, 0x0b } }
210};
211
212
213#define FREF 16
214
215static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz)
216{
217 int i, j;
218 u32 plln, pllf;
219 u64 tmp;
220
221 plln = (freq_khz * 1000) / 2 / FREF;
222
223
224 tmp = plln % 1000000;
225 plln /= 1000000;
226
227 tmp *= 1048576;
228 do_div(tmp, 1000000);
229 pllf = (u32) tmp;
230
231 state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF;
232 itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln);
233
234 itd1000_write_reg(state, PLLNH, 0x80);
235 itd1000_write_reg(state, PLLNL, plln & 0xff);
236 itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f));
237 itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff);
238 itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff);
239
240 for (i = 0; i < ARRAY_SIZE(itd1000_fre_values); i++) {
241 if (freq_khz <= itd1000_fre_values[i].freq) {
242 itd_dbg("fre_values: %d\n", i);
243 itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]);
244 for (j = 0; j < 9; j++)
245 itd1000_write_reg(state, RFST1+j, itd1000_fre_values[i].values[j+1]);
246 break;
247 }
248 }
249
250 itd1000_set_vco(state, freq_khz);
251}
252
253static int itd1000_set_parameters(struct dvb_frontend *fe)
254{
255 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
256 struct itd1000_state *state = fe->tuner_priv;
257 u8 pllcon1;
258
259 itd1000_set_lo(state, c->frequency);
260 itd1000_set_lpf_bw(state, c->symbol_rate);
261
262 pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f;
263 itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7));
264 itd1000_write_reg(state, PLLCON1, pllcon1);
265
266 return 0;
267}
268
269static int itd1000_get_frequency(struct dvb_frontend *fe, u32 *frequency)
270{
271 struct itd1000_state *state = fe->tuner_priv;
272 *frequency = state->frequency;
273 return 0;
274}
275
276static int itd1000_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
277{
278 return 0;
279}
280
281static u8 itd1000_init_tab[][2] = {
282 { PLLCON1, 0x65 },
283 { PLLNH, 0x80 },
284 { RESERVED_0X6D, 0x3b },
285 { VCO_CHP2_I2C, 0x12 },
286 { 0x72, 0xf9 },
287 { RESERVED_0X73, 0xff },
288 { RESERVED_0X74, 0xb2 },
289 { RESERVED_0X75, 0xc7 },
290 { EXTGVBBRF, 0xf0 },
291 { DIVAGCCK, 0x80 },
292 { BBTR, 0xa0 },
293 { RESERVED_0X7E, 0x4f },
294 { 0x82, 0x88 },
295 { 0x83, 0x80 },
296 { 0x84, 0x80 },
297 { RESERVED_0X85, 0x74 },
298 { RESERVED_0X86, 0xff },
299 { RESERVED_0X88, 0x02 },
300 { RESERVED_0X89, 0x16 },
301 { RFST0, 0x1f },
302 { RESERVED_0X94, 0x66 },
303 { RESERVED_0X95, 0x66 },
304 { RESERVED_0X96, 0x77 },
305 { RESERVED_0X97, 0x99 },
306 { RESERVED_0X98, 0xff },
307 { RESERVED_0X99, 0xfc },
308 { RESERVED_0X9A, 0xba },
309 { RESERVED_0X9B, 0xaa },
310};
311
312static u8 itd1000_reinit_tab[][2] = {
313 { VCO_CHP1_I2C, 0x8a },
314 { BW, 0x87 },
315 { GVBB_I2C, 0x03 },
316 { BBGVMIN, 0x03 },
317 { CON1, 0x2e },
318};
319
320
321static int itd1000_init(struct dvb_frontend *fe)
322{
323 struct itd1000_state *state = fe->tuner_priv;
324 int i;
325
326 for (i = 0; i < ARRAY_SIZE(itd1000_init_tab); i++)
327 itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]);
328
329 for (i = 0; i < ARRAY_SIZE(itd1000_reinit_tab); i++)
330 itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]);
331
332 return 0;
333}
334
335static int itd1000_sleep(struct dvb_frontend *fe)
336{
337 return 0;
338}
339
340static int itd1000_release(struct dvb_frontend *fe)
341{
342 kfree(fe->tuner_priv);
343 fe->tuner_priv = NULL;
344 return 0;
345}
346
347static const struct dvb_tuner_ops itd1000_tuner_ops = {
348 .info = {
349 .name = "Integrant ITD1000",
350 .frequency_min = 950000,
351 .frequency_max = 2150000,
352 .frequency_step = 125,
353 },
354
355 .release = itd1000_release,
356
357 .init = itd1000_init,
358 .sleep = itd1000_sleep,
359
360 .set_params = itd1000_set_parameters,
361 .get_frequency = itd1000_get_frequency,
362 .get_bandwidth = itd1000_get_bandwidth
363};
364
365
366struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg)
367{
368 struct itd1000_state *state = NULL;
369 u8 i = 0;
370
371 state = kzalloc(sizeof(struct itd1000_state), GFP_KERNEL);
372 if (state == NULL)
373 return NULL;
374
375 state->cfg = cfg;
376 state->i2c = i2c;
377
378 i = itd1000_read_reg(state, 0);
379 if (i != 0) {
380 kfree(state);
381 return NULL;
382 }
383 itd_info("successfully identified (ID: %d)\n", i);
384
385 memset(state->shadow, 0xff, sizeof(state->shadow));
386 for (i = 0x65; i < 0x9c; i++)
387 state->shadow[i] = itd1000_read_reg(state, i);
388
389 memcpy(&fe->ops.tuner_ops, &itd1000_tuner_ops, sizeof(struct dvb_tuner_ops));
390
391 fe->tuner_priv = state;
392
393 return fe;
394}
395EXPORT_SYMBOL(itd1000_attach);
396
397MODULE_AUTHOR("Patrick Boettcher <pb@linuxtv.org>");
398MODULE_DESCRIPTION("Integrant ITD1000 driver");
399MODULE_LICENSE("GPL");
400
