linux/drivers/media/dvb-frontends/s5h1420.c
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   1/*
   2 * Driver for
   3 *    Samsung S5H1420 and
   4 *    PnpNetwork PN1010 QPSK Demodulator
   5 *
   6 * Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
   7 * Copyright (C) 2005-8 Patrick Boettcher <pb@linuxtv.org>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; either version 2 of the License, or
  12 * (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 *
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23 */
  24
  25#include <linux/kernel.h>
  26#include <linux/module.h>
  27#include <linux/init.h>
  28#include <linux/string.h>
  29#include <linux/slab.h>
  30#include <linux/delay.h>
  31#include <linux/jiffies.h>
  32#include <asm/div64.h>
  33
  34#include <linux/i2c.h>
  35
  36
  37#include "dvb_frontend.h"
  38#include "s5h1420.h"
  39#include "s5h1420_priv.h"
  40
  41#define TONE_FREQ 22000
  42
  43struct s5h1420_state {
  44        struct i2c_adapter* i2c;
  45        const struct s5h1420_config* config;
  46
  47        struct dvb_frontend frontend;
  48        struct i2c_adapter tuner_i2c_adapter;
  49
  50        u8 CON_1_val;
  51
  52        u8 postlocked:1;
  53        u32 fclk;
  54        u32 tunedfreq;
  55        fe_code_rate_t fec_inner;
  56        u32 symbol_rate;
  57
  58        /* FIXME: ugly workaround for flexcop's incapable i2c-controller
  59         * it does not support repeated-start, workaround: write addr-1
  60         * and then read
  61         */
  62        u8 shadow[256];
  63};
  64
  65static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
  66static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
  67                                     struct dvb_frontend_tune_settings* fesettings);
  68
  69
  70static int debug;
  71module_param(debug, int, 0644);
  72MODULE_PARM_DESC(debug, "enable debugging");
  73
  74#define dprintk(x...) do { \
  75        if (debug) \
  76                printk(KERN_DEBUG "S5H1420: " x); \
  77} while (0)
  78
  79static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg)
  80{
  81        int ret;
  82        u8 b[2];
  83        struct i2c_msg msg[] = {
  84                { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 },
  85                { .addr = state->config->demod_address, .flags = 0, .buf = &reg, .len = 1 },
  86                { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 },
  87        };
  88
  89        b[0] = (reg - 1) & 0xff;
  90        b[1] = state->shadow[(reg - 1) & 0xff];
  91
  92        if (state->config->repeated_start_workaround) {
  93                ret = i2c_transfer(state->i2c, msg, 3);
  94                if (ret != 3)
  95                        return ret;
  96        } else {
  97                ret = i2c_transfer(state->i2c, &msg[1], 1);
  98                if (ret != 1)
  99                        return ret;
 100                ret = i2c_transfer(state->i2c, &msg[2], 1);
 101                if (ret != 1)
 102                        return ret;
 103        }
 104
 105        /* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */
 106
 107        return b[0];
 108}
 109
 110static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
 111{
 112        u8 buf[] = { reg, data };
 113        struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
 114        int err;
 115
 116        /* dprintk("wr(%02x): %02x %02x\n", state->config->demod_address, reg, data); */
 117        err = i2c_transfer(state->i2c, &msg, 1);
 118        if (err != 1) {
 119                dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
 120                return -EREMOTEIO;
 121        }
 122        state->shadow[reg] = data;
 123
 124        return 0;
 125}
 126
 127static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
 128{
 129        struct s5h1420_state* state = fe->demodulator_priv;
 130
 131        dprintk("enter %s\n", __func__);
 132
 133        switch(voltage) {
 134        case SEC_VOLTAGE_13:
 135                s5h1420_writereg(state, 0x3c,
 136                                 (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
 137                break;
 138
 139        case SEC_VOLTAGE_18:
 140                s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);
 141                break;
 142
 143        case SEC_VOLTAGE_OFF:
 144                s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);
 145                break;
 146        }
 147
 148        dprintk("leave %s\n", __func__);
 149        return 0;
 150}
 151
 152static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
 153{
 154        struct s5h1420_state* state = fe->demodulator_priv;
 155
 156        dprintk("enter %s\n", __func__);
 157        switch(tone) {
 158        case SEC_TONE_ON:
 159                s5h1420_writereg(state, 0x3b,
 160                                 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
 161                break;
 162
 163        case SEC_TONE_OFF:
 164                s5h1420_writereg(state, 0x3b,
 165                                 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
 166                break;
 167        }
 168        dprintk("leave %s\n", __func__);
 169
 170        return 0;
 171}
 172
 173static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
 174                                    struct dvb_diseqc_master_cmd* cmd)
 175{
 176        struct s5h1420_state* state = fe->demodulator_priv;
 177        u8 val;
 178        int i;
 179        unsigned long timeout;
 180        int result = 0;
 181
 182        dprintk("enter %s\n", __func__);
 183        if (cmd->msg_len > 8)
 184                return -EINVAL;
 185
 186        /* setup for DISEQC */
 187        val = s5h1420_readreg(state, 0x3b);
 188        s5h1420_writereg(state, 0x3b, 0x02);
 189        msleep(15);
 190
 191        /* write the DISEQC command bytes */
 192        for(i=0; i< cmd->msg_len; i++) {
 193                s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
 194        }
 195
 196        /* kick off transmission */
 197        s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
 198                                      ((cmd->msg_len-1) << 4) | 0x08);
 199
 200        /* wait for transmission to complete */
 201        timeout = jiffies + ((100*HZ) / 1000);
 202        while(time_before(jiffies, timeout)) {
 203                if (!(s5h1420_readreg(state, 0x3b) & 0x08))
 204                        break;
 205
 206                msleep(5);
 207        }
 208        if (time_after(jiffies, timeout))
 209                result = -ETIMEDOUT;
 210
 211        /* restore original settings */
 212        s5h1420_writereg(state, 0x3b, val);
 213        msleep(15);
 214        dprintk("leave %s\n", __func__);
 215        return result;
 216}
 217
 218static int s5h1420_recv_slave_reply (struct dvb_frontend* fe,
 219                                     struct dvb_diseqc_slave_reply* reply)
 220{
 221        struct s5h1420_state* state = fe->demodulator_priv;
 222        u8 val;
 223        int i;
 224        int length;
 225        unsigned long timeout;
 226        int result = 0;
 227
 228        /* setup for DISEQC receive */
 229        val = s5h1420_readreg(state, 0x3b);
 230        s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */
 231        msleep(15);
 232
 233        /* wait for reception to complete */
 234        timeout = jiffies + ((reply->timeout*HZ) / 1000);
 235        while(time_before(jiffies, timeout)) {
 236                if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */
 237                        break;
 238
 239                msleep(5);
 240        }
 241        if (time_after(jiffies, timeout)) {
 242                result = -ETIMEDOUT;
 243                goto exit;
 244        }
 245
 246        /* check error flag - FIXME: not sure what this does - docs do not describe
 247         * beyond "error flag for diseqc receive data :( */
 248        if (s5h1420_readreg(state, 0x49)) {
 249                result = -EIO;
 250                goto exit;
 251        }
 252
 253        /* check length */
 254        length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4;
 255        if (length > sizeof(reply->msg)) {
 256                result = -EOVERFLOW;
 257                goto exit;
 258        }
 259        reply->msg_len = length;
 260
 261        /* extract data */
 262        for(i=0; i< length; i++) {
 263                reply->msg[i] = s5h1420_readreg(state, 0x3d + i);
 264        }
 265
 266exit:
 267        /* restore original settings */
 268        s5h1420_writereg(state, 0x3b, val);
 269        msleep(15);
 270        return result;
 271}
 272
 273static int s5h1420_send_burst (struct dvb_frontend* fe, fe_sec_mini_cmd_t minicmd)
 274{
 275        struct s5h1420_state* state = fe->demodulator_priv;
 276        u8 val;
 277        int result = 0;
 278        unsigned long timeout;
 279
 280        /* setup for tone burst */
 281        val = s5h1420_readreg(state, 0x3b);
 282        s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);
 283
 284        /* set value for B position if requested */
 285        if (minicmd == SEC_MINI_B) {
 286                s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);
 287        }
 288        msleep(15);
 289
 290        /* start transmission */
 291        s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
 292
 293        /* wait for transmission to complete */
 294        timeout = jiffies + ((100*HZ) / 1000);
 295        while(time_before(jiffies, timeout)) {
 296                if (!(s5h1420_readreg(state, 0x3b) & 0x08))
 297                        break;
 298
 299                msleep(5);
 300        }
 301        if (time_after(jiffies, timeout))
 302                result = -ETIMEDOUT;
 303
 304        /* restore original settings */
 305        s5h1420_writereg(state, 0x3b, val);
 306        msleep(15);
 307        return result;
 308}
 309
 310static fe_status_t s5h1420_get_status_bits(struct s5h1420_state* state)
 311{
 312        u8 val;
 313        fe_status_t status = 0;
 314
 315        val = s5h1420_readreg(state, 0x14);
 316        if (val & 0x02)
 317                status |=  FE_HAS_SIGNAL;
 318        if (val & 0x01)
 319                status |=  FE_HAS_CARRIER;
 320        val = s5h1420_readreg(state, 0x36);
 321        if (val & 0x01)
 322                status |=  FE_HAS_VITERBI;
 323        if (val & 0x20)
 324                status |=  FE_HAS_SYNC;
 325        if (status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI|FE_HAS_SYNC))
 326                status |=  FE_HAS_LOCK;
 327
 328        return status;
 329}
 330
 331static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
 332{
 333        struct s5h1420_state* state = fe->demodulator_priv;
 334        u8 val;
 335
 336        dprintk("enter %s\n", __func__);
 337
 338        if (status == NULL)
 339                return -EINVAL;
 340
 341        /* determine lock state */
 342        *status = s5h1420_get_status_bits(state);
 343
 344        /* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
 345        the inversion, wait a bit and check again */
 346        if (*status == (FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI)) {
 347                val = s5h1420_readreg(state, Vit10);
 348                if ((val & 0x07) == 0x03) {
 349                        if (val & 0x08)
 350                                s5h1420_writereg(state, Vit09, 0x13);
 351                        else
 352                                s5h1420_writereg(state, Vit09, 0x1b);
 353
 354                        /* wait a bit then update lock status */
 355                        mdelay(200);
 356                        *status = s5h1420_get_status_bits(state);
 357                }
 358        }
 359
 360        /* perform post lock setup */
 361        if ((*status & FE_HAS_LOCK) && !state->postlocked) {
 362
 363                /* calculate the data rate */
 364                u32 tmp = s5h1420_getsymbolrate(state);
 365                switch (s5h1420_readreg(state, Vit10) & 0x07) {
 366                case 0: tmp = (tmp * 2 * 1) / 2; break;
 367                case 1: tmp = (tmp * 2 * 2) / 3; break;
 368                case 2: tmp = (tmp * 2 * 3) / 4; break;
 369                case 3: tmp = (tmp * 2 * 5) / 6; break;
 370                case 4: tmp = (tmp * 2 * 6) / 7; break;
 371                case 5: tmp = (tmp * 2 * 7) / 8; break;
 372                }
 373
 374                if (tmp == 0) {
 375                        printk(KERN_ERR "s5h1420: avoided division by 0\n");
 376                        tmp = 1;
 377                }
 378                tmp = state->fclk / tmp;
 379
 380
 381                /* set the MPEG_CLK_INTL for the calculated data rate */
 382                if (tmp < 2)
 383                        val = 0x00;
 384                else if (tmp < 5)
 385                        val = 0x01;
 386                else if (tmp < 9)
 387                        val = 0x02;
 388                else if (tmp < 13)
 389                        val = 0x03;
 390                else if (tmp < 17)
 391                        val = 0x04;
 392                else if (tmp < 25)
 393                        val = 0x05;
 394                else if (tmp < 33)
 395                        val = 0x06;
 396                else
 397                        val = 0x07;
 398                dprintk("for MPEG_CLK_INTL %d %x\n", tmp, val);
 399
 400                s5h1420_writereg(state, FEC01, 0x18);
 401                s5h1420_writereg(state, FEC01, 0x10);
 402                s5h1420_writereg(state, FEC01, val);
 403
 404                /* Enable "MPEG_Out" */
 405                val = s5h1420_readreg(state, Mpeg02);
 406                s5h1420_writereg(state, Mpeg02, val | (1 << 6));
 407
 408                /* kicker disable */
 409                val = s5h1420_readreg(state, QPSK01) & 0x7f;
 410                s5h1420_writereg(state, QPSK01, val);
 411
 412                /* DC freeze TODO it was never activated by default or it can stay activated */
 413
 414                if (s5h1420_getsymbolrate(state) >= 20000000) {
 415                        s5h1420_writereg(state, Loop04, 0x8a);
 416                        s5h1420_writereg(state, Loop05, 0x6a);
 417                } else {
 418                        s5h1420_writereg(state, Loop04, 0x58);
 419                        s5h1420_writereg(state, Loop05, 0x27);
 420                }
 421
 422                /* post-lock processing has been done! */
 423                state->postlocked = 1;
 424        }
 425
 426        dprintk("leave %s\n", __func__);
 427
 428        return 0;
 429}
 430
 431static int s5h1420_read_ber(struct dvb_frontend* fe, u32* ber)
 432{
 433        struct s5h1420_state* state = fe->demodulator_priv;
 434
 435        s5h1420_writereg(state, 0x46, 0x1d);
 436        mdelay(25);
 437
 438        *ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
 439
 440        return 0;
 441}
 442
 443static int s5h1420_read_signal_strength(struct dvb_frontend* fe, u16* strength)
 444{
 445        struct s5h1420_state* state = fe->demodulator_priv;
 446
 447        u8 val = s5h1420_readreg(state, 0x15);
 448
 449        *strength =  (u16) ((val << 8) | val);
 450
 451        return 0;
 452}
 453
 454static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 455{
 456        struct s5h1420_state* state = fe->demodulator_priv;
 457
 458        s5h1420_writereg(state, 0x46, 0x1f);
 459        mdelay(25);
 460
 461        *ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
 462
 463        return 0;
 464}
 465
 466static void s5h1420_reset(struct s5h1420_state* state)
 467{
 468        dprintk("%s\n", __func__);
 469        s5h1420_writereg (state, 0x01, 0x08);
 470        s5h1420_writereg (state, 0x01, 0x00);
 471        udelay(10);
 472}
 473
 474static void s5h1420_setsymbolrate(struct s5h1420_state* state,
 475                                  struct dtv_frontend_properties *p)
 476{
 477        u8 v;
 478        u64 val;
 479
 480        dprintk("enter %s\n", __func__);
 481
 482        val = ((u64) p->symbol_rate / 1000ULL) * (1ULL<<24);
 483        if (p->symbol_rate < 29000000)
 484                val *= 2;
 485        do_div(val, (state->fclk / 1000));
 486
 487        dprintk("symbol rate register: %06llx\n", (unsigned long long)val);
 488
 489        v = s5h1420_readreg(state, Loop01);
 490        s5h1420_writereg(state, Loop01, v & 0x7f);
 491        s5h1420_writereg(state, Tnco01, val >> 16);
 492        s5h1420_writereg(state, Tnco02, val >> 8);
 493        s5h1420_writereg(state, Tnco03, val & 0xff);
 494        s5h1420_writereg(state, Loop01,  v | 0x80);
 495        dprintk("leave %s\n", __func__);
 496}
 497
 498static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
 499{
 500        return state->symbol_rate;
 501}
 502
 503static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
 504{
 505        int val;
 506        u8 v;
 507
 508        dprintk("enter %s\n", __func__);
 509
 510        /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
 511         * divide fclk by 1000000 to get the correct value. */
 512        val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
 513
 514        dprintk("phase rotator/freqoffset: %d %06x\n", freqoffset, val);
 515
 516        v = s5h1420_readreg(state, Loop01);
 517        s5h1420_writereg(state, Loop01, v & 0xbf);
 518        s5h1420_writereg(state, Pnco01, val >> 16);
 519        s5h1420_writereg(state, Pnco02, val >> 8);
 520        s5h1420_writereg(state, Pnco03, val & 0xff);
 521        s5h1420_writereg(state, Loop01, v | 0x40);
 522        dprintk("leave %s\n", __func__);
 523}
 524
 525static int s5h1420_getfreqoffset(struct s5h1420_state* state)
 526{
 527        int val;
 528
 529        s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
 530        val  = s5h1420_readreg(state, 0x0e) << 16;
 531        val |= s5h1420_readreg(state, 0x0f) << 8;
 532        val |= s5h1420_readreg(state, 0x10);
 533        s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
 534
 535        if (val & 0x800000)
 536                val |= 0xff000000;
 537
 538        /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
 539         * divide fclk by 1000000 to get the correct value. */
 540        val = (((-val) * (state->fclk/1000000)) / (1<<24));
 541
 542        return val;
 543}
 544
 545static void s5h1420_setfec_inversion(struct s5h1420_state* state,
 546                                     struct dtv_frontend_properties *p)
 547{
 548        u8 inversion = 0;
 549        u8 vit08, vit09;
 550
 551        dprintk("enter %s\n", __func__);
 552
 553        if (p->inversion == INVERSION_OFF)
 554                inversion = state->config->invert ? 0x08 : 0;
 555        else if (p->inversion == INVERSION_ON)
 556                inversion = state->config->invert ? 0 : 0x08;
 557
 558        if ((p->fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
 559                vit08 = 0x3f;
 560                vit09 = 0;
 561        } else {
 562                switch (p->fec_inner) {
 563                case FEC_1_2:
 564                        vit08 = 0x01; vit09 = 0x10;
 565                        break;
 566
 567                case FEC_2_3:
 568                        vit08 = 0x02; vit09 = 0x11;
 569                        break;
 570
 571                case FEC_3_4:
 572                        vit08 = 0x04; vit09 = 0x12;
 573                        break;
 574
 575                case FEC_5_6:
 576                        vit08 = 0x08; vit09 = 0x13;
 577                        break;
 578
 579                case FEC_6_7:
 580                        vit08 = 0x10; vit09 = 0x14;
 581                        break;
 582
 583                case FEC_7_8:
 584                        vit08 = 0x20; vit09 = 0x15;
 585                        break;
 586
 587                default:
 588                        return;
 589                }
 590        }
 591        vit09 |= inversion;
 592        dprintk("fec: %02x %02x\n", vit08, vit09);
 593        s5h1420_writereg(state, Vit08, vit08);
 594        s5h1420_writereg(state, Vit09, vit09);
 595        dprintk("leave %s\n", __func__);
 596}
 597
 598static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state)
 599{
 600        switch(s5h1420_readreg(state, 0x32) & 0x07) {
 601        case 0:
 602                return FEC_1_2;
 603
 604        case 1:
 605                return FEC_2_3;
 606
 607        case 2:
 608                return FEC_3_4;
 609
 610        case 3:
 611                return FEC_5_6;
 612
 613        case 4:
 614                return FEC_6_7;
 615
 616        case 5:
 617                return FEC_7_8;
 618        }
 619
 620        return FEC_NONE;
 621}
 622
 623static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state)
 624{
 625        if (s5h1420_readreg(state, 0x32) & 0x08)
 626                return INVERSION_ON;
 627
 628        return INVERSION_OFF;
 629}
 630
 631static int s5h1420_set_frontend(struct dvb_frontend *fe)
 632{
 633        struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 634        struct s5h1420_state* state = fe->demodulator_priv;
 635        int frequency_delta;
 636        struct dvb_frontend_tune_settings fesettings;
 637
 638        dprintk("enter %s\n", __func__);
 639
 640        /* check if we should do a fast-tune */
 641        s5h1420_get_tune_settings(fe, &fesettings);
 642        frequency_delta = p->frequency - state->tunedfreq;
 643        if ((frequency_delta > -fesettings.max_drift) &&
 644                        (frequency_delta < fesettings.max_drift) &&
 645                        (frequency_delta != 0) &&
 646                        (state->fec_inner == p->fec_inner) &&
 647                        (state->symbol_rate == p->symbol_rate)) {
 648
 649                if (fe->ops.tuner_ops.set_params) {
 650                        fe->ops.tuner_ops.set_params(fe);
 651                        if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
 652                }
 653                if (fe->ops.tuner_ops.get_frequency) {
 654                        u32 tmp;
 655                        fe->ops.tuner_ops.get_frequency(fe, &tmp);
 656                        if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
 657                        s5h1420_setfreqoffset(state, p->frequency - tmp);
 658                } else {
 659                        s5h1420_setfreqoffset(state, 0);
 660                }
 661                dprintk("simple tune\n");
 662                return 0;
 663        }
 664        dprintk("tuning demod\n");
 665
 666        /* first of all, software reset */
 667        s5h1420_reset(state);
 668
 669        /* set s5h1420 fclk PLL according to desired symbol rate */
 670        if (p->symbol_rate > 33000000)
 671                state->fclk = 80000000;
 672        else if (p->symbol_rate > 28500000)
 673                state->fclk = 59000000;
 674        else if (p->symbol_rate > 25000000)
 675                state->fclk = 86000000;
 676        else if (p->symbol_rate > 1900000)
 677                state->fclk = 88000000;
 678        else
 679                state->fclk = 44000000;
 680
 681        dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
 682        s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
 683        s5h1420_writereg(state, PLL02, 0x40);
 684        s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
 685
 686        /* TODO DC offset removal, config parameter ? */
 687        if (p->symbol_rate > 29000000)
 688                s5h1420_writereg(state, QPSK01, 0xae | 0x10);
 689        else
 690                s5h1420_writereg(state, QPSK01, 0xac | 0x10);
 691
 692        /* set misc registers */
 693        s5h1420_writereg(state, CON_1, 0x00);
 694        s5h1420_writereg(state, QPSK02, 0x00);
 695        s5h1420_writereg(state, Pre01, 0xb0);
 696
 697        s5h1420_writereg(state, Loop01, 0xF0);
 698        s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
 699        s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
 700        if (p->symbol_rate > 20000000)
 701                s5h1420_writereg(state, Loop04, 0x79);
 702        else
 703                s5h1420_writereg(state, Loop04, 0x58);
 704        s5h1420_writereg(state, Loop05, 0x6b);
 705
 706        if (p->symbol_rate >= 8000000)
 707                s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
 708        else if (p->symbol_rate >= 4000000)
 709                s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
 710        else
 711                s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
 712
 713        s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
 714
 715        s5h1420_writereg(state, Sync01, 0x33);
 716        s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
 717        s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
 718        s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
 719
 720        s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
 721        s5h1420_writereg(state, DiS03, 0x00);
 722        s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
 723
 724        /* set tuner PLL */
 725        if (fe->ops.tuner_ops.set_params) {
 726                fe->ops.tuner_ops.set_params(fe);
 727                if (fe->ops.i2c_gate_ctrl)
 728                        fe->ops.i2c_gate_ctrl(fe, 0);
 729                s5h1420_setfreqoffset(state, 0);
 730        }
 731
 732        /* set the reset of the parameters */
 733        s5h1420_setsymbolrate(state, p);
 734        s5h1420_setfec_inversion(state, p);
 735
 736        /* start QPSK */
 737        s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
 738
 739        state->fec_inner = p->fec_inner;
 740        state->symbol_rate = p->symbol_rate;
 741        state->postlocked = 0;
 742        state->tunedfreq = p->frequency;
 743
 744        dprintk("leave %s\n", __func__);
 745        return 0;
 746}
 747
 748static int s5h1420_get_frontend(struct dvb_frontend* fe)
 749{
 750        struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 751        struct s5h1420_state* state = fe->demodulator_priv;
 752
 753        p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state);
 754        p->inversion = s5h1420_getinversion(state);
 755        p->symbol_rate = s5h1420_getsymbolrate(state);
 756        p->fec_inner = s5h1420_getfec(state);
 757
 758        return 0;
 759}
 760
 761static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
 762                                     struct dvb_frontend_tune_settings* fesettings)
 763{
 764        struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 765        if (p->symbol_rate > 20000000) {
 766                fesettings->min_delay_ms = 50;
 767                fesettings->step_size = 2000;
 768                fesettings->max_drift = 8000;
 769        } else if (p->symbol_rate > 12000000) {
 770                fesettings->min_delay_ms = 100;
 771                fesettings->step_size = 1500;
 772                fesettings->max_drift = 9000;
 773        } else if (p->symbol_rate > 8000000) {
 774                fesettings->min_delay_ms = 100;
 775                fesettings->step_size = 1000;
 776                fesettings->max_drift = 8000;
 777        } else if (p->symbol_rate > 4000000) {
 778                fesettings->min_delay_ms = 100;
 779                fesettings->step_size = 500;
 780                fesettings->max_drift = 7000;
 781        } else if (p->symbol_rate > 2000000) {
 782                fesettings->min_delay_ms = 200;
 783                fesettings->step_size = (p->symbol_rate / 8000);
 784                fesettings->max_drift = 14 * fesettings->step_size;
 785        } else {
 786                fesettings->min_delay_ms = 200;
 787                fesettings->step_size = (p->symbol_rate / 8000);
 788                fesettings->max_drift = 18 * fesettings->step_size;
 789        }
 790
 791        return 0;
 792}
 793
 794static int s5h1420_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
 795{
 796        struct s5h1420_state* state = fe->demodulator_priv;
 797
 798        if (enable)
 799                return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
 800        else
 801                return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
 802}
 803
 804static int s5h1420_init (struct dvb_frontend* fe)
 805{
 806        struct s5h1420_state* state = fe->demodulator_priv;
 807
 808        /* disable power down and do reset */
 809        state->CON_1_val = state->config->serial_mpeg << 4;
 810        s5h1420_writereg(state, 0x02, state->CON_1_val);
 811        msleep(10);
 812        s5h1420_reset(state);
 813
 814        return 0;
 815}
 816
 817static int s5h1420_sleep(struct dvb_frontend* fe)
 818{
 819        struct s5h1420_state* state = fe->demodulator_priv;
 820        state->CON_1_val = 0x12;
 821        return s5h1420_writereg(state, 0x02, state->CON_1_val);
 822}
 823
 824static void s5h1420_release(struct dvb_frontend* fe)
 825{
 826        struct s5h1420_state* state = fe->demodulator_priv;
 827        i2c_del_adapter(&state->tuner_i2c_adapter);
 828        kfree(state);
 829}
 830
 831static u32 s5h1420_tuner_i2c_func(struct i2c_adapter *adapter)
 832{
 833        return I2C_FUNC_I2C;
 834}
 835
 836static int s5h1420_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
 837{
 838        struct s5h1420_state *state = i2c_get_adapdata(i2c_adap);
 839        struct i2c_msg m[1 + num];
 840        u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */
 841
 842        memset(m, 0, sizeof(struct i2c_msg) * (1 + num));
 843
 844        m[0].addr = state->config->demod_address;
 845        m[0].buf  = tx_open;
 846        m[0].len  = 2;
 847
 848        memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
 849
 850        return i2c_transfer(state->i2c, m, 1+num) == 1 + num ? num : -EIO;
 851}
 852
 853static struct i2c_algorithm s5h1420_tuner_i2c_algo = {
 854        .master_xfer   = s5h1420_tuner_i2c_tuner_xfer,
 855        .functionality = s5h1420_tuner_i2c_func,
 856};
 857
 858struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
 859{
 860        struct s5h1420_state *state = fe->demodulator_priv;
 861        return &state->tuner_i2c_adapter;
 862}
 863EXPORT_SYMBOL(s5h1420_get_tuner_i2c_adapter);
 864
 865static struct dvb_frontend_ops s5h1420_ops;
 866
 867struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
 868                                    struct i2c_adapter *i2c)
 869{
 870        /* allocate memory for the internal state */
 871        struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
 872        u8 i;
 873
 874        if (state == NULL)
 875                goto error;
 876
 877        /* setup the state */
 878        state->config = config;
 879        state->i2c = i2c;
 880        state->postlocked = 0;
 881        state->fclk = 88000000;
 882        state->tunedfreq = 0;
 883        state->fec_inner = FEC_NONE;
 884        state->symbol_rate = 0;
 885
 886        /* check if the demod is there + identify it */
 887        i = s5h1420_readreg(state, ID01);
 888        if (i != 0x03)
 889                goto error;
 890
 891        memset(state->shadow, 0xff, sizeof(state->shadow));
 892
 893        for (i = 0; i < 0x50; i++)
 894                state->shadow[i] = s5h1420_readreg(state, i);
 895
 896        /* create dvb_frontend */
 897        memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
 898        state->frontend.demodulator_priv = state;
 899
 900        /* create tuner i2c adapter */
 901        strlcpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus",
 902                sizeof(state->tuner_i2c_adapter.name));
 903        state->tuner_i2c_adapter.algo      = &s5h1420_tuner_i2c_algo;
 904        state->tuner_i2c_adapter.algo_data = NULL;
 905        i2c_set_adapdata(&state->tuner_i2c_adapter, state);
 906        if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
 907                printk(KERN_ERR "S5H1420/PN1010: tuner i2c bus could not be initialized\n");
 908                goto error;
 909        }
 910
 911        return &state->frontend;
 912
 913error:
 914        kfree(state);
 915        return NULL;
 916}
 917EXPORT_SYMBOL(s5h1420_attach);
 918
 919static struct dvb_frontend_ops s5h1420_ops = {
 920        .delsys = { SYS_DVBS },
 921        .info = {
 922                .name     = "Samsung S5H1420/PnpNetwork PN1010 DVB-S",
 923                .frequency_min    = 950000,
 924                .frequency_max    = 2150000,
 925                .frequency_stepsize = 125,     /* kHz for QPSK frontends */
 926                .frequency_tolerance  = 29500,
 927                .symbol_rate_min  = 1000000,
 928                .symbol_rate_max  = 45000000,
 929                /*  .symbol_rate_tolerance  = ???,*/
 930                .caps = FE_CAN_INVERSION_AUTO |
 931                FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 932                FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 933                FE_CAN_QPSK
 934        },
 935
 936        .release = s5h1420_release,
 937
 938        .init = s5h1420_init,
 939        .sleep = s5h1420_sleep,
 940        .i2c_gate_ctrl = s5h1420_i2c_gate_ctrl,
 941
 942        .set_frontend = s5h1420_set_frontend,
 943        .get_frontend = s5h1420_get_frontend,
 944        .get_tune_settings = s5h1420_get_tune_settings,
 945
 946        .read_status = s5h1420_read_status,
 947        .read_ber = s5h1420_read_ber,
 948        .read_signal_strength = s5h1420_read_signal_strength,
 949        .read_ucblocks = s5h1420_read_ucblocks,
 950
 951        .diseqc_send_master_cmd = s5h1420_send_master_cmd,
 952        .diseqc_recv_slave_reply = s5h1420_recv_slave_reply,
 953        .diseqc_send_burst = s5h1420_send_burst,
 954        .set_tone = s5h1420_set_tone,
 955        .set_voltage = s5h1420_set_voltage,
 956};
 957
 958MODULE_DESCRIPTION("Samsung S5H1420/PnpNetwork PN1010 DVB-S Demodulator driver");
 959MODULE_AUTHOR("Andrew de Quincey, Patrick Boettcher");
 960MODULE_LICENSE("GPL");
 961