LXR linux/drivers/media/platform/omap3isp/isp.h

   1/*
   2 * isp.h
   3 *
   4 * TI OMAP3 ISP - Core
   5 *
   6 * Copyright (C) 2009-2010 Nokia Corporation
   7 * Copyright (C) 2009 Texas Instruments, Inc.
   8 *
   9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10 *           Sakari Ailus <sakari.ailus@iki.fi>
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of the GNU General Public License version 2 as
  14 * published by the Free Software Foundation.
  15 *
  16 * This program is distributed in the hope that it will be useful, but
  17 * WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19 * General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  24 * 02110-1301 USA
  25 */
  26
  27#ifndef OMAP3_ISP_CORE_H
  28#define OMAP3_ISP_CORE_H
  29
  30#include <media/omap3isp.h>
  31#include <media/v4l2-device.h>
  32#include <linux/clk-provider.h>
  33#include <linux/device.h>
  34#include <linux/io.h>
  35#include <linux/iommu.h>
  36#include <linux/platform_device.h>
  37#include <linux/wait.h>
  38
  39#include "ispstat.h"
  40#include "ispccdc.h"
  41#include "ispreg.h"
  42#include "ispresizer.h"
  43#include "isppreview.h"
  44#include "ispcsiphy.h"
  45#include "ispcsi2.h"
  46#include "ispccp2.h"
  47
  48#define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8)
  49
  50#define ISP_TOK_TERM            0xFFFFFFFF      /*
  51                                                 * terminating token for ISP
  52                                                 * modules reg list
  53                                                 */
  54#define to_isp_device(ptr_module)                               \
  55        container_of(ptr_module, struct isp_device, isp_##ptr_module)
  56#define to_device(ptr_module)                                           \
  57        (to_isp_device(ptr_module)->dev)
  58
  59enum isp_mem_resources {
  60        OMAP3_ISP_IOMEM_MAIN,
  61        OMAP3_ISP_IOMEM_CCP2,
  62        OMAP3_ISP_IOMEM_CCDC,
  63        OMAP3_ISP_IOMEM_HIST,
  64        OMAP3_ISP_IOMEM_H3A,
  65        OMAP3_ISP_IOMEM_PREV,
  66        OMAP3_ISP_IOMEM_RESZ,
  67        OMAP3_ISP_IOMEM_SBL,
  68        OMAP3_ISP_IOMEM_CSI2A_REGS1,
  69        OMAP3_ISP_IOMEM_CSIPHY2,
  70        OMAP3_ISP_IOMEM_CSI2A_REGS2,
  71        OMAP3_ISP_IOMEM_CSI2C_REGS1,
  72        OMAP3_ISP_IOMEM_CSIPHY1,
  73        OMAP3_ISP_IOMEM_CSI2C_REGS2,
  74        OMAP3_ISP_IOMEM_343X_CONTROL_CSIRXFE,
  75        OMAP3_ISP_IOMEM_3630_CONTROL_CAMERA_PHY_CTRL,
  76        OMAP3_ISP_IOMEM_LAST
  77};
  78
  79enum isp_sbl_resource {
  80        OMAP3_ISP_SBL_CSI1_READ         = 0x1,
  81        OMAP3_ISP_SBL_CSI1_WRITE        = 0x2,
  82        OMAP3_ISP_SBL_CSI2A_WRITE       = 0x4,
  83        OMAP3_ISP_SBL_CSI2C_WRITE       = 0x8,
  84        OMAP3_ISP_SBL_CCDC_LSC_READ     = 0x10,
  85        OMAP3_ISP_SBL_CCDC_WRITE        = 0x20,
  86        OMAP3_ISP_SBL_PREVIEW_READ      = 0x40,
  87        OMAP3_ISP_SBL_PREVIEW_WRITE     = 0x80,
  88        OMAP3_ISP_SBL_RESIZER_READ      = 0x100,
  89        OMAP3_ISP_SBL_RESIZER_WRITE     = 0x200,
  90};
  91
  92enum isp_subclk_resource {
  93        OMAP3_ISP_SUBCLK_CCDC           = (1 << 0),
  94        OMAP3_ISP_SUBCLK_AEWB           = (1 << 1),
  95        OMAP3_ISP_SUBCLK_AF             = (1 << 2),
  96        OMAP3_ISP_SUBCLK_HIST           = (1 << 3),
  97        OMAP3_ISP_SUBCLK_PREVIEW        = (1 << 4),
  98        OMAP3_ISP_SUBCLK_RESIZER        = (1 << 5),
  99};
 100
 101/* ISP: OMAP 34xx ES 1.0 */
 102#define ISP_REVISION_1_0                0x10
 103/* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
 104#define ISP_REVISION_2_0                0x20
 105/* ISP2P: OMAP 36xx */
 106#define ISP_REVISION_15_0               0xF0
 107
 108/*
 109 * struct isp_res_mapping - Map ISP io resources to ISP revision.
 110 * @isp_rev: ISP_REVISION_x_x
 111 * @map: bitmap for enum isp_mem_resources
 112 */
 113struct isp_res_mapping {
 114        u32 isp_rev;
 115        u32 map;
 116};
 117
 118/*
 119 * struct isp_reg - Structure for ISP register values.
 120 * @reg: 32-bit Register address.
 121 * @val: 32-bit Register value.
 122 */
 123struct isp_reg {
 124        enum isp_mem_resources mmio_range;
 125        u32 reg;
 126        u32 val;
 127};
 128
 129enum isp_xclk_id {
 130        ISP_XCLK_A,
 131        ISP_XCLK_B,
 132};
 133
 134struct isp_xclk {
 135        struct isp_device *isp;
 136        struct clk_hw hw;
 137        struct clk_lookup *lookup;
 138        enum isp_xclk_id id;
 139
 140        spinlock_t lock;        /* Protects enabled and divider */
 141        bool enabled;
 142        unsigned int divider;
 143};
 144
 145/*
 146 * struct isp_device - ISP device structure.
 147 * @dev: Device pointer specific to the OMAP3 ISP.
 148 * @revision: Stores current ISP module revision.
 149 * @irq_num: Currently used IRQ number.
 150 * @mmio_base: Array with kernel base addresses for ioremapped ISP register
 151 *             regions.
 152 * @mmio_base_phys: Array with physical L4 bus addresses for ISP register
 153 *                  regions.
 154 * @mmio_size: Array with ISP register regions size in bytes.
 155 * @raw_dmamask: Raw DMA mask
 156 * @stat_lock: Spinlock for handling statistics
 157 * @isp_mutex: Mutex for serializing requests to ISP.
 158 * @crashed: Bitmask of crashed entities (indexed by entity ID)
 159 * @has_context: Context has been saved at least once and can be restored.
 160 * @ref_count: Reference count for handling multiple ISP requests.
 161 * @cam_ick: Pointer to camera interface clock structure.
 162 * @cam_mclk: Pointer to camera functional clock structure.
 163 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
 164 * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
 165 * @xclks: External clocks provided by the ISP
 166 * @irq: Currently attached ISP ISR callbacks information structure.
 167 * @isp_af: Pointer to current settings for ISP AutoFocus SCM.
 168 * @isp_hist: Pointer to current settings for ISP Histogram SCM.
 169 * @isp_h3a: Pointer to current settings for ISP Auto Exposure and
 170 *           White Balance SCM.
 171 * @isp_res: Pointer to current settings for ISP Resizer.
 172 * @isp_prev: Pointer to current settings for ISP Preview.
 173 * @isp_ccdc: Pointer to current settings for ISP CCDC.
 174 * @iommu: Pointer to requested IOMMU instance for ISP.
 175 * @platform_cb: ISP driver callback function pointers for platform code
 176 *
 177 * This structure is used to store the OMAP ISP Information.
 178 */
 179struct isp_device {
 180        struct v4l2_device v4l2_dev;
 181        struct media_device media_dev;
 182        struct device *dev;
 183        u32 revision;
 184
 185        /* platform HW resources */
 186        struct isp_platform_data *pdata;
 187        unsigned int irq_num;
 188
 189        void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
 190        unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST];
 191        resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST];
 192
 193        u64 raw_dmamask;
 194
 195        /* ISP Obj */
 196        spinlock_t stat_lock;   /* common lock for statistic drivers */
 197        struct mutex isp_mutex; /* For handling ref_count field */
 198        u32 crashed;
 199        int has_context;
 200        int ref_count;
 201        unsigned int autoidle;
 202#define ISP_CLK_CAM_ICK         0
 203#define ISP_CLK_CAM_MCLK        1
 204#define ISP_CLK_CSI2_FCK        2
 205#define ISP_CLK_L3_ICK          3
 206        struct clk *clock[4];
 207        struct isp_xclk xclks[2];
 208
 209        /* ISP modules */
 210        struct ispstat isp_af;
 211        struct ispstat isp_aewb;
 212        struct ispstat isp_hist;
 213        struct isp_res_device isp_res;
 214        struct isp_prev_device isp_prev;
 215        struct isp_ccdc_device isp_ccdc;
 216        struct isp_csi2_device isp_csi2a;
 217        struct isp_csi2_device isp_csi2c;
 218        struct isp_ccp2_device isp_ccp2;
 219        struct isp_csiphy isp_csiphy1;
 220        struct isp_csiphy isp_csiphy2;
 221
 222        unsigned int sbl_resources;
 223        unsigned int subclk_resources;
 224
 225        struct iommu_domain *domain;
 226};
 227
 228#define v4l2_dev_to_isp_device(dev) \
 229        container_of(dev, struct isp_device, v4l2_dev)
 230
 231void omap3isp_hist_dma_done(struct isp_device *isp);
 232
 233void omap3isp_flush(struct isp_device *isp);
 234
 235int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
 236                              atomic_t *stopping);
 237
 238int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
 239                                     atomic_t *stopping);
 240
 241int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
 242                                 enum isp_pipeline_stream_state state);
 243void omap3isp_configure_bridge(struct isp_device *isp,
 244                               enum ccdc_input_entity input,
 245                               const struct isp_parallel_platform_data *pdata,
 246                               unsigned int shift, unsigned int bridge);
 247
 248struct isp_device *omap3isp_get(struct isp_device *isp);
 249void omap3isp_put(struct isp_device *isp);
 250
 251void omap3isp_print_status(struct isp_device *isp);
 252
 253void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
 254void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
 255
 256void omap3isp_subclk_enable(struct isp_device *isp,
 257                            enum isp_subclk_resource res);
 258void omap3isp_subclk_disable(struct isp_device *isp,
 259                             enum isp_subclk_resource res);
 260
 261int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);
 262
 263int omap3isp_register_entities(struct platform_device *pdev,
 264                               struct v4l2_device *v4l2_dev);
 265void omap3isp_unregister_entities(struct platform_device *pdev);
 266
 267/*
 268 * isp_reg_readl - Read value of an OMAP3 ISP register
 269 * @dev: Device pointer specific to the OMAP3 ISP.
 270 * @isp_mmio_range: Range to which the register offset refers to.
 271 * @reg_offset: Register offset to read from.
 272 *
 273 * Returns an unsigned 32 bit value with the required register contents.
 274 */
 275static inline
 276u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
 277                  u32 reg_offset)
 278{
 279        return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
 280}
 281
 282/*
 283 * isp_reg_writel - Write value to an OMAP3 ISP register
 284 * @dev: Device pointer specific to the OMAP3 ISP.
 285 * @reg_value: 32 bit value to write to the register.
 286 * @isp_mmio_range: Range to which the register offset refers to.
 287 * @reg_offset: Register offset to write into.
 288 */
 289static inline
 290void isp_reg_writel(struct isp_device *isp, u32 reg_value,
 291                    enum isp_mem_resources isp_mmio_range, u32 reg_offset)
 292{
 293        __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
 294}
 295
 296/*
 297 * isp_reg_and - Clear individual bits in an OMAP3 ISP register
 298 * @dev: Device pointer specific to the OMAP3 ISP.
 299 * @mmio_range: Range to which the register offset refers to.
 300 * @reg: Register offset to work on.
 301 * @clr_bits: 32 bit value which would be cleared in the register.
 302 */
 303static inline
 304void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
 305                 u32 reg, u32 clr_bits)
 306{
 307        u32 v = isp_reg_readl(isp, mmio_range, reg);
 308
 309        isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
 310}
 311
 312/*
 313 * isp_reg_set - Set individual bits in an OMAP3 ISP register
 314 * @dev: Device pointer specific to the OMAP3 ISP.
 315 * @mmio_range: Range to which the register offset refers to.
 316 * @reg: Register offset to work on.
 317 * @set_bits: 32 bit value which would be set in the register.
 318 */
 319static inline
 320void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
 321                 u32 reg, u32 set_bits)
 322{
 323        u32 v = isp_reg_readl(isp, mmio_range, reg);
 324
 325        isp_reg_writel(isp, v | set_bits, mmio_range, reg);
 326}
 327
 328/*
 329 * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
 330 * @dev: Device pointer specific to the OMAP3 ISP.
 331 * @mmio_range: Range to which the register offset refers to.
 332 * @reg: Register offset to work on.
 333 * @clr_bits: 32 bit value which would be cleared in the register.
 334 * @set_bits: 32 bit value which would be set in the register.
 335 *
 336 * The clear operation is done first, and then the set operation.
 337 */
 338static inline
 339void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
 340                     u32 reg, u32 clr_bits, u32 set_bits)
 341{
 342        u32 v = isp_reg_readl(isp, mmio_range, reg);
 343
 344        isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
 345}
 346
 347static inline enum v4l2_buf_type
 348isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
 349{
 350        if (pad >= subdev->entity.num_pads)
 351                return 0;
 352
 353        if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
 354                return V4L2_BUF_TYPE_VIDEO_OUTPUT;
 355        else
 356                return V4L2_BUF_TYPE_VIDEO_CAPTURE;
 357}
 358
 359#endif  /* OMAP3_ISP_CORE_H */
 360