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19#ifndef BNX2X_SP_VERBS
20#define BNX2X_SP_VERBS
21
22struct bnx2x;
23struct eth_context;
24
25
26enum {
27 RAMROD_TX,
28 RAMROD_RX,
29
30 RAMROD_COMP_WAIT,
31
32 RAMROD_DRV_CLR_ONLY,
33
34 RAMROD_RESTORE,
35
36 RAMROD_EXEC,
37
38
39
40
41
42 RAMROD_CONT,
43
44
45
46
47
48 RAMROD_RETRY,
49};
50
51typedef enum {
52 BNX2X_OBJ_TYPE_RX,
53 BNX2X_OBJ_TYPE_TX,
54 BNX2X_OBJ_TYPE_RX_TX,
55} bnx2x_obj_type;
56
57
58enum {
59 BNX2X_FILTER_MAC_PENDING,
60 BNX2X_FILTER_VLAN_PENDING,
61 BNX2X_FILTER_VLAN_MAC_PENDING,
62 BNX2X_FILTER_RX_MODE_PENDING,
63 BNX2X_FILTER_RX_MODE_SCHED,
64 BNX2X_FILTER_ISCSI_ETH_START_SCHED,
65 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
66 BNX2X_FILTER_FCOE_ETH_START_SCHED,
67 BNX2X_FILTER_FCOE_ETH_STOP_SCHED,
68 BNX2X_FILTER_MCAST_PENDING,
69 BNX2X_FILTER_MCAST_SCHED,
70 BNX2X_FILTER_RSS_CONF_PENDING,
71 BNX2X_AFEX_FCOE_Q_UPDATE_PENDING,
72 BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
73};
74
75struct bnx2x_raw_obj {
76 u8 func_id;
77
78
79 u8 cl_id;
80 u32 cid;
81
82
83 void *rdata;
84 dma_addr_t rdata_mapping;
85
86
87 int state;
88 unsigned long *pstate;
89
90 bnx2x_obj_type obj_type;
91
92 int (*wait_comp)(struct bnx2x *bp,
93 struct bnx2x_raw_obj *o);
94
95 bool (*check_pending)(struct bnx2x_raw_obj *o);
96 void (*clear_pending)(struct bnx2x_raw_obj *o);
97 void (*set_pending)(struct bnx2x_raw_obj *o);
98};
99
100
101struct bnx2x_mac_ramrod_data {
102 u8 mac[ETH_ALEN];
103 u8 is_inner_mac;
104};
105
106struct bnx2x_vlan_ramrod_data {
107 u16 vlan;
108};
109
110struct bnx2x_vlan_mac_ramrod_data {
111 u8 mac[ETH_ALEN];
112 u8 is_inner_mac;
113 u16 vlan;
114};
115
116union bnx2x_classification_ramrod_data {
117 struct bnx2x_mac_ramrod_data mac;
118 struct bnx2x_vlan_ramrod_data vlan;
119 struct bnx2x_vlan_mac_ramrod_data vlan_mac;
120};
121
122
123enum bnx2x_vlan_mac_cmd {
124 BNX2X_VLAN_MAC_ADD,
125 BNX2X_VLAN_MAC_DEL,
126 BNX2X_VLAN_MAC_MOVE,
127};
128
129struct bnx2x_vlan_mac_data {
130
131 enum bnx2x_vlan_mac_cmd cmd;
132
133
134
135
136 unsigned long vlan_mac_flags;
137
138
139 struct bnx2x_vlan_mac_obj *target_obj;
140
141 union bnx2x_classification_ramrod_data u;
142};
143
144
145union bnx2x_exe_queue_cmd_data {
146 struct bnx2x_vlan_mac_data vlan_mac;
147
148 struct {
149
150 } mcast;
151};
152
153struct bnx2x_exeq_elem {
154 struct list_head link;
155
156
157 int cmd_len;
158
159 union bnx2x_exe_queue_cmd_data cmd_data;
160};
161
162union bnx2x_qable_obj;
163
164union bnx2x_exeq_comp_elem {
165 union event_ring_elem *elem;
166};
167
168struct bnx2x_exe_queue_obj;
169
170typedef int (*exe_q_validate)(struct bnx2x *bp,
171 union bnx2x_qable_obj *o,
172 struct bnx2x_exeq_elem *elem);
173
174typedef int (*exe_q_remove)(struct bnx2x *bp,
175 union bnx2x_qable_obj *o,
176 struct bnx2x_exeq_elem *elem);
177
178
179
180
181typedef int (*exe_q_optimize)(struct bnx2x *bp,
182 union bnx2x_qable_obj *o,
183 struct bnx2x_exeq_elem *elem);
184typedef int (*exe_q_execute)(struct bnx2x *bp,
185 union bnx2x_qable_obj *o,
186 struct list_head *exe_chunk,
187 unsigned long *ramrod_flags);
188typedef struct bnx2x_exeq_elem *
189 (*exe_q_get)(struct bnx2x_exe_queue_obj *o,
190 struct bnx2x_exeq_elem *elem);
191
192struct bnx2x_exe_queue_obj {
193
194
195
196 struct list_head exe_queue;
197
198
199
200
201 struct list_head pending_comp;
202
203 spinlock_t lock;
204
205
206 int exe_chunk_len;
207
208 union bnx2x_qable_obj *owner;
209
210
211
212
213
214
215
216
217 exe_q_validate validate;
218
219
220
221
222
223 exe_q_remove remove;
224
225
226
227
228
229
230
231
232
233 exe_q_optimize optimize;
234
235
236
237
238 exe_q_execute execute;
239
240
241
242
243
244 exe_q_get get;
245};
246
247
248
249
250
251struct bnx2x_vlan_mac_registry_elem {
252 struct list_head link;
253
254
255
256
257
258
259 int cam_offset;
260
261
262 unsigned long vlan_mac_flags;
263
264 union bnx2x_classification_ramrod_data u;
265};
266
267
268enum {
269 BNX2X_UC_LIST_MAC,
270 BNX2X_ETH_MAC,
271 BNX2X_ISCSI_ETH_MAC,
272 BNX2X_NETQ_ETH_MAC,
273 BNX2X_DONT_CONSUME_CAM_CREDIT,
274 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
275};
276
277struct bnx2x_vlan_mac_ramrod_params {
278
279 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
280
281
282 unsigned long ramrod_flags;
283
284
285 struct bnx2x_vlan_mac_data user_req;
286};
287
288struct bnx2x_vlan_mac_obj {
289 struct bnx2x_raw_obj raw;
290
291
292
293
294 struct list_head head;
295
296
297 struct bnx2x_exe_queue_obj exe_queue;
298
299
300 struct bnx2x_credit_pool_obj *macs_pool;
301
302
303 struct bnx2x_credit_pool_obj *vlans_pool;
304
305
306 int ramrod_cmd;
307
308
309
310
311
312
313
314
315
316
317
318 int (*get_n_elements)(struct bnx2x *bp,
319 struct bnx2x_vlan_mac_obj *o, int n, u8 *base,
320 u8 stride, u8 size);
321
322
323
324
325
326
327
328 int (*check_add)(struct bnx2x *bp,
329 struct bnx2x_vlan_mac_obj *o,
330 union bnx2x_classification_ramrod_data *data);
331
332
333
334
335
336
337 struct bnx2x_vlan_mac_registry_elem *
338 (*check_del)(struct bnx2x *bp,
339 struct bnx2x_vlan_mac_obj *o,
340 union bnx2x_classification_ramrod_data *data);
341
342
343
344
345
346
347 bool (*check_move)(struct bnx2x *bp,
348 struct bnx2x_vlan_mac_obj *src_o,
349 struct bnx2x_vlan_mac_obj *dst_o,
350 union bnx2x_classification_ramrod_data *data);
351
352
353
354
355
356 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o);
357 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o);
358 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset);
359 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset);
360
361
362
363
364 void (*set_one_rule)(struct bnx2x *bp,
365 struct bnx2x_vlan_mac_obj *o,
366 struct bnx2x_exeq_elem *elem, int rule_idx,
367 int cam_offset);
368
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381
382
383
384
385
386 int (*delete_all)(struct bnx2x *bp,
387 struct bnx2x_vlan_mac_obj *o,
388 unsigned long *vlan_mac_flags,
389 unsigned long *ramrod_flags);
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406 int (*restore)(struct bnx2x *bp,
407 struct bnx2x_vlan_mac_ramrod_params *p,
408 struct bnx2x_vlan_mac_registry_elem **ppos);
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
428 union event_ring_elem *cqe,
429 unsigned long *ramrod_flags);
430
431
432
433
434
435
436 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o);
437};
438
439enum {
440 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0,
441 BNX2X_LLH_CAM_ETH_LINE,
442 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
443};
444
445void bnx2x_set_mac_in_nig(struct bnx2x *bp,
446 bool add, unsigned char *dev_addr, int index);
447
448
449
450
451
452
453enum {
454 BNX2X_RX_MODE_FCOE_ETH,
455 BNX2X_RX_MODE_ISCSI_ETH,
456};
457
458enum {
459 BNX2X_ACCEPT_UNICAST,
460 BNX2X_ACCEPT_MULTICAST,
461 BNX2X_ACCEPT_ALL_UNICAST,
462 BNX2X_ACCEPT_ALL_MULTICAST,
463 BNX2X_ACCEPT_BROADCAST,
464 BNX2X_ACCEPT_UNMATCHED,
465 BNX2X_ACCEPT_ANY_VLAN
466};
467
468struct bnx2x_rx_mode_ramrod_params {
469 struct bnx2x_rx_mode_obj *rx_mode_obj;
470 unsigned long *pstate;
471 int state;
472 u8 cl_id;
473 u32 cid;
474 u8 func_id;
475 unsigned long ramrod_flags;
476 unsigned long rx_mode_flags;
477
478
479
480
481
482 void *rdata;
483 dma_addr_t rdata_mapping;
484
485
486 unsigned long rx_accept_flags;
487
488
489 unsigned long tx_accept_flags;
490};
491
492struct bnx2x_rx_mode_obj {
493 int (*config_rx_mode)(struct bnx2x *bp,
494 struct bnx2x_rx_mode_ramrod_params *p);
495
496 int (*wait_comp)(struct bnx2x *bp,
497 struct bnx2x_rx_mode_ramrod_params *p);
498};
499
500
501
502struct bnx2x_mcast_list_elem {
503 struct list_head link;
504 u8 *mac;
505};
506
507union bnx2x_mcast_config_data {
508 u8 *mac;
509 u8 bin;
510};
511
512struct bnx2x_mcast_ramrod_params {
513 struct bnx2x_mcast_obj *mcast_obj;
514
515
516 unsigned long ramrod_flags;
517
518 struct list_head mcast_list;
519
520
521
522
523
524
525
526
527 int mcast_list_len;
528};
529
530enum bnx2x_mcast_cmd {
531 BNX2X_MCAST_CMD_ADD,
532 BNX2X_MCAST_CMD_CONT,
533 BNX2X_MCAST_CMD_DEL,
534 BNX2X_MCAST_CMD_RESTORE,
535};
536
537struct bnx2x_mcast_obj {
538 struct bnx2x_raw_obj raw;
539
540 union {
541 struct {
542 #define BNX2X_MCAST_BINS_NUM 256
543 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64)
544 u64 vec[BNX2X_MCAST_VEC_SZ];
545
546
547
548
549
550 int num_bins_set;
551 } aprox_match;
552
553 struct {
554 struct list_head macs;
555 int num_macs_set;
556 } exact_match;
557 } registry;
558
559
560 struct list_head pending_cmds_head;
561
562
563 int sched_state;
564
565
566 int max_cmd_len;
567
568
569
570
571 int total_pending_num;
572
573 u8 engine_id;
574
575
576
577
578 int (*config_mcast)(struct bnx2x *bp,
579 struct bnx2x_mcast_ramrod_params *p,
580 enum bnx2x_mcast_cmd cmd);
581
582
583
584
585
586
587
588
589
590
591
592
593 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
594 int start_bin, int *rdata_idx);
595
596 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
597 struct bnx2x_mcast_ramrod_params *p,
598 enum bnx2x_mcast_cmd cmd);
599
600 void (*set_one_rule)(struct bnx2x *bp,
601 struct bnx2x_mcast_obj *o, int idx,
602 union bnx2x_mcast_config_data *cfg_data,
603 enum bnx2x_mcast_cmd cmd);
604
605
606
607
608 bool (*check_pending)(struct bnx2x_mcast_obj *o);
609
610
611
612
613 void (*set_sched)(struct bnx2x_mcast_obj *o);
614 void (*clear_sched)(struct bnx2x_mcast_obj *o);
615 bool (*check_sched)(struct bnx2x_mcast_obj *o);
616
617
618 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o);
619
620
621
622
623
624
625 int (*validate)(struct bnx2x *bp,
626 struct bnx2x_mcast_ramrod_params *p,
627 enum bnx2x_mcast_cmd cmd);
628
629
630
631
632 void (*revert)(struct bnx2x *bp,
633 struct bnx2x_mcast_ramrod_params *p,
634 int old_num_bins);
635
636 int (*get_registry_size)(struct bnx2x_mcast_obj *o);
637 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n);
638};
639
640
641struct bnx2x_credit_pool_obj {
642
643
644 atomic_t credit;
645
646
647 int pool_sz;
648
649
650
651
652
653
654
655
656#define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64)
657 u64 pool_mirror[BNX2X_POOL_VEC_SIZE];
658
659
660 int base_pool_offset;
661
662
663
664
665
666
667 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry);
668
669
670
671
672
673
674
675 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry);
676
677
678
679
680
681
682
683 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt);
684
685
686
687
688
689
690
691 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt);
692
693
694
695
696 int (*check)(struct bnx2x_credit_pool_obj *o);
697};
698
699
700enum {
701
702 BNX2X_RSS_MODE_DISABLED,
703 BNX2X_RSS_MODE_REGULAR,
704
705 BNX2X_RSS_SET_SRCH,
706
707 BNX2X_RSS_IPV4,
708 BNX2X_RSS_IPV4_TCP,
709 BNX2X_RSS_IPV4_UDP,
710 BNX2X_RSS_IPV6,
711 BNX2X_RSS_IPV6_TCP,
712 BNX2X_RSS_IPV6_UDP,
713};
714
715struct bnx2x_config_rss_params {
716 struct bnx2x_rss_config_obj *rss_obj;
717
718
719 unsigned long ramrod_flags;
720
721
722 unsigned long rss_flags;
723
724
725 u8 rss_result_mask;
726
727
728 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
729
730
731 u32 rss_key[10];
732
733
734 u16 toe_rss_bitmap;
735};
736
737struct bnx2x_rss_config_obj {
738 struct bnx2x_raw_obj raw;
739
740
741 u8 engine_id;
742
743
744 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
745
746
747 u8 udp_rss_v4;
748 u8 udp_rss_v6;
749
750 int (*config_rss)(struct bnx2x *bp,
751 struct bnx2x_config_rss_params *p);
752};
753
754
755
756
757enum {
758 BNX2X_Q_UPDATE_IN_VLAN_REM,
759 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
760 BNX2X_Q_UPDATE_OUT_VLAN_REM,
761 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
762 BNX2X_Q_UPDATE_ANTI_SPOOF,
763 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG,
764 BNX2X_Q_UPDATE_ACTIVATE,
765 BNX2X_Q_UPDATE_ACTIVATE_CHNG,
766 BNX2X_Q_UPDATE_DEF_VLAN_EN,
767 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
768 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
769 BNX2X_Q_UPDATE_SILENT_VLAN_REM
770};
771
772
773enum bnx2x_q_state {
774 BNX2X_Q_STATE_RESET,
775 BNX2X_Q_STATE_INITIALIZED,
776 BNX2X_Q_STATE_ACTIVE,
777 BNX2X_Q_STATE_MULTI_COS,
778 BNX2X_Q_STATE_MCOS_TERMINATED,
779 BNX2X_Q_STATE_INACTIVE,
780 BNX2X_Q_STATE_STOPPED,
781 BNX2X_Q_STATE_TERMINATED,
782 BNX2X_Q_STATE_FLRED,
783 BNX2X_Q_STATE_MAX,
784};
785
786
787enum bnx2x_q_logical_state {
788 BNX2X_Q_LOGICAL_STATE_ACTIVE,
789 BNX2X_Q_LOGICAL_STATE_STOPPED,
790};
791
792
793enum bnx2x_queue_cmd {
794 BNX2X_Q_CMD_INIT,
795 BNX2X_Q_CMD_SETUP,
796 BNX2X_Q_CMD_SETUP_TX_ONLY,
797 BNX2X_Q_CMD_DEACTIVATE,
798 BNX2X_Q_CMD_ACTIVATE,
799 BNX2X_Q_CMD_UPDATE,
800 BNX2X_Q_CMD_UPDATE_TPA,
801 BNX2X_Q_CMD_HALT,
802 BNX2X_Q_CMD_CFC_DEL,
803 BNX2X_Q_CMD_TERMINATE,
804 BNX2X_Q_CMD_EMPTY,
805 BNX2X_Q_CMD_MAX,
806};
807
808
809enum {
810 BNX2X_Q_FLG_TPA,
811 BNX2X_Q_FLG_TPA_IPV6,
812 BNX2X_Q_FLG_TPA_GRO,
813 BNX2X_Q_FLG_STATS,
814 BNX2X_Q_FLG_ZERO_STATS,
815 BNX2X_Q_FLG_ACTIVE,
816 BNX2X_Q_FLG_OV,
817 BNX2X_Q_FLG_VLAN,
818 BNX2X_Q_FLG_COS,
819 BNX2X_Q_FLG_HC,
820 BNX2X_Q_FLG_HC_EN,
821 BNX2X_Q_FLG_DHC,
822 BNX2X_Q_FLG_FCOE,
823 BNX2X_Q_FLG_LEADING_RSS,
824 BNX2X_Q_FLG_MCAST,
825 BNX2X_Q_FLG_DEF_VLAN,
826 BNX2X_Q_FLG_TX_SWITCH,
827 BNX2X_Q_FLG_TX_SEC,
828 BNX2X_Q_FLG_ANTI_SPOOF,
829 BNX2X_Q_FLG_SILENT_VLAN_REM,
830 BNX2X_Q_FLG_FORCE_DEFAULT_PRI,
831 BNX2X_Q_FLG_PCSUM_ON_PKT,
832 BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
833};
834
835
836enum bnx2x_q_type {
837
838
839
840 BNX2X_Q_TYPE_HAS_RX,
841 BNX2X_Q_TYPE_HAS_TX,
842};
843
844#define BNX2X_PRIMARY_CID_INDEX 0
845#define BNX2X_MULTI_TX_COS_E1X 3
846#define BNX2X_MULTI_TX_COS_E2_E3A0 2
847#define BNX2X_MULTI_TX_COS_E3B0 3
848#define BNX2X_MULTI_TX_COS 3
849
850#define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
851
852struct bnx2x_queue_init_params {
853 struct {
854 unsigned long flags;
855 u16 hc_rate;
856 u8 fw_sb_id;
857 u8 sb_cq_index;
858 } tx;
859
860 struct {
861 unsigned long flags;
862 u16 hc_rate;
863 u8 fw_sb_id;
864 u8 sb_cq_index;
865 } rx;
866
867
868 struct eth_context *cxts[BNX2X_MULTI_TX_COS];
869
870
871 u8 max_cos;
872};
873
874struct bnx2x_queue_terminate_params {
875
876 u8 cid_index;
877};
878
879struct bnx2x_queue_cfc_del_params {
880
881 u8 cid_index;
882};
883
884struct bnx2x_queue_update_params {
885 unsigned long update_flags;
886 u16 def_vlan;
887 u16 silent_removal_value;
888 u16 silent_removal_mask;
889
890 u8 cid_index;
891};
892
893struct rxq_pause_params {
894 u16 bd_th_lo;
895 u16 bd_th_hi;
896 u16 rcq_th_lo;
897 u16 rcq_th_hi;
898 u16 sge_th_lo;
899 u16 sge_th_hi;
900 u16 pri_map;
901};
902
903
904struct bnx2x_general_setup_params {
905
906 u8 stat_id;
907
908 u8 spcl_id;
909 u16 mtu;
910 u8 cos;
911};
912
913struct bnx2x_rxq_setup_params {
914
915 dma_addr_t dscr_map;
916 dma_addr_t sge_map;
917 dma_addr_t rcq_map;
918 dma_addr_t rcq_np_map;
919
920 u16 drop_flags;
921 u16 buf_sz;
922 u8 fw_sb_id;
923 u8 cl_qzone_id;
924
925
926 u16 tpa_agg_sz;
927 u16 sge_buf_sz;
928 u8 max_sges_pkt;
929 u8 max_tpa_queues;
930 u8 rss_engine_id;
931
932
933 u8 mcast_engine_id;
934
935 u8 cache_line_log;
936
937 u8 sb_cq_index;
938
939
940 u16 silent_removal_value;
941 u16 silent_removal_mask;
942};
943
944struct bnx2x_txq_setup_params {
945
946 dma_addr_t dscr_map;
947
948 u8 fw_sb_id;
949 u8 sb_cq_index;
950 u8 cos;
951 u16 traffic_type;
952
953 u8 tss_leading_cl_id;
954
955
956 u16 default_vlan;
957};
958
959struct bnx2x_queue_setup_params {
960 struct bnx2x_general_setup_params gen_params;
961 struct bnx2x_txq_setup_params txq_params;
962 struct bnx2x_rxq_setup_params rxq_params;
963 struct rxq_pause_params pause_params;
964 unsigned long flags;
965};
966
967struct bnx2x_queue_setup_tx_only_params {
968 struct bnx2x_general_setup_params gen_params;
969 struct bnx2x_txq_setup_params txq_params;
970 unsigned long flags;
971
972 u8 cid_index;
973};
974
975struct bnx2x_queue_state_params {
976 struct bnx2x_queue_sp_obj *q_obj;
977
978
979 enum bnx2x_queue_cmd cmd;
980
981
982 unsigned long ramrod_flags;
983
984
985 union {
986 struct bnx2x_queue_update_params update;
987 struct bnx2x_queue_setup_params setup;
988 struct bnx2x_queue_init_params init;
989 struct bnx2x_queue_setup_tx_only_params tx_only;
990 struct bnx2x_queue_terminate_params terminate;
991 struct bnx2x_queue_cfc_del_params cfc_del;
992 } params;
993};
994
995struct bnx2x_viflist_params {
996 u8 echo_res;
997 u8 func_bit_map_res;
998};
999
1000struct bnx2x_queue_sp_obj {
1001 u32 cids[BNX2X_MULTI_TX_COS];
1002 u8 cl_id;
1003 u8 func_id;
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014 u8 max_cos;
1015 u8 num_tx_only, next_tx_only;
1016
1017 enum bnx2x_q_state state, next_state;
1018
1019
1020 unsigned long type;
1021
1022
1023
1024
1025
1026
1027 unsigned long pending;
1028
1029
1030 void *rdata;
1031 dma_addr_t rdata_mapping;
1032
1033
1034
1035
1036
1037
1038 int (*send_cmd)(struct bnx2x *bp,
1039 struct bnx2x_queue_state_params *params);
1040
1041
1042
1043
1044 int (*set_pending)(struct bnx2x_queue_sp_obj *o,
1045 struct bnx2x_queue_state_params *params);
1046
1047
1048
1049
1050 int (*check_transition)(struct bnx2x *bp,
1051 struct bnx2x_queue_sp_obj *o,
1052 struct bnx2x_queue_state_params *params);
1053
1054
1055
1056
1057 int (*complete_cmd)(struct bnx2x *bp,
1058 struct bnx2x_queue_sp_obj *o,
1059 enum bnx2x_queue_cmd);
1060
1061 int (*wait_comp)(struct bnx2x *bp,
1062 struct bnx2x_queue_sp_obj *o,
1063 enum bnx2x_queue_cmd cmd);
1064};
1065
1066
1067
1068enum bnx2x_func_state {
1069 BNX2X_F_STATE_RESET,
1070 BNX2X_F_STATE_INITIALIZED,
1071 BNX2X_F_STATE_STARTED,
1072 BNX2X_F_STATE_TX_STOPPED,
1073 BNX2X_F_STATE_MAX,
1074};
1075
1076
1077enum bnx2x_func_cmd {
1078 BNX2X_F_CMD_HW_INIT,
1079 BNX2X_F_CMD_START,
1080 BNX2X_F_CMD_STOP,
1081 BNX2X_F_CMD_HW_RESET,
1082 BNX2X_F_CMD_AFEX_UPDATE,
1083 BNX2X_F_CMD_AFEX_VIFLISTS,
1084 BNX2X_F_CMD_TX_STOP,
1085 BNX2X_F_CMD_TX_START,
1086 BNX2X_F_CMD_SWITCH_UPDATE,
1087 BNX2X_F_CMD_MAX,
1088};
1089
1090struct bnx2x_func_hw_init_params {
1091
1092
1093
1094
1095
1096
1097
1098
1099 u32 load_phase;
1100};
1101
1102struct bnx2x_func_hw_reset_params {
1103
1104
1105
1106
1107
1108
1109
1110
1111 u32 reset_phase;
1112};
1113
1114struct bnx2x_func_start_params {
1115
1116
1117
1118
1119
1120 u16 mf_mode;
1121
1122
1123 u16 sd_vlan_tag;
1124
1125
1126 u8 network_cos_mode;
1127
1128
1129 u8 nvgre_clss_en;
1130
1131
1132 u8 gre_tunnel_mode;
1133
1134
1135 u8 gre_tunnel_rss;
1136};
1137
1138struct bnx2x_func_switch_update_params {
1139 u8 suspend;
1140};
1141
1142struct bnx2x_func_afex_update_params {
1143 u16 vif_id;
1144 u16 afex_default_vlan;
1145 u8 allowed_priorities;
1146};
1147
1148struct bnx2x_func_afex_viflists_params {
1149 u16 vif_list_index;
1150 u8 func_bit_map;
1151 u8 afex_vif_list_command;
1152 u8 func_to_clear;
1153};
1154struct bnx2x_func_tx_start_params {
1155 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1156 u8 dcb_enabled;
1157 u8 dcb_version;
1158 u8 dont_add_pri_0_en;
1159};
1160
1161struct bnx2x_func_state_params {
1162 struct bnx2x_func_sp_obj *f_obj;
1163
1164
1165 enum bnx2x_func_cmd cmd;
1166
1167
1168 unsigned long ramrod_flags;
1169
1170
1171 union {
1172 struct bnx2x_func_hw_init_params hw_init;
1173 struct bnx2x_func_hw_reset_params hw_reset;
1174 struct bnx2x_func_start_params start;
1175 struct bnx2x_func_switch_update_params switch_update;
1176 struct bnx2x_func_afex_update_params afex_update;
1177 struct bnx2x_func_afex_viflists_params afex_viflists;
1178 struct bnx2x_func_tx_start_params tx_start;
1179 } params;
1180};
1181
1182struct bnx2x_func_sp_drv_ops {
1183
1184
1185
1186
1187
1188
1189 int (*init_hw_cmn_chip)(struct bnx2x *bp);
1190 int (*init_hw_cmn)(struct bnx2x *bp);
1191 int (*init_hw_port)(struct bnx2x *bp);
1192 int (*init_hw_func)(struct bnx2x *bp);
1193
1194
1195 void (*reset_hw_cmn)(struct bnx2x *bp);
1196 void (*reset_hw_port)(struct bnx2x *bp);
1197 void (*reset_hw_func)(struct bnx2x *bp);
1198
1199
1200 int (*gunzip_init)(struct bnx2x *bp);
1201 void (*gunzip_end)(struct bnx2x *bp);
1202
1203
1204 int (*init_fw)(struct bnx2x *bp);
1205 void (*release_fw)(struct bnx2x *bp);
1206};
1207
1208struct bnx2x_func_sp_obj {
1209 enum bnx2x_func_state state, next_state;
1210
1211
1212
1213
1214
1215
1216 unsigned long pending;
1217
1218
1219 void *rdata;
1220 dma_addr_t rdata_mapping;
1221
1222
1223
1224
1225
1226 void *afex_rdata;
1227 dma_addr_t afex_rdata_mapping;
1228
1229
1230
1231
1232 struct mutex one_pending_mutex;
1233
1234
1235 struct bnx2x_func_sp_drv_ops *drv;
1236
1237
1238
1239
1240
1241
1242 int (*send_cmd)(struct bnx2x *bp,
1243 struct bnx2x_func_state_params *params);
1244
1245
1246
1247
1248 int (*check_transition)(struct bnx2x *bp,
1249 struct bnx2x_func_sp_obj *o,
1250 struct bnx2x_func_state_params *params);
1251
1252
1253
1254
1255 int (*complete_cmd)(struct bnx2x *bp,
1256 struct bnx2x_func_sp_obj *o,
1257 enum bnx2x_func_cmd cmd);
1258
1259 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o,
1260 enum bnx2x_func_cmd cmd);
1261};
1262
1263
1264
1265union bnx2x_qable_obj {
1266 struct bnx2x_vlan_mac_obj vlan_mac;
1267};
1268
1269void bnx2x_init_func_obj(struct bnx2x *bp,
1270 struct bnx2x_func_sp_obj *obj,
1271 void *rdata, dma_addr_t rdata_mapping,
1272 void *afex_rdata, dma_addr_t afex_rdata_mapping,
1273 struct bnx2x_func_sp_drv_ops *drv_iface);
1274
1275int bnx2x_func_state_change(struct bnx2x *bp,
1276 struct bnx2x_func_state_params *params);
1277
1278enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
1279 struct bnx2x_func_sp_obj *o);
1280
1281void bnx2x_init_queue_obj(struct bnx2x *bp,
1282 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids,
1283 u8 cid_cnt, u8 func_id, void *rdata,
1284 dma_addr_t rdata_mapping, unsigned long type);
1285
1286int bnx2x_queue_state_change(struct bnx2x *bp,
1287 struct bnx2x_queue_state_params *params);
1288
1289int bnx2x_get_q_logical_state(struct bnx2x *bp,
1290 struct bnx2x_queue_sp_obj *obj);
1291
1292
1293void bnx2x_init_mac_obj(struct bnx2x *bp,
1294 struct bnx2x_vlan_mac_obj *mac_obj,
1295 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1296 dma_addr_t rdata_mapping, int state,
1297 unsigned long *pstate, bnx2x_obj_type type,
1298 struct bnx2x_credit_pool_obj *macs_pool);
1299
1300void bnx2x_init_vlan_obj(struct bnx2x *bp,
1301 struct bnx2x_vlan_mac_obj *vlan_obj,
1302 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1303 dma_addr_t rdata_mapping, int state,
1304 unsigned long *pstate, bnx2x_obj_type type,
1305 struct bnx2x_credit_pool_obj *vlans_pool);
1306
1307void bnx2x_init_vlan_mac_obj(struct bnx2x *bp,
1308 struct bnx2x_vlan_mac_obj *vlan_mac_obj,
1309 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1310 dma_addr_t rdata_mapping, int state,
1311 unsigned long *pstate, bnx2x_obj_type type,
1312 struct bnx2x_credit_pool_obj *macs_pool,
1313 struct bnx2x_credit_pool_obj *vlans_pool);
1314
1315int bnx2x_config_vlan_mac(struct bnx2x *bp,
1316 struct bnx2x_vlan_mac_ramrod_params *p);
1317
1318int bnx2x_vlan_mac_move(struct bnx2x *bp,
1319 struct bnx2x_vlan_mac_ramrod_params *p,
1320 struct bnx2x_vlan_mac_obj *dest_o);
1321
1322
1323
1324void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
1325 struct bnx2x_rx_mode_obj *o);
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336int bnx2x_config_rx_mode(struct bnx2x *bp,
1337 struct bnx2x_rx_mode_ramrod_params *p);
1338
1339
1340
1341void bnx2x_init_mcast_obj(struct bnx2x *bp,
1342 struct bnx2x_mcast_obj *mcast_obj,
1343 u8 mcast_cl_id, u32 mcast_cid, u8 func_id,
1344 u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
1345 int state, unsigned long *pstate,
1346 bnx2x_obj_type type);
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368int bnx2x_config_mcast(struct bnx2x *bp,
1369 struct bnx2x_mcast_ramrod_params *p,
1370 enum bnx2x_mcast_cmd cmd);
1371
1372
1373void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
1374 struct bnx2x_credit_pool_obj *p, u8 func_id,
1375 u8 func_num);
1376void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
1377 struct bnx2x_credit_pool_obj *p, u8 func_id,
1378 u8 func_num);
1379
1380
1381
1382void bnx2x_init_rss_config_obj(struct bnx2x *bp,
1383 struct bnx2x_rss_config_obj *rss_obj,
1384 u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
1385 void *rdata, dma_addr_t rdata_mapping,
1386 int state, unsigned long *pstate,
1387 bnx2x_obj_type type);
1388
1389
1390
1391
1392
1393
1394int bnx2x_config_rss(struct bnx2x *bp,
1395 struct bnx2x_config_rss_params *p);
1396
1397
1398
1399
1400
1401
1402
1403
1404void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
1405 u8 *ind_table);
1406
1407#endif
1408