1
2
3
4
5
6
7
8
9
10
11
12#ifndef CNIC_H
13#define CNIC_H
14
15#define HC_INDEX_ISCSI_EQ_CONS 6
16
17#define HC_INDEX_FCOE_EQ_CONS 3
18
19#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
20#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
21
22#define KWQ_PAGE_CNT 4
23#define KCQ_PAGE_CNT 16
24
25#define KWQ_CID 24
26#define KCQ_CID 25
27
28
29
30
31#define L5_KRNLQ_FLAGS 0x00000000
32#define L5_KRNLQ_SIZE 0x00000000
33#define L5_KRNLQ_TYPE 0x00000000
34#define KRNLQ_FLAGS_PG_SZ (0xf<<0)
35#define KRNLQ_FLAGS_PG_SZ_256 (0<<0)
36#define KRNLQ_FLAGS_PG_SZ_512 (1<<0)
37#define KRNLQ_FLAGS_PG_SZ_1K (2<<0)
38#define KRNLQ_FLAGS_PG_SZ_2K (3<<0)
39#define KRNLQ_FLAGS_PG_SZ_4K (4<<0)
40#define KRNLQ_FLAGS_PG_SZ_8K (5<<0)
41#define KRNLQ_FLAGS_PG_SZ_16K (6<<0)
42#define KRNLQ_FLAGS_PG_SZ_32K (7<<0)
43#define KRNLQ_FLAGS_PG_SZ_64K (8<<0)
44#define KRNLQ_FLAGS_PG_SZ_128K (9<<0)
45#define KRNLQ_FLAGS_PG_SZ_256K (10<<0)
46#define KRNLQ_FLAGS_PG_SZ_512K (11<<0)
47#define KRNLQ_FLAGS_PG_SZ_1M (12<<0)
48#define KRNLQ_FLAGS_PG_SZ_2M (13<<0)
49#define KRNLQ_FLAGS_QE_SELF_SEQ (1<<15)
50#define KRNLQ_SIZE_TYPE_SIZE ((((0x28 + 0x1f) & ~0x1f) / 0x20) << 16)
51#define KRNLQ_TYPE_TYPE (0xf<<28)
52#define KRNLQ_TYPE_TYPE_EMPTY (0<<28)
53#define KRNLQ_TYPE_TYPE_KRNLQ (6<<28)
54
55#define L5_KRNLQ_HOST_QIDX 0x00000004
56#define L5_KRNLQ_HOST_FW_QIDX 0x00000008
57#define L5_KRNLQ_NX_QE_SELF_SEQ 0x0000000c
58#define L5_KRNLQ_QE_SELF_SEQ_MAX 0x0000000c
59#define L5_KRNLQ_NX_QE_HADDR_HI 0x00000010
60#define L5_KRNLQ_NX_QE_HADDR_LO 0x00000014
61#define L5_KRNLQ_PGTBL_PGIDX 0x00000018
62#define L5_KRNLQ_NX_PG_QIDX 0x00000018
63#define L5_KRNLQ_PGTBL_NPAGES 0x0000001c
64#define L5_KRNLQ_QIDX_INCR 0x0000001c
65#define L5_KRNLQ_PGTBL_HADDR_HI 0x00000020
66#define L5_KRNLQ_PGTBL_HADDR_LO 0x00000024
67
68#define BNX2_PG_CTX_MAP 0x1a0034
69#define BNX2_ISCSI_CTX_MAP 0x1a0074
70
71#define MAX_COMPLETED_KCQE 64
72
73#define MAX_CNIC_L5_CONTEXT 256
74
75#define MAX_CM_SK_TBL_SZ MAX_CNIC_L5_CONTEXT
76
77#define MAX_ISCSI_TBL_SZ 256
78
79#define CNIC_LOCAL_PORT_MIN 60000
80#define CNIC_LOCAL_PORT_MAX 61024
81#define CNIC_LOCAL_PORT_RANGE (CNIC_LOCAL_PORT_MAX - CNIC_LOCAL_PORT_MIN)
82
83#define KWQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kwqe))
84#define KCQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kcqe))
85#define MAX_KWQE_CNT (KWQE_CNT - 1)
86#define MAX_KCQE_CNT (KCQE_CNT - 1)
87
88#define MAX_KWQ_IDX ((KWQ_PAGE_CNT * KWQE_CNT) - 1)
89#define MAX_KCQ_IDX ((KCQ_PAGE_CNT * KCQE_CNT) - 1)
90
91#define KWQ_PG(x) (((x) & ~MAX_KWQE_CNT) >> (BNX2_PAGE_BITS - 5))
92#define KWQ_IDX(x) ((x) & MAX_KWQE_CNT)
93
94#define KCQ_PG(x) (((x) & ~MAX_KCQE_CNT) >> (BNX2_PAGE_BITS - 5))
95#define KCQ_IDX(x) ((x) & MAX_KCQE_CNT)
96
97#define BNX2X_NEXT_KCQE(x) (((x) & (MAX_KCQE_CNT - 1)) == \
98 (MAX_KCQE_CNT - 1)) ? \
99 (x) + 2 : (x) + 1
100
101#define BNX2X_KWQ_DATA_PG(cp, x) ((x) / (cp)->kwq_16_data_pp)
102#define BNX2X_KWQ_DATA_IDX(cp, x) ((x) % (cp)->kwq_16_data_pp)
103#define BNX2X_KWQ_DATA(cp, x) \
104 &(cp)->kwq_16_data[BNX2X_KWQ_DATA_PG(cp, x)][BNX2X_KWQ_DATA_IDX(cp, x)]
105
106#define DEF_IPID_START 0x8000
107
108#define DEF_KA_TIMEOUT 10000
109#define DEF_KA_INTERVAL 300000
110#define DEF_KA_MAX_PROBE_COUNT 3
111#define DEF_TOS 0
112#define DEF_TTL 0xfe
113#define DEF_SND_SEQ_SCALE 0
114#define DEF_RCV_BUF 0xffff
115#define DEF_SND_BUF 0xffff
116#define DEF_SEED 0
117#define DEF_MAX_RT_TIME 500
118#define DEF_MAX_DA_COUNT 2
119#define DEF_SWS_TIMER 1000
120#define DEF_MAX_CWND 0xffff
121
122struct cnic_ctx {
123 u32 cid;
124 void *ctx;
125 dma_addr_t mapping;
126};
127
128#define BNX2_MAX_CID 0x2000
129
130struct cnic_dma {
131 int num_pages;
132 void **pg_arr;
133 dma_addr_t *pg_map_arr;
134 int pgtbl_size;
135 u32 *pgtbl;
136 dma_addr_t pgtbl_map;
137};
138
139struct cnic_id_tbl {
140 spinlock_t lock;
141 u32 start;
142 u32 max;
143 u32 next;
144 unsigned long *table;
145};
146
147#define CNIC_KWQ16_DATA_SIZE 128
148
149struct kwqe_16_data {
150 u8 data[CNIC_KWQ16_DATA_SIZE];
151};
152
153struct cnic_iscsi {
154 struct cnic_dma task_array_info;
155 struct cnic_dma r2tq_info;
156 struct cnic_dma hq_info;
157};
158
159struct cnic_context {
160 u32 cid;
161 struct kwqe_16_data *kwqe_data;
162 dma_addr_t kwqe_data_mapping;
163 wait_queue_head_t waitq;
164 int wait_cond;
165 unsigned long timestamp;
166 unsigned long ctx_flags;
167#define CTX_FL_OFFLD_START 0
168#define CTX_FL_DELETE_WAIT 1
169#define CTX_FL_CID_ERROR 2
170 u8 ulp_proto_id;
171 union {
172 struct cnic_iscsi *iscsi;
173 } proto;
174};
175
176struct kcq_info {
177 struct cnic_dma dma;
178 struct kcqe **kcq;
179
180 u16 *hw_prod_idx_ptr;
181 u16 sw_prod_idx;
182 u16 *status_idx_ptr;
183 u32 io_addr;
184
185 u16 (*next_idx)(u16);
186 u16 (*hw_idx)(u16);
187};
188
189struct cnic_uio_dev {
190 struct uio_info cnic_uinfo;
191 u32 uio_dev;
192
193 int l2_ring_size;
194 void *l2_ring;
195 dma_addr_t l2_ring_map;
196
197 int l2_buf_size;
198 void *l2_buf;
199 dma_addr_t l2_buf_map;
200
201 struct cnic_dev *dev;
202 struct pci_dev *pdev;
203 struct list_head list;
204};
205
206struct cnic_local {
207
208 spinlock_t cnic_ulp_lock;
209 void *ulp_handle[MAX_CNIC_ULP_TYPE];
210 unsigned long ulp_flags[MAX_CNIC_ULP_TYPE];
211#define ULP_F_INIT 0
212#define ULP_F_START 1
213#define ULP_F_CALL_PENDING 2
214 struct cnic_ulp_ops __rcu *ulp_ops[MAX_CNIC_ULP_TYPE];
215
216 unsigned long cnic_local_flags;
217#define CNIC_LCL_FL_KWQ_INIT 0x0
218#define CNIC_LCL_FL_L2_WAIT 0x1
219#define CNIC_LCL_FL_RINGS_INITED 0x2
220#define CNIC_LCL_FL_STOP_ISCSI 0x4
221
222 struct cnic_dev *dev;
223
224 struct cnic_eth_dev *ethdev;
225
226 struct cnic_uio_dev *udev;
227
228 int l2_rx_ring_size;
229 int l2_single_buf_size;
230
231 u16 *rx_cons_ptr;
232 u16 *tx_cons_ptr;
233 u16 rx_cons;
234 u16 tx_cons;
235
236 struct cnic_dma kwq_info;
237 struct kwqe **kwq;
238
239 struct cnic_dma kwq_16_data_info;
240
241 u16 max_kwq_idx;
242
243 u16 kwq_prod_idx;
244 u32 kwq_io_addr;
245
246 u16 *kwq_con_idx_ptr;
247 u16 kwq_con_idx;
248
249 struct kcq_info kcq1;
250 struct kcq_info kcq2;
251
252 union {
253 void *gen;
254 struct status_block_msix *bnx2;
255 struct host_hc_status_block_e1x *bnx2x_e1x;
256
257 #define SM_RX_ID 0
258 #define SM_TX_ID 1
259 } status_blk;
260
261 struct host_sp_status_block *bnx2x_def_status_blk;
262
263 u32 status_blk_num;
264 u32 bnx2x_igu_sb_id;
265 u32 int_num;
266 u32 last_status_idx;
267 struct tasklet_struct cnic_irq_task;
268
269 struct kcqe *completed_kcq[MAX_COMPLETED_KCQE];
270
271 struct cnic_sock *csk_tbl;
272 struct cnic_id_tbl csk_port_tbl;
273
274 struct cnic_dma gbl_buf_info;
275
276 struct cnic_iscsi *iscsi_tbl;
277 struct cnic_context *ctx_tbl;
278 struct cnic_id_tbl cid_tbl;
279 atomic_t iscsi_conn;
280 u32 iscsi_start_cid;
281
282 u32 fcoe_init_cid;
283 u32 fcoe_start_cid;
284 struct cnic_id_tbl fcoe_cid_tbl;
285
286 u32 max_cid_space;
287
288
289 int num_iscsi_tasks;
290 int num_ccells;
291 int task_array_size;
292 int r2tq_size;
293 int hq_size;
294 int num_cqs;
295
296 struct delayed_work delete_task;
297
298 struct cnic_ctx *ctx_arr;
299 int ctx_blks;
300 int ctx_blk_size;
301 unsigned long ctx_align;
302 int cids_per_blk;
303
304 u32 chip_id;
305 int func;
306 u32 pfid;
307 u8 port_mode;
308
309 u32 shmem_base;
310
311 struct cnic_ops *cnic_ops;
312 int (*start_hw)(struct cnic_dev *);
313 void (*stop_hw)(struct cnic_dev *);
314 void (*setup_pgtbl)(struct cnic_dev *,
315 struct cnic_dma *);
316 int (*alloc_resc)(struct cnic_dev *);
317 void (*free_resc)(struct cnic_dev *);
318 int (*start_cm)(struct cnic_dev *);
319 void (*stop_cm)(struct cnic_dev *);
320 void (*enable_int)(struct cnic_dev *);
321 void (*disable_int_sync)(struct cnic_dev *);
322 void (*ack_int)(struct cnic_dev *);
323 void (*arm_int)(struct cnic_dev *, u32 index);
324 void (*close_conn)(struct cnic_sock *, u32 opcode);
325};
326
327struct bnx2x_bd_chain_next {
328 u32 addr_lo;
329 u32 addr_hi;
330 u8 reserved[8];
331};
332
333#define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1)
334
335#define ISCSI_RAMROD_CMD_ID_UPDATE_CONN (ISCSI_KCQE_OPCODE_UPDATE_CONN)
336#define ISCSI_RAMROD_CMD_ID_INIT (ISCSI_KCQE_OPCODE_INIT)
337
338#define CDU_REGION_NUMBER_XCM_AG 2
339#define CDU_REGION_NUMBER_UCM_AG 4
340
341#define CDU_VALID_DATA(_cid, _region, _type) \
342 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
343
344#define CDU_CRC8(_cid, _region, _type) \
345 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
346
347#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
348 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
349
350#define BNX2X_CONTEXT_MEM_SIZE 1024
351#define BNX2X_FCOE_CID 16
352
353#define BNX2X_ISCSI_START_CID 18
354#define BNX2X_ISCSI_NUM_CONNECTIONS 128
355#define BNX2X_ISCSI_TASK_CONTEXT_SIZE 128
356#define BNX2X_ISCSI_MAX_PENDING_R2TS 4
357#define BNX2X_ISCSI_R2TQE_SIZE 8
358#define BNX2X_ISCSI_HQ_BD_SIZE 64
359#define BNX2X_ISCSI_GLB_BUF_SIZE 64
360#define BNX2X_ISCSI_PBL_NOT_CACHED 0xff
361#define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED 0xff
362
363#define BNX2X_FCOE_NUM_CONNECTIONS 1024
364
365#define BNX2X_FCOE_L5_CID_BASE MAX_ISCSI_TBL_SZ
366
367#define BNX2X_CHIP_NUM_57710 0x164e
368#define BNX2X_CHIP_NUM_57711 0x164f
369#define BNX2X_CHIP_NUM_57711E 0x1650
370#define BNX2X_CHIP_NUM_57712 0x1662
371#define BNX2X_CHIP_NUM_57712E 0x1663
372#define BNX2X_CHIP_NUM_57713 0x1651
373#define BNX2X_CHIP_NUM_57713E 0x1652
374#define BNX2X_CHIP_NUM_57800 0x168a
375#define BNX2X_CHIP_NUM_57810 0x168e
376#define BNX2X_CHIP_NUM_57840 0x168d
377
378#define BNX2X_CHIP_NUM(x) (x >> 16)
379#define BNX2X_CHIP_IS_57710(x) \
380 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57710)
381#define BNX2X_CHIP_IS_57711(x) \
382 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57711)
383#define BNX2X_CHIP_IS_57711E(x) \
384 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57711E)
385#define BNX2X_CHIP_IS_E1H(x) \
386 (BNX2X_CHIP_IS_57711(x) || BNX2X_CHIP_IS_57711E(x))
387#define BNX2X_CHIP_IS_57712(x) \
388 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57712)
389#define BNX2X_CHIP_IS_57712E(x) \
390 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57712E)
391#define BNX2X_CHIP_IS_57713(x) \
392 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57713)
393#define BNX2X_CHIP_IS_57713E(x) \
394 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57713E)
395#define BNX2X_CHIP_IS_57800(x) \
396 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57800)
397#define BNX2X_CHIP_IS_57810(x) \
398 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57810)
399#define BNX2X_CHIP_IS_57840(x) \
400 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57840)
401#define BNX2X_CHIP_IS_E2(x) \
402 (BNX2X_CHIP_IS_57712(x) || BNX2X_CHIP_IS_57712E(x) || \
403 BNX2X_CHIP_IS_57713(x) || BNX2X_CHIP_IS_57713E(x))
404#define BNX2X_CHIP_IS_E3(x) \
405 (BNX2X_CHIP_IS_57800(x) || BNX2X_CHIP_IS_57810(x) || \
406 BNX2X_CHIP_IS_57840(x))
407#define BNX2X_CHIP_IS_E2_PLUS(x) (BNX2X_CHIP_IS_E2(x) || BNX2X_CHIP_IS_E3(x))
408
409#define BNX2X_RX_DESC_CNT (BNX2_PAGE_SIZE / \
410 sizeof(struct eth_rx_bd))
411#define BNX2X_MAX_RX_DESC_CNT (BNX2X_RX_DESC_CNT - 2)
412#define BNX2X_RCQ_DESC_CNT (BNX2_PAGE_SIZE / \
413 sizeof(union eth_rx_cqe))
414#define BNX2X_MAX_RCQ_DESC_CNT (BNX2X_RCQ_DESC_CNT - 1)
415
416#define BNX2X_NEXT_RCQE(x) (((x) & BNX2X_MAX_RCQ_DESC_CNT) == \
417 (BNX2X_MAX_RCQ_DESC_CNT - 1)) ? \
418 ((x) + 2) : ((x) + 1)
419
420#define BNX2X_DEF_SB_ID HC_SP_SB_ID
421
422#define BNX2X_SHMEM_MF_BLK_OFFSET 0x7e4
423
424#define BNX2X_SHMEM_ADDR(base, field) (base + \
425 offsetof(struct shmem_region, field))
426
427#define BNX2X_SHMEM2_ADDR(base, field) (base + \
428 offsetof(struct shmem2_region, field))
429
430#define BNX2X_SHMEM2_HAS(base, field) \
431 ((base) && \
432 (CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base, size)) > \
433 offsetof(struct shmem2_region, field)))
434
435#define BNX2X_MF_CFG_ADDR(base, field) \
436 ((base) + offsetof(struct mf_cfg, field))
437
438#ifndef ETH_MAX_RX_CLIENTS_E2
439#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
440#endif
441
442#define CNIC_PORT(cp) ((cp)->pfid & 1)
443#define CNIC_FUNC(cp) ((cp)->func)
444#define CNIC_PATH(cp) (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ? \
445 0 : (CNIC_FUNC(cp) & 1))
446#define CNIC_E1HVN(cp) ((cp)->pfid >> 1)
447
448#define BNX2X_HW_CID(cp, x) ((CNIC_PORT(cp) << 23) | \
449 (CNIC_E1HVN(cp) << 17) | (x))
450
451#define BNX2X_SW_CID(x) (x & 0x1ffff)
452
453#define BNX2X_CL_QZONE_ID(cp, cli) \
454 (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ? cli : \
455 cli + (CNIC_PORT(cp) * ETH_MAX_RX_CLIENTS_E1H))
456
457#ifndef MAX_STAT_COUNTER_ID
458#define MAX_STAT_COUNTER_ID \
459 (BNX2X_CHIP_IS_E1H((cp)->chip_id) ? MAX_STAT_COUNTER_ID_E1H : \
460 ((BNX2X_CHIP_IS_E2_PLUS((cp)->chip_id)) ? MAX_STAT_COUNTER_ID_E2 :\
461 MAX_STAT_COUNTER_ID_E1))
462#endif
463
464#define CNIC_SUPPORTS_FCOE(cp) \
465 (BNX2X_CHIP_IS_E2_PLUS((cp)->chip_id) && \
466 !((cp)->ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
467
468#define CNIC_RAMROD_TMO (HZ / 4)
469
470#endif
471
472
