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18#ifndef BE_H
19#define BE_H
20
21#include <linux/pci.h>
22#include <linux/etherdevice.h>
23#include <linux/delay.h>
24#include <net/tcp.h>
25#include <net/ip.h>
26#include <net/ipv6.h>
27#include <linux/if_vlan.h>
28#include <linux/workqueue.h>
29#include <linux/interrupt.h>
30#include <linux/firmware.h>
31#include <linux/slab.h>
32#include <linux/u64_stats_sync.h>
33
34#include "be_hw.h"
35#include "be_roce.h"
36
37#define DRV_VER "4.6.62.0u"
38#define DRV_NAME "be2net"
39#define BE_NAME "Emulex BladeEngine2"
40#define BE3_NAME "Emulex BladeEngine3"
41#define OC_NAME "Emulex OneConnect"
42#define OC_NAME_BE OC_NAME "(be3)"
43#define OC_NAME_LANCER OC_NAME "(Lancer)"
44#define OC_NAME_SH OC_NAME "(Skyhawk)"
45#define DRV_DESC "Emulex OneConnect 10Gbps NIC Driver"
46
47#define BE_VENDOR_ID 0x19a2
48#define EMULEX_VENDOR_ID 0x10df
49#define BE_DEVICE_ID1 0x211
50#define BE_DEVICE_ID2 0x221
51#define OC_DEVICE_ID1 0x700
52#define OC_DEVICE_ID2 0x710
53#define OC_DEVICE_ID3 0xe220
54#define OC_DEVICE_ID4 0xe228
55#define OC_DEVICE_ID5 0x720
56#define OC_DEVICE_ID6 0x728
57#define OC_SUBSYS_DEVICE_ID1 0xE602
58#define OC_SUBSYS_DEVICE_ID2 0xE642
59#define OC_SUBSYS_DEVICE_ID3 0xE612
60#define OC_SUBSYS_DEVICE_ID4 0xE652
61
62static inline char *nic_name(struct pci_dev *pdev)
63{
64 switch (pdev->device) {
65 case OC_DEVICE_ID1:
66 return OC_NAME;
67 case OC_DEVICE_ID2:
68 return OC_NAME_BE;
69 case OC_DEVICE_ID3:
70 case OC_DEVICE_ID4:
71 return OC_NAME_LANCER;
72 case BE_DEVICE_ID2:
73 return BE3_NAME;
74 case OC_DEVICE_ID5:
75 case OC_DEVICE_ID6:
76 return OC_NAME_SH;
77 default:
78 return BE_NAME;
79 }
80}
81
82
83#define BE_HDR_LEN ((u16) 64)
84
85#define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
86
87#define BE_MAX_JUMBO_FRAME_SIZE 9018
88#define BE_MIN_MTU 256
89
90#define BE_NUM_VLANS_SUPPORTED 64
91#define BE_MAX_EQD 96u
92#define BE_MAX_TX_FRAG_COUNT 30
93
94#define EVNT_Q_LEN 1024
95#define TX_Q_LEN 2048
96#define TX_CQ_LEN 1024
97#define RX_Q_LEN 1024
98#define RX_CQ_LEN 1024
99#define MCC_Q_LEN 128
100#define MCC_CQ_LEN 256
101
102#define BE3_MAX_RSS_QS 8
103#define BE2_MAX_RSS_QS 4
104#define MAX_RSS_QS BE3_MAX_RSS_QS
105#define MAX_RX_QS (MAX_RSS_QS + 1)
106
107#define MAX_TX_QS 8
108#define MAX_ROCE_EQS 5
109#define MAX_MSIX_VECTORS (MAX_RSS_QS + MAX_ROCE_EQS)
110#define BE_TX_BUDGET 256
111#define BE_NAPI_WEIGHT 64
112#define MAX_RX_POST BE_NAPI_WEIGHT
113#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
114
115#define MAX_VFS 30
116#define FW_VER_LEN 32
117
118struct be_dma_mem {
119 void *va;
120 dma_addr_t dma;
121 u32 size;
122};
123
124struct be_queue_info {
125 struct be_dma_mem dma_mem;
126 u16 len;
127 u16 entry_size;
128 u16 id;
129 u16 tail, head;
130 bool created;
131 atomic_t used;
132};
133
134static inline u32 MODULO(u16 val, u16 limit)
135{
136 BUG_ON(limit & (limit - 1));
137 return val & (limit - 1);
138}
139
140static inline void index_adv(u16 *index, u16 val, u16 limit)
141{
142 *index = MODULO((*index + val), limit);
143}
144
145static inline void index_inc(u16 *index, u16 limit)
146{
147 *index = MODULO((*index + 1), limit);
148}
149
150static inline void *queue_head_node(struct be_queue_info *q)
151{
152 return q->dma_mem.va + q->head * q->entry_size;
153}
154
155static inline void *queue_tail_node(struct be_queue_info *q)
156{
157 return q->dma_mem.va + q->tail * q->entry_size;
158}
159
160static inline void *queue_index_node(struct be_queue_info *q, u16 index)
161{
162 return q->dma_mem.va + index * q->entry_size;
163}
164
165static inline void queue_head_inc(struct be_queue_info *q)
166{
167 index_inc(&q->head, q->len);
168}
169
170static inline void index_dec(u16 *index, u16 limit)
171{
172 *index = MODULO((*index - 1), limit);
173}
174
175static inline void queue_tail_inc(struct be_queue_info *q)
176{
177 index_inc(&q->tail, q->len);
178}
179
180struct be_eq_obj {
181 struct be_queue_info q;
182 char desc[32];
183
184
185 bool enable_aic;
186 u32 min_eqd;
187 u32 max_eqd;
188 u32 eqd;
189 u32 cur_eqd;
190
191 u8 idx;
192 u16 tx_budget;
193 u16 spurious_intr;
194 struct napi_struct napi;
195 struct be_adapter *adapter;
196} ____cacheline_aligned_in_smp;
197
198struct be_mcc_obj {
199 struct be_queue_info q;
200 struct be_queue_info cq;
201 bool rearm_cq;
202};
203
204struct be_tx_stats {
205 u64 tx_bytes;
206 u64 tx_pkts;
207 u64 tx_reqs;
208 u64 tx_wrbs;
209 u64 tx_compl;
210 ulong tx_jiffies;
211 u32 tx_stops;
212 struct u64_stats_sync sync;
213 struct u64_stats_sync sync_compl;
214};
215
216struct be_tx_obj {
217 u32 db_offset;
218 struct be_queue_info q;
219 struct be_queue_info cq;
220
221 struct sk_buff *sent_skb_list[TX_Q_LEN];
222 struct be_tx_stats stats;
223} ____cacheline_aligned_in_smp;
224
225
226struct be_rx_page_info {
227 struct page *page;
228 DEFINE_DMA_UNMAP_ADDR(bus);
229 u16 page_offset;
230 bool last_page_user;
231};
232
233struct be_rx_stats {
234 u64 rx_bytes;
235 u64 rx_pkts;
236 u64 rx_pkts_prev;
237 ulong rx_jiffies;
238 u32 rx_drops_no_skbs;
239 u32 rx_drops_no_frags;
240 u32 rx_post_fail;
241 u32 rx_compl;
242 u32 rx_mcast_pkts;
243 u32 rx_compl_err;
244 u32 rx_pps;
245 struct u64_stats_sync sync;
246};
247
248struct be_rx_compl_info {
249 u32 rss_hash;
250 u16 vlan_tag;
251 u16 pkt_size;
252 u16 rxq_idx;
253 u16 port;
254 u8 vlanf;
255 u8 num_rcvd;
256 u8 err;
257 u8 ipf;
258 u8 tcpf;
259 u8 udpf;
260 u8 ip_csum;
261 u8 l4_csum;
262 u8 ipv6;
263 u8 vtm;
264 u8 pkt_type;
265 u8 ip_frag;
266};
267
268struct be_rx_obj {
269 struct be_adapter *adapter;
270 struct be_queue_info q;
271 struct be_queue_info cq;
272 struct be_rx_compl_info rxcp;
273 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
274 struct be_rx_stats stats;
275 u8 rss_id;
276 bool rx_post_starved;
277} ____cacheline_aligned_in_smp;
278
279struct be_drv_stats {
280 u32 be_on_die_temperature;
281 u32 eth_red_drops;
282 u32 rx_drops_no_pbuf;
283 u32 rx_drops_no_txpb;
284 u32 rx_drops_no_erx_descr;
285 u32 rx_drops_no_tpre_descr;
286 u32 rx_drops_too_many_frags;
287 u32 forwarded_packets;
288 u32 rx_drops_mtu;
289 u32 rx_crc_errors;
290 u32 rx_alignment_symbol_errors;
291 u32 rx_pause_frames;
292 u32 rx_priority_pause_frames;
293 u32 rx_control_frames;
294 u32 rx_in_range_errors;
295 u32 rx_out_range_errors;
296 u32 rx_frame_too_long;
297 u32 rx_address_filtered;
298 u32 rx_dropped_too_small;
299 u32 rx_dropped_too_short;
300 u32 rx_dropped_header_too_small;
301 u32 rx_dropped_tcp_length;
302 u32 rx_dropped_runt;
303 u32 rx_ip_checksum_errs;
304 u32 rx_tcp_checksum_errs;
305 u32 rx_udp_checksum_errs;
306 u32 tx_pauseframes;
307 u32 tx_priority_pauseframes;
308 u32 tx_controlframes;
309 u32 rxpp_fifo_overflow_drop;
310 u32 rx_input_fifo_overflow_drop;
311 u32 pmem_fifo_overflow_drop;
312 u32 jabber_events;
313};
314
315struct be_vf_cfg {
316 unsigned char mac_addr[ETH_ALEN];
317 int if_handle;
318 int pmac_id;
319 u16 def_vid;
320 u16 vlan_tag;
321 u32 tx_rate;
322};
323
324enum vf_state {
325 ENABLED = 0,
326 ASSIGNED = 1
327};
328
329#define BE_FLAGS_LINK_STATUS_INIT 1
330#define BE_FLAGS_WORKER_SCHEDULED (1 << 3)
331#define BE_FLAGS_NAPI_ENABLED (1 << 9)
332#define BE_UC_PMAC_COUNT 30
333#define BE_VF_UC_PMAC_COUNT 2
334#define BE_FLAGS_QNQ_ASYNC_EVT_RCVD (1 << 11)
335
336struct phy_info {
337 u8 transceiver;
338 u8 autoneg;
339 u8 fc_autoneg;
340 u8 port_type;
341 u16 phy_type;
342 u16 interface_type;
343 u32 misc_params;
344 u16 auto_speeds_supported;
345 u16 fixed_speeds_supported;
346 int link_speed;
347 u32 dac_cable_len;
348 u32 advertising;
349 u32 supported;
350};
351
352struct be_adapter {
353 struct pci_dev *pdev;
354 struct net_device *netdev;
355
356 u8 __iomem *csr;
357 u8 __iomem *db;
358
359 struct mutex mbox_lock;
360 struct be_dma_mem mbox_mem;
361
362
363 struct be_dma_mem mbox_mem_alloced;
364
365 struct be_mcc_obj mcc_obj;
366 spinlock_t mcc_lock;
367 spinlock_t mcc_cq_lock;
368
369 u32 num_msix_vec;
370 u32 num_evt_qs;
371 struct be_eq_obj eq_obj[MAX_MSIX_VECTORS];
372 struct msix_entry msix_entries[MAX_MSIX_VECTORS];
373 bool isr_registered;
374
375
376 u32 num_tx_qs;
377 struct be_tx_obj tx_obj[MAX_TX_QS];
378
379
380 u32 num_rx_qs;
381 struct be_rx_obj rx_obj[MAX_RX_QS];
382 u32 big_page_size;
383
384 struct be_drv_stats drv_stats;
385 u16 vlans_added;
386 u8 vlan_tag[VLAN_N_VID];
387 u8 vlan_prio_bmap;
388 u16 recommended_prio;
389 struct be_dma_mem rx_filter;
390
391 struct be_dma_mem stats_cmd;
392
393 struct delayed_work work;
394 u16 work_counter;
395
396 struct delayed_work func_recovery_work;
397 u32 flags;
398 u32 cmd_privileges;
399
400 char fw_ver[FW_VER_LEN];
401 int if_handle;
402 u32 *pmac_id;
403 u32 beacon_state;
404
405 bool eeh_error;
406 bool fw_timeout;
407 bool hw_error;
408
409 u32 port_num;
410 bool promiscuous;
411 u32 function_mode;
412 u32 function_caps;
413 u32 rx_fc;
414 u32 tx_fc;
415 bool stats_cmd_sent;
416 u32 if_type;
417 struct {
418 u32 size;
419 u32 total_size;
420 u64 io_addr;
421 } roce_db;
422 u32 num_msix_roce_vec;
423 struct ocrdma_dev *ocrdma_dev;
424 struct list_head entry;
425
426 u32 flash_status;
427 struct completion flash_compl;
428
429 u32 num_vfs;
430 u32 dev_num_vfs;
431 u8 virtfn;
432 struct be_vf_cfg *vf_cfg;
433 bool be3_native;
434 u32 sli_family;
435 u8 hba_port_num;
436 u16 pvid;
437 struct phy_info phy;
438 u8 wol_cap;
439 bool wol;
440 u32 uc_macs;
441 u16 asic_rev;
442 u16 qnq_vid;
443 u32 msg_enable;
444 int be_get_temp_freq;
445 u16 max_mcast_mac;
446 u16 max_tx_queues;
447 u16 max_rss_queues;
448 u16 max_rx_queues;
449 u16 max_pmac_cnt;
450 u16 max_vlans;
451 u16 max_event_queues;
452 u32 if_cap_flags;
453 u8 pf_number;
454 u64 rss_flags;
455};
456
457#define be_physfn(adapter) (!adapter->virtfn)
458#define sriov_enabled(adapter) (adapter->num_vfs > 0)
459#define sriov_want(adapter) (adapter->dev_num_vfs && num_vfs && \
460 be_physfn(adapter))
461#define for_all_vfs(adapter, vf_cfg, i) \
462 for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
463 i++, vf_cfg++)
464
465#define ON 1
466#define OFF 0
467
468#define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \
469 adapter->pdev->device == OC_DEVICE_ID4)
470
471#define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \
472 adapter->pdev->device == OC_DEVICE_ID6)
473
474#define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \
475 adapter->pdev->device == OC_DEVICE_ID2)
476
477#define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \
478 adapter->pdev->device == OC_DEVICE_ID1)
479
480#define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter))
481
482#define be_roce_supported(adapter) (skyhawk_chip(adapter) && \
483 (adapter->function_mode & RDMA_ENABLED))
484
485extern const struct ethtool_ops be_ethtool_ops;
486
487#define msix_enabled(adapter) (adapter->num_msix_vec > 0)
488#define num_irqs(adapter) (msix_enabled(adapter) ? \
489 adapter->num_msix_vec : 1)
490#define tx_stats(txo) (&(txo)->stats)
491#define rx_stats(rxo) (&(rxo)->stats)
492
493
494#define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1])
495
496#define for_all_rx_queues(adapter, rxo, i) \
497 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
498 i++, rxo++)
499
500
501#define for_all_rss_queues(adapter, rxo, i) \
502 for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
503 i++, rxo++)
504
505#define for_all_tx_queues(adapter, txo, i) \
506 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
507 i++, txo++)
508
509#define for_all_evt_queues(adapter, eqo, i) \
510 for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
511 i++, eqo++)
512
513#define is_mcc_eqo(eqo) (eqo->idx == 0)
514#define mcc_eqo(adapter) (&adapter->eq_obj[0])
515
516#define PAGE_SHIFT_4K 12
517#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
518
519
520#define PAGES_4K_SPANNED(_address, size) \
521 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
522 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
523
524
525#define AMAP_BIT_OFFSET(_struct, field) \
526 (((size_t)&(((_struct *)0)->field))%32)
527
528
529static inline u32 amap_mask(u32 bitsize)
530{
531 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
532}
533
534static inline void
535amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
536{
537 u32 *dw = (u32 *) ptr + dw_offset;
538 *dw &= ~(mask << offset);
539 *dw |= (mask & value) << offset;
540}
541
542#define AMAP_SET_BITS(_struct, field, ptr, val) \
543 amap_set(ptr, \
544 offsetof(_struct, field)/32, \
545 amap_mask(sizeof(((_struct *)0)->field)), \
546 AMAP_BIT_OFFSET(_struct, field), \
547 val)
548
549static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
550{
551 u32 *dw = (u32 *) ptr;
552 return mask & (*(dw + dw_offset) >> offset);
553}
554
555#define AMAP_GET_BITS(_struct, field, ptr) \
556 amap_get(ptr, \
557 offsetof(_struct, field)/32, \
558 amap_mask(sizeof(((_struct *)0)->field)), \
559 AMAP_BIT_OFFSET(_struct, field))
560
561#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
562#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
563static inline void swap_dws(void *wrb, int len)
564{
565#ifdef __BIG_ENDIAN
566 u32 *dw = wrb;
567 BUG_ON(len % 4);
568 do {
569 *dw = cpu_to_le32(*dw);
570 dw++;
571 len -= 4;
572 } while (len);
573#endif
574}
575
576static inline u8 is_tcp_pkt(struct sk_buff *skb)
577{
578 u8 val = 0;
579
580 if (ip_hdr(skb)->version == 4)
581 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
582 else if (ip_hdr(skb)->version == 6)
583 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
584
585 return val;
586}
587
588static inline u8 is_udp_pkt(struct sk_buff *skb)
589{
590 u8 val = 0;
591
592 if (ip_hdr(skb)->version == 4)
593 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
594 else if (ip_hdr(skb)->version == 6)
595 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
596
597 return val;
598}
599
600static inline bool is_ipv4_pkt(struct sk_buff *skb)
601{
602 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
603}
604
605static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
606{
607 u32 addr;
608
609 addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
610
611 mac[5] = (u8)(addr & 0xFF);
612 mac[4] = (u8)((addr >> 8) & 0xFF);
613 mac[3] = (u8)((addr >> 16) & 0xFF);
614
615 memcpy(mac, adapter->netdev->dev_addr, 3);
616}
617
618static inline bool be_multi_rxq(const struct be_adapter *adapter)
619{
620 return adapter->num_rx_qs > 1;
621}
622
623static inline bool be_error(struct be_adapter *adapter)
624{
625 return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout;
626}
627
628static inline bool be_hw_error(struct be_adapter *adapter)
629{
630 return adapter->eeh_error || adapter->hw_error;
631}
632
633static inline void be_clear_all_error(struct be_adapter *adapter)
634{
635 adapter->eeh_error = false;
636 adapter->hw_error = false;
637 adapter->fw_timeout = false;
638}
639
640static inline bool be_is_wol_excluded(struct be_adapter *adapter)
641{
642 struct pci_dev *pdev = adapter->pdev;
643
644 if (!be_physfn(adapter))
645 return true;
646
647 switch (pdev->subsystem_device) {
648 case OC_SUBSYS_DEVICE_ID1:
649 case OC_SUBSYS_DEVICE_ID2:
650 case OC_SUBSYS_DEVICE_ID3:
651 case OC_SUBSYS_DEVICE_ID4:
652 return true;
653 default:
654 return false;
655 }
656}
657
658static inline int qnq_async_evt_rcvd(struct be_adapter *adapter)
659{
660 return adapter->flags & BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
661}
662
663extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
664 u16 num_popped);
665extern void be_link_status_update(struct be_adapter *adapter, u8 link_status);
666extern void be_parse_stats(struct be_adapter *adapter);
667extern int be_load_fw(struct be_adapter *adapter, u8 *func);
668extern bool be_is_wol_supported(struct be_adapter *adapter);
669extern bool be_pause_supported(struct be_adapter *adapter);
670extern u32 be_get_fw_log_level(struct be_adapter *adapter);
671
672
673
674
675extern void be_roce_dev_add(struct be_adapter *);
676extern void be_roce_dev_remove(struct be_adapter *);
677
678
679
680
681extern void be_roce_dev_open(struct be_adapter *);
682extern void be_roce_dev_close(struct be_adapter *);
683
684#endif
685