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23#ifndef __GIANFAR_H
24#define __GIANFAR_H
25
26#include <linux/kernel.h>
27#include <linux/sched.h>
28#include <linux/string.h>
29#include <linux/errno.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/spinlock.h>
38#include <linux/mm.h>
39#include <linux/mii.h>
40#include <linux/phy.h>
41
42#include <asm/io.h>
43#include <asm/irq.h>
44#include <asm/uaccess.h>
45#include <linux/module.h>
46#include <linux/crc32.h>
47#include <linux/workqueue.h>
48#include <linux/ethtool.h>
49
50struct ethtool_flow_spec_container {
51 struct ethtool_rx_flow_spec fs;
52 struct list_head list;
53};
54
55struct ethtool_rx_list {
56 struct list_head list;
57 unsigned int count;
58};
59
60
61#define GFAR_DEV_WEIGHT 64
62
63
64#define GMAC_FCB_LEN 8
65
66
67#define GMAC_TXPAL_LEN 16
68
69
70#define DEFAULT_PADDING 2
71
72
73#define RXBUF_ALIGNMENT 64
74
75
76
77
78#define INCREMENTAL_BUFFER_SIZE 512
79
80#define PHY_INIT_TIMEOUT 100000
81
82#define DRV_NAME "gfar-enet"
83extern const char gfar_driver_version[];
84
85
86#define MAX_TX_QS 0x8
87#define MAX_RX_QS 0x8
88
89
90#define MAXGROUPS 0x2
91
92
93#define DEFAULT_TX_RING_SIZE 256
94#define DEFAULT_RX_RING_SIZE 256
95
96#define GFAR_RX_MAX_RING_SIZE 256
97#define GFAR_TX_MAX_RING_SIZE 256
98
99#define GFAR_MAX_FIFO_THRESHOLD 511
100#define GFAR_MAX_FIFO_STARVE 511
101#define GFAR_MAX_FIFO_STARVE_OFF 511
102
103#define DEFAULT_RX_BUFFER_SIZE 1536
104#define TX_RING_MOD_MASK(size) (size-1)
105#define RX_RING_MOD_MASK(size) (size-1)
106#define JUMBO_BUFFER_SIZE 9728
107#define JUMBO_FRAME_SIZE 9600
108
109#define DEFAULT_FIFO_TX_THR 0x100
110#define DEFAULT_FIFO_TX_STARVE 0x40
111#define DEFAULT_FIFO_TX_STARVE_OFF 0x80
112#define DEFAULT_BD_STASH 1
113#define DEFAULT_STASH_LENGTH 96
114#define DEFAULT_STASH_INDEX 0
115
116
117#define GFAR_EM_NUM 15
118
119
120
121
122
123
124
125
126
127
128
129#define GFAR_GBIT_TIME 512
130#define GFAR_100_TIME 2560
131#define GFAR_10_TIME 25600
132
133#define DEFAULT_TX_COALESCE 1
134#define DEFAULT_TXCOUNT 16
135#define DEFAULT_TXTIME 21
136
137#define DEFAULT_RXTIME 21
138
139#define DEFAULT_RX_COALESCE 0
140#define DEFAULT_RXCOUNT 0
141
142#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
143 | SUPPORTED_10baseT_Full \
144 | SUPPORTED_100baseT_Half \
145 | SUPPORTED_100baseT_Full \
146 | SUPPORTED_Autoneg \
147 | SUPPORTED_MII)
148
149
150#define MII_TBICON 0x11
151
152
153#define TBICON_CLK_SELECT 0x0020
154
155
156#define MACCFG1_SOFT_RESET 0x80000000
157#define MACCFG1_RESET_RX_MC 0x00080000
158#define MACCFG1_RESET_TX_MC 0x00040000
159#define MACCFG1_RESET_RX_FUN 0x00020000
160#define MACCFG1_RESET_TX_FUN 0x00010000
161#define MACCFG1_LOOPBACK 0x00000100
162#define MACCFG1_RX_FLOW 0x00000020
163#define MACCFG1_TX_FLOW 0x00000010
164#define MACCFG1_SYNCD_RX_EN 0x00000008
165#define MACCFG1_RX_EN 0x00000004
166#define MACCFG1_SYNCD_TX_EN 0x00000002
167#define MACCFG1_TX_EN 0x00000001
168
169#define MACCFG2_INIT_SETTINGS 0x00007205
170#define MACCFG2_FULL_DUPLEX 0x00000001
171#define MACCFG2_IF 0x00000300
172#define MACCFG2_MII 0x00000100
173#define MACCFG2_GMII 0x00000200
174#define MACCFG2_HUGEFRAME 0x00000020
175#define MACCFG2_LENGTHCHECK 0x00000010
176#define MACCFG2_MPEN 0x00000008
177
178#define ECNTRL_FIFM 0x00008000
179#define ECNTRL_INIT_SETTINGS 0x00001000
180#define ECNTRL_TBI_MODE 0x00000020
181#define ECNTRL_REDUCED_MODE 0x00000010
182#define ECNTRL_R100 0x00000008
183#define ECNTRL_REDUCED_MII_MODE 0x00000004
184#define ECNTRL_SGMII_MODE 0x00000002
185
186#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
187
188#define MINFLR_INIT_SETTINGS 0x00000040
189
190
191#define TQUEUE_EN0 0x00008000
192#define TQUEUE_EN1 0x00004000
193#define TQUEUE_EN2 0x00002000
194#define TQUEUE_EN3 0x00001000
195#define TQUEUE_EN4 0x00000800
196#define TQUEUE_EN5 0x00000400
197#define TQUEUE_EN6 0x00000200
198#define TQUEUE_EN7 0x00000100
199#define TQUEUE_EN_ALL 0x0000FF00
200
201#define TR03WT_WT0_MASK 0xFF000000
202#define TR03WT_WT1_MASK 0x00FF0000
203#define TR03WT_WT2_MASK 0x0000FF00
204#define TR03WT_WT3_MASK 0x000000FF
205
206#define TR47WT_WT4_MASK 0xFF000000
207#define TR47WT_WT5_MASK 0x00FF0000
208#define TR47WT_WT6_MASK 0x0000FF00
209#define TR47WT_WT7_MASK 0x000000FF
210
211
212#define RQUEUE_EX0 0x00800000
213#define RQUEUE_EX1 0x00400000
214#define RQUEUE_EX2 0x00200000
215#define RQUEUE_EX3 0x00100000
216#define RQUEUE_EX4 0x00080000
217#define RQUEUE_EX5 0x00040000
218#define RQUEUE_EX6 0x00020000
219#define RQUEUE_EX7 0x00010000
220#define RQUEUE_EX_ALL 0x00FF0000
221
222#define RQUEUE_EN0 0x00000080
223#define RQUEUE_EN1 0x00000040
224#define RQUEUE_EN2 0x00000020
225#define RQUEUE_EN3 0x00000010
226#define RQUEUE_EN4 0x00000008
227#define RQUEUE_EN5 0x00000004
228#define RQUEUE_EN6 0x00000002
229#define RQUEUE_EN7 0x00000001
230#define RQUEUE_EN_ALL 0x000000FF
231
232
233#define DMACTRL_INIT_SETTINGS 0x000000c3
234#define DMACTRL_GRS 0x00000010
235#define DMACTRL_GTS 0x00000008
236
237#define TSTAT_CLEAR_THALT_ALL 0xFF000000
238#define TSTAT_CLEAR_THALT 0x80000000
239#define TSTAT_CLEAR_THALT0 0x80000000
240#define TSTAT_CLEAR_THALT1 0x40000000
241#define TSTAT_CLEAR_THALT2 0x20000000
242#define TSTAT_CLEAR_THALT3 0x10000000
243#define TSTAT_CLEAR_THALT4 0x08000000
244#define TSTAT_CLEAR_THALT5 0x04000000
245#define TSTAT_CLEAR_THALT6 0x02000000
246#define TSTAT_CLEAR_THALT7 0x01000000
247
248
249#define IC_ICEN 0x80000000
250#define IC_ICFT_MASK 0x1fe00000
251#define IC_ICFT_SHIFT 21
252#define mk_ic_icft(x) \
253 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
254#define IC_ICTT_MASK 0x0000ffff
255#define mk_ic_ictt(x) (x&IC_ICTT_MASK)
256
257#define mk_ic_value(count, time) (IC_ICEN | \
258 mk_ic_icft(count) | \
259 mk_ic_ictt(time))
260#define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
261 IC_ICFT_SHIFT)
262#define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
263
264#define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
265#define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
266
267#define skip_bd(bdp, stride, base, ring_size) ({ \
268 typeof(bdp) new_bd = (bdp) + (stride); \
269 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; })
270
271#define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size)
272
273#define RCTRL_TS_ENABLE 0x01000000
274#define RCTRL_PAL_MASK 0x001f0000
275#define RCTRL_VLEX 0x00002000
276#define RCTRL_FILREN 0x00001000
277#define RCTRL_GHTX 0x00000400
278#define RCTRL_IPCSEN 0x00000200
279#define RCTRL_TUCSEN 0x00000100
280#define RCTRL_PRSDEP_MASK 0x000000c0
281#define RCTRL_PRSDEP_INIT 0x000000c0
282#define RCTRL_PRSFM 0x00000020
283#define RCTRL_PROM 0x00000008
284#define RCTRL_EMEN 0x00000002
285#define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
286 RCTRL_TUCSEN | RCTRL_FILREN)
287#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
288 RCTRL_PRSDEP_INIT)
289#define RCTRL_EXTHASH (RCTRL_GHTX)
290#define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
291#define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
292
293
294#define RSTAT_CLEAR_RHALT 0x00800000
295#define RSTAT_CLEAR_RXF0 0x00000080
296#define RSTAT_RXF_MASK 0x000000ff
297
298#define TCTRL_IPCSEN 0x00004000
299#define TCTRL_TUCSEN 0x00002000
300#define TCTRL_VLINS 0x00001000
301#define TCTRL_THDF 0x00000800
302#define TCTRL_RFCPAUSE 0x00000010
303#define TCTRL_TFCPAUSE 0x00000008
304#define TCTRL_TXSCHED_MASK 0x00000006
305#define TCTRL_TXSCHED_INIT 0x00000000
306
307#define TCTRL_TXSCHED_PRIO 0x00000002
308
309#define TCTRL_TXSCHED_WRRS 0x00000004
310
311
312
313
314#define DEFAULT_WRRS_WEIGHT 0x18181818
315
316#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
317
318#define IEVENT_INIT_CLEAR 0xffffffff
319#define IEVENT_BABR 0x80000000
320#define IEVENT_RXC 0x40000000
321#define IEVENT_BSY 0x20000000
322#define IEVENT_EBERR 0x10000000
323#define IEVENT_MSRO 0x04000000
324#define IEVENT_GTSC 0x02000000
325#define IEVENT_BABT 0x01000000
326#define IEVENT_TXC 0x00800000
327#define IEVENT_TXE 0x00400000
328#define IEVENT_TXB 0x00200000
329#define IEVENT_TXF 0x00100000
330#define IEVENT_LC 0x00040000
331#define IEVENT_CRL 0x00020000
332#define IEVENT_XFUN 0x00010000
333#define IEVENT_RXB0 0x00008000
334#define IEVENT_MAG 0x00000800
335#define IEVENT_GRSC 0x00000100
336#define IEVENT_RXF0 0x00000080
337#define IEVENT_FIR 0x00000008
338#define IEVENT_FIQ 0x00000004
339#define IEVENT_DPE 0x00000002
340#define IEVENT_PERR 0x00000001
341#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
342#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
343#define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
344#define IEVENT_ERR_MASK \
345(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
346 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
347 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
348 | IEVENT_MAG | IEVENT_BABR)
349
350#define IMASK_INIT_CLEAR 0x00000000
351#define IMASK_BABR 0x80000000
352#define IMASK_RXC 0x40000000
353#define IMASK_BSY 0x20000000
354#define IMASK_EBERR 0x10000000
355#define IMASK_MSRO 0x04000000
356#define IMASK_GTSC 0x02000000
357#define IMASK_BABT 0x01000000
358#define IMASK_TXC 0x00800000
359#define IMASK_TXEEN 0x00400000
360#define IMASK_TXBEN 0x00200000
361#define IMASK_TXFEN 0x00100000
362#define IMASK_LC 0x00040000
363#define IMASK_CRL 0x00020000
364#define IMASK_XFUN 0x00010000
365#define IMASK_RXB0 0x00008000
366#define IMASK_MAG 0x00000800
367#define IMASK_GRSC 0x00000100
368#define IMASK_RXFEN0 0x00000080
369#define IMASK_FIR 0x00000008
370#define IMASK_FIQ 0x00000004
371#define IMASK_DPE 0x00000002
372#define IMASK_PERR 0x00000001
373#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
374 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
375 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
376 | IMASK_PERR)
377#define IMASK_RTX_DISABLED ((~(IMASK_RXFEN0 | IMASK_TXFEN | IMASK_BSY)) \
378 & IMASK_DEFAULT)
379
380
381#define FIFO_TX_THR_MASK 0x01ff
382#define FIFO_TX_STARVE_MASK 0x01ff
383#define FIFO_TX_STARVE_OFF_MASK 0x01ff
384
385
386
387
388#define ATTR_BDSTASH 0x00000800
389
390#define ATTR_BUFSTASH 0x00004000
391
392#define ATTR_SNOOPING 0x000000c0
393#define ATTR_INIT_SETTINGS ATTR_SNOOPING
394
395#define ATTRELI_INIT_SETTINGS 0x0
396#define ATTRELI_EL_MASK 0x3fff0000
397#define ATTRELI_EL(x) (x << 16)
398#define ATTRELI_EI_MASK 0x00003fff
399#define ATTRELI_EI(x) (x)
400
401#define BD_LFLAG(flags) ((flags) << 16)
402#define BD_LENGTH_MASK 0x0000ffff
403
404#define FPR_FILER_MASK 0xFFFFFFFF
405#define MAX_FILER_IDX 0xFF
406
407
408
409#define DEFAULT_RIR0 0x05397700
410
411
412#define RQFCR_GPI 0x80000000
413#define RQFCR_HASHTBL_Q 0x00000000
414#define RQFCR_HASHTBL_0 0x00020000
415#define RQFCR_HASHTBL_1 0x00040000
416#define RQFCR_HASHTBL_2 0x00060000
417#define RQFCR_HASHTBL_3 0x00080000
418#define RQFCR_HASH 0x00010000
419#define RQFCR_QUEUE 0x0000FC00
420#define RQFCR_CLE 0x00000200
421#define RQFCR_RJE 0x00000100
422#define RQFCR_AND 0x00000080
423#define RQFCR_CMP_EXACT 0x00000000
424#define RQFCR_CMP_MATCH 0x00000020
425#define RQFCR_CMP_NOEXACT 0x00000040
426#define RQFCR_CMP_NOMATCH 0x00000060
427
428
429#define RQFCR_PID_MASK 0x00000000
430#define RQFCR_PID_PARSE 0x00000001
431#define RQFCR_PID_ARB 0x00000002
432#define RQFCR_PID_DAH 0x00000003
433#define RQFCR_PID_DAL 0x00000004
434#define RQFCR_PID_SAH 0x00000005
435#define RQFCR_PID_SAL 0x00000006
436#define RQFCR_PID_ETY 0x00000007
437#define RQFCR_PID_VID 0x00000008
438#define RQFCR_PID_PRI 0x00000009
439#define RQFCR_PID_TOS 0x0000000A
440#define RQFCR_PID_L4P 0x0000000B
441#define RQFCR_PID_DIA 0x0000000C
442#define RQFCR_PID_SIA 0x0000000D
443#define RQFCR_PID_DPT 0x0000000E
444#define RQFCR_PID_SPT 0x0000000F
445
446
447#define RQFPR_HDR_GE_512 0x00200000
448#define RQFPR_LERR 0x00100000
449#define RQFPR_RAR 0x00080000
450#define RQFPR_RARQ 0x00040000
451#define RQFPR_AR 0x00020000
452#define RQFPR_ARQ 0x00010000
453#define RQFPR_EBC 0x00008000
454#define RQFPR_VLN 0x00004000
455#define RQFPR_CFI 0x00002000
456#define RQFPR_JUM 0x00001000
457#define RQFPR_IPF 0x00000800
458#define RQFPR_FIF 0x00000400
459#define RQFPR_IPV4 0x00000200
460#define RQFPR_IPV6 0x00000100
461#define RQFPR_ICC 0x00000080
462#define RQFPR_ICV 0x00000040
463#define RQFPR_TCP 0x00000020
464#define RQFPR_UDP 0x00000010
465#define RQFPR_TUC 0x00000008
466#define RQFPR_TUV 0x00000004
467#define RQFPR_PER 0x00000002
468#define RQFPR_EER 0x00000001
469
470
471#define TXBD_READY 0x8000
472#define TXBD_PADCRC 0x4000
473#define TXBD_WRAP 0x2000
474#define TXBD_INTERRUPT 0x1000
475#define TXBD_LAST 0x0800
476#define TXBD_CRC 0x0400
477#define TXBD_DEF 0x0200
478#define TXBD_HUGEFRAME 0x0080
479#define TXBD_LATECOLLISION 0x0080
480#define TXBD_RETRYLIMIT 0x0040
481#define TXBD_RETRYCOUNTMASK 0x003c
482#define TXBD_UNDERRUN 0x0002
483#define TXBD_TOE 0x0002
484
485
486#define TXFCB_VLN 0x80
487#define TXFCB_IP 0x40
488#define TXFCB_IP6 0x20
489#define TXFCB_TUP 0x10
490#define TXFCB_UDP 0x08
491#define TXFCB_CIP 0x04
492#define TXFCB_CTU 0x02
493#define TXFCB_NPH 0x01
494#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
495
496
497#define RXBD_EMPTY 0x8000
498#define RXBD_RO1 0x4000
499#define RXBD_WRAP 0x2000
500#define RXBD_INTERRUPT 0x1000
501#define RXBD_LAST 0x0800
502#define RXBD_FIRST 0x0400
503#define RXBD_MISS 0x0100
504#define RXBD_BROADCAST 0x0080
505#define RXBD_MULTICAST 0x0040
506#define RXBD_LARGE 0x0020
507#define RXBD_NONOCTET 0x0010
508#define RXBD_SHORT 0x0008
509#define RXBD_CRCERR 0x0004
510#define RXBD_OVERRUN 0x0002
511#define RXBD_TRUNCATED 0x0001
512#define RXBD_STATS 0x01ff
513#define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
514 | RXBD_CRCERR | RXBD_OVERRUN \
515 | RXBD_TRUNCATED)
516
517
518#define RXFCB_VLN 0x8000
519#define RXFCB_IP 0x4000
520#define RXFCB_IP6 0x2000
521#define RXFCB_TUP 0x1000
522#define RXFCB_CIP 0x0800
523#define RXFCB_CTU 0x0400
524#define RXFCB_EIP 0x0200
525#define RXFCB_ETU 0x0100
526#define RXFCB_CSUM_MASK 0x0f00
527#define RXFCB_PERR_MASK 0x000c
528#define RXFCB_PERR_BADL3 0x0008
529
530#define GFAR_INT_NAME_MAX (IFNAMSIZ + 6)
531
532struct txbd8
533{
534 union {
535 struct {
536 u16 status;
537 u16 length;
538 };
539 u32 lstatus;
540 };
541 u32 bufPtr;
542};
543
544struct txfcb {
545 u8 flags;
546 u8 ptp;
547 u8 l4os;
548 u8 l3os;
549 u16 phcs;
550 u16 vlctl;
551};
552
553struct rxbd8
554{
555 union {
556 struct {
557 u16 status;
558 u16 length;
559 };
560 u32 lstatus;
561 };
562 u32 bufPtr;
563};
564
565struct rxfcb {
566 u16 flags;
567 u8 rq;
568 u8 pro;
569 u16 reserved;
570 u16 vlctl;
571};
572
573struct gianfar_skb_cb {
574 int alignamount;
575};
576
577#define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
578
579struct rmon_mib
580{
581 u32 tr64;
582 u32 tr127;
583 u32 tr255;
584 u32 tr511;
585 u32 tr1k;
586 u32 trmax;
587 u32 trmgv;
588 u32 rbyt;
589 u32 rpkt;
590 u32 rfcs;
591 u32 rmca;
592 u32 rbca;
593 u32 rxcf;
594 u32 rxpf;
595 u32 rxuo;
596 u32 raln;
597 u32 rflr;
598 u32 rcde;
599 u32 rcse;
600 u32 rund;
601 u32 rovr;
602 u32 rfrg;
603 u32 rjbr;
604 u32 rdrp;
605 u32 tbyt;
606 u32 tpkt;
607 u32 tmca;
608 u32 tbca;
609 u32 txpf;
610 u32 tdfr;
611 u32 tedf;
612 u32 tscl;
613 u32 tmcl;
614 u32 tlcl;
615 u32 txcl;
616 u32 tncl;
617 u8 res1[4];
618 u32 tdrp;
619 u32 tjbr;
620 u32 tfcs;
621 u32 txcf;
622 u32 tovr;
623 u32 tund;
624 u32 tfrg;
625 u32 car1;
626 u32 car2;
627 u32 cam1;
628 u32 cam2;
629};
630
631struct gfar_extra_stats {
632 atomic64_t rx_large;
633 atomic64_t rx_short;
634 atomic64_t rx_nonoctet;
635 atomic64_t rx_crcerr;
636 atomic64_t rx_overrun;
637 atomic64_t rx_bsy;
638 atomic64_t rx_babr;
639 atomic64_t rx_trunc;
640 atomic64_t eberr;
641 atomic64_t tx_babt;
642 atomic64_t tx_underrun;
643 atomic64_t rx_skbmissing;
644 atomic64_t tx_timeout;
645};
646
647#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
648#define GFAR_EXTRA_STATS_LEN \
649 (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t))
650
651
652#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
653
654struct gfar {
655 u32 tsec_id;
656 u32 tsec_id2;
657 u8 res1[8];
658 u32 ievent;
659 u32 imask;
660 u32 edis;
661 u32 emapg;
662 u32 ecntrl;
663 u32 minflr;
664 u32 ptv;
665 u32 dmactrl;
666 u32 tbipa;
667 u8 res2[28];
668 u32 fifo_rx_pause;
669
670 u32 fifo_rx_pause_shutoff;
671
672 u32 fifo_rx_alarm;
673
674 u32 fifo_rx_alarm_shutoff;
675
676 u8 res3[44];
677 u32 fifo_tx_thr;
678 u8 res4[8];
679 u32 fifo_tx_starve;
680 u32 fifo_tx_starve_shutoff;
681 u8 res5[96];
682 u32 tctrl;
683 u32 tstat;
684 u32 dfvlan;
685 u32 tbdlen;
686 u32 txic;
687 u32 tqueue;
688 u8 res7[40];
689 u32 tr03wt;
690 u32 tr47wt;
691 u8 res8[52];
692 u32 tbdbph;
693 u8 res9a[4];
694 u32 tbptr0;
695 u8 res9b[4];
696 u32 tbptr1;
697 u8 res9c[4];
698 u32 tbptr2;
699 u8 res9d[4];
700 u32 tbptr3;
701 u8 res9e[4];
702 u32 tbptr4;
703 u8 res9f[4];
704 u32 tbptr5;
705 u8 res9g[4];
706 u32 tbptr6;
707 u8 res9h[4];
708 u32 tbptr7;
709 u8 res9[64];
710 u32 tbaseh;
711 u32 tbase0;
712 u8 res10a[4];
713 u32 tbase1;
714 u8 res10b[4];
715 u32 tbase2;
716 u8 res10c[4];
717 u32 tbase3;
718 u8 res10d[4];
719 u32 tbase4;
720 u8 res10e[4];
721 u32 tbase5;
722 u8 res10f[4];
723 u32 tbase6;
724 u8 res10g[4];
725 u32 tbase7;
726 u8 res10[192];
727 u32 rctrl;
728 u32 rstat;
729 u8 res12[8];
730 u32 rxic;
731 u32 rqueue;
732 u32 rir0;
733 u32 rir1;
734 u32 rir2;
735 u32 rir3;
736 u8 res13[8];
737 u32 rbifx;
738 u32 rqfar;
739 u32 rqfcr;
740 u32 rqfpr;
741 u32 mrblr;
742 u8 res14[56];
743 u32 rbdbph;
744 u8 res15a[4];
745 u32 rbptr0;
746 u8 res15b[4];
747 u32 rbptr1;
748 u8 res15c[4];
749 u32 rbptr2;
750 u8 res15d[4];
751 u32 rbptr3;
752 u8 res15e[4];
753 u32 rbptr4;
754 u8 res15f[4];
755 u32 rbptr5;
756 u8 res15g[4];
757 u32 rbptr6;
758 u8 res15h[4];
759 u32 rbptr7;
760 u8 res16[64];
761 u32 rbaseh;
762 u32 rbase0;
763 u8 res17a[4];
764 u32 rbase1;
765 u8 res17b[4];
766 u32 rbase2;
767 u8 res17c[4];
768 u32 rbase3;
769 u8 res17d[4];
770 u32 rbase4;
771 u8 res17e[4];
772 u32 rbase5;
773 u8 res17f[4];
774 u32 rbase6;
775 u8 res17g[4];
776 u32 rbase7;
777 u8 res17[192];
778 u32 maccfg1;
779 u32 maccfg2;
780 u32 ipgifg;
781 u32 hafdup;
782 u32 maxfrm;
783 u8 res18[12];
784 u8 gfar_mii_regs[24];
785 u32 ifctrl;
786 u32 ifstat;
787 u32 macstnaddr1;
788 u32 macstnaddr2;
789 u32 mac01addr1;
790 u32 mac01addr2;
791 u32 mac02addr1;
792 u32 mac02addr2;
793 u32 mac03addr1;
794 u32 mac03addr2;
795 u32 mac04addr1;
796 u32 mac04addr2;
797 u32 mac05addr1;
798 u32 mac05addr2;
799 u32 mac06addr1;
800 u32 mac06addr2;
801 u32 mac07addr1;
802 u32 mac07addr2;
803 u32 mac08addr1;
804 u32 mac08addr2;
805 u32 mac09addr1;
806 u32 mac09addr2;
807 u32 mac10addr1;
808 u32 mac10addr2;
809 u32 mac11addr1;
810 u32 mac11addr2;
811 u32 mac12addr1;
812 u32 mac12addr2;
813 u32 mac13addr1;
814 u32 mac13addr2;
815 u32 mac14addr1;
816 u32 mac14addr2;
817 u32 mac15addr1;
818 u32 mac15addr2;
819 u8 res20[192];
820 struct rmon_mib rmon;
821 u32 rrej;
822 u8 res21[188];
823 u32 igaddr0;
824 u32 igaddr1;
825 u32 igaddr2;
826 u32 igaddr3;
827 u32 igaddr4;
828 u32 igaddr5;
829 u32 igaddr6;
830 u32 igaddr7;
831 u8 res22[96];
832 u32 gaddr0;
833 u32 gaddr1;
834 u32 gaddr2;
835 u32 gaddr3;
836 u32 gaddr4;
837 u32 gaddr5;
838 u32 gaddr6;
839 u32 gaddr7;
840 u8 res23a[352];
841 u32 fifocfg;
842 u8 res23b[252];
843 u8 res23c[248];
844 u32 attr;
845 u32 attreli;
846 u8 res24[688];
847 u32 isrg0;
848 u32 isrg1;
849 u32 isrg2;
850 u32 isrg3;
851 u8 res25[16];
852 u32 rxic0;
853 u32 rxic1;
854 u32 rxic2;
855 u32 rxic3;
856 u32 rxic4;
857 u32 rxic5;
858 u32 rxic6;
859 u32 rxic7;
860 u8 res26[32];
861 u32 txic0;
862 u32 txic1;
863 u32 txic2;
864 u32 txic3;
865 u32 txic4;
866 u32 txic5;
867 u32 txic6;
868 u32 txic7;
869 u8 res27[208];
870};
871
872
873#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
874#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
875#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
876#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
877#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
878#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
879#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
880#define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
881#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
882#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
883#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
884#define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800
885
886#if (MAXGROUPS == 2)
887#define DEFAULT_MAPPING 0xAA
888#else
889#define DEFAULT_MAPPING 0xFF
890#endif
891
892#define ISRG_SHIFT_TX 0x10
893#define ISRG_SHIFT_RX 0x18
894
895
896
897
898
899
900enum {
901 SQ_SG_MODE = 0,
902 MQ_MG_MODE
903};
904
905
906
907
908struct tx_q_stats {
909 unsigned long tx_packets;
910 unsigned long tx_bytes;
911};
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933struct gfar_priv_tx_q {
934
935 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
936 struct txbd8 *tx_bd_base;
937 struct txbd8 *cur_tx;
938 unsigned int num_txbdfree;
939 unsigned short skb_curtx;
940 unsigned short tx_ring_size;
941 struct tx_q_stats stats;
942 struct gfar_priv_grp *grp;
943
944 struct net_device *dev;
945 struct sk_buff **tx_skbuff;
946 struct txbd8 *dirty_tx;
947 unsigned short skb_dirtytx;
948 unsigned short qindex;
949
950 unsigned int txcoalescing;
951 unsigned long txic;
952 dma_addr_t tx_bd_dma_base;
953};
954
955
956
957
958struct rx_q_stats {
959 unsigned long rx_packets;
960 unsigned long rx_bytes;
961 unsigned long rx_dropped;
962};
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978struct gfar_priv_rx_q {
979 spinlock_t rxlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
980 struct sk_buff ** rx_skbuff;
981 dma_addr_t rx_bd_dma_base;
982 struct rxbd8 *rx_bd_base;
983 struct rxbd8 *cur_rx;
984 struct net_device *dev;
985 struct gfar_priv_grp *grp;
986 struct rx_q_stats stats;
987 u16 skb_currx;
988 u16 qindex;
989 unsigned int rx_ring_size;
990
991 unsigned char rxcoalescing;
992 unsigned long rxic;
993};
994
995enum gfar_irqinfo_id {
996 GFAR_TX = 0,
997 GFAR_RX = 1,
998 GFAR_ER = 2,
999 GFAR_NUM_IRQS = 3
1000};
1001
1002struct gfar_irqinfo {
1003 unsigned int irq;
1004 char name[GFAR_INT_NAME_MAX];
1005};
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016struct gfar_priv_grp {
1017 spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES)));
1018 struct napi_struct napi;
1019 struct gfar_private *priv;
1020 struct gfar __iomem *regs;
1021 unsigned int grp_id;
1022 unsigned long num_rx_queues;
1023 unsigned long rx_bit_map;
1024
1025 unsigned int rstat;
1026 unsigned int tstat;
1027 unsigned long num_tx_queues;
1028 unsigned long tx_bit_map;
1029
1030 struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
1031};
1032
1033#define gfar_irq(grp, ID) \
1034 ((grp)->irqinfo[GFAR_##ID])
1035
1036enum gfar_errata {
1037 GFAR_ERRATA_74 = 0x01,
1038 GFAR_ERRATA_76 = 0x02,
1039 GFAR_ERRATA_A002 = 0x04,
1040 GFAR_ERRATA_12 = 0x08,
1041};
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052struct gfar_private {
1053 unsigned int num_rx_queues;
1054
1055 struct device *dev;
1056 struct net_device *ndev;
1057 enum gfar_errata errata;
1058 unsigned int rx_buffer_size;
1059
1060 u16 uses_rxfcb;
1061 u16 padding;
1062
1063
1064 int hwts_rx_en;
1065 int hwts_tx_en;
1066
1067 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1068 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
1069 struct gfar_priv_grp gfargrp[MAXGROUPS];
1070
1071 u32 device_flags;
1072
1073 unsigned int mode;
1074 unsigned int num_tx_queues;
1075 unsigned int num_grps;
1076
1077
1078 struct gfar_extra_stats extra_stats;
1079
1080
1081 phy_interface_t interface;
1082 struct device_node *phy_node;
1083 struct device_node *tbi_node;
1084 struct phy_device *phydev;
1085 struct mii_bus *mii_bus;
1086 int oldspeed;
1087 int oldduplex;
1088 int oldlink;
1089
1090
1091 spinlock_t bflock;
1092
1093 uint32_t msg_enable;
1094
1095 struct work_struct reset_task;
1096
1097 struct platform_device *ofdev;
1098 unsigned char
1099 extended_hash:1,
1100 bd_stash_en:1,
1101 rx_filer_enable:1,
1102
1103 wol_en:1,
1104
1105 prio_sched_en:1;
1106
1107
1108 unsigned int total_tx_ring_size;
1109 unsigned int total_rx_ring_size;
1110
1111
1112 unsigned int rx_stash_size;
1113 unsigned int rx_stash_index;
1114
1115 u32 cur_filer_idx;
1116
1117
1118 struct ethtool_rx_list rx_list;
1119 struct mutex rx_queue_access;
1120
1121
1122 u32 __iomem *hash_regs[16];
1123 int hash_width;
1124
1125
1126 unsigned int fifo_threshold;
1127 unsigned int fifo_starve;
1128 unsigned int fifo_starve_off;
1129
1130
1131 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
1132 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
1133};
1134
1135
1136static inline int gfar_has_errata(struct gfar_private *priv,
1137 enum gfar_errata err)
1138{
1139 return priv->errata & err;
1140}
1141
1142static inline u32 gfar_read(unsigned __iomem *addr)
1143{
1144 u32 val;
1145 val = ioread32be(addr);
1146 return val;
1147}
1148
1149static inline void gfar_write(unsigned __iomem *addr, u32 val)
1150{
1151 iowrite32be(val, addr);
1152}
1153
1154static inline void gfar_write_filer(struct gfar_private *priv,
1155 unsigned int far, unsigned int fcr, unsigned int fpr)
1156{
1157 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1158
1159 gfar_write(®s->rqfar, far);
1160 gfar_write(®s->rqfcr, fcr);
1161 gfar_write(®s->rqfpr, fpr);
1162}
1163
1164static inline void gfar_read_filer(struct gfar_private *priv,
1165 unsigned int far, unsigned int *fcr, unsigned int *fpr)
1166{
1167 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1168
1169 gfar_write(®s->rqfar, far);
1170 *fcr = gfar_read(®s->rqfcr);
1171 *fpr = gfar_read(®s->rqfpr);
1172}
1173
1174extern void lock_rx_qs(struct gfar_private *priv);
1175extern void lock_tx_qs(struct gfar_private *priv);
1176extern void unlock_rx_qs(struct gfar_private *priv);
1177extern void unlock_tx_qs(struct gfar_private *priv);
1178extern irqreturn_t gfar_receive(int irq, void *dev_id);
1179extern int startup_gfar(struct net_device *dev);
1180extern void stop_gfar(struct net_device *dev);
1181extern void gfar_halt(struct net_device *dev);
1182extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
1183 int enable, u32 regnum, u32 read);
1184extern void gfar_configure_coalescing_all(struct gfar_private *priv);
1185void gfar_init_sysfs(struct net_device *dev);
1186int gfar_set_features(struct net_device *dev, netdev_features_t features);
1187extern void gfar_check_rx_parser_mode(struct gfar_private *priv);
1188extern void gfar_vlan_mode(struct net_device *dev, netdev_features_t features);
1189
1190extern const struct ethtool_ops gfar_ethtool_ops;
1191
1192#define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX))
1193
1194#define RQFCR_PID_PRI_MASK 0xFFFFFFF8
1195#define RQFCR_PID_L4P_MASK 0xFFFFFF00
1196#define RQFCR_PID_VID_MASK 0xFFFFF000
1197#define RQFCR_PID_PORT_MASK 0xFFFF0000
1198#define RQFCR_PID_MAC_MASK 0xFF000000
1199
1200struct gfar_mask_entry {
1201 unsigned int mask;
1202 unsigned int start;
1203 unsigned int end;
1204 unsigned int block;
1205};
1206
1207
1208struct gfar_filer_entry {
1209 u32 ctrl;
1210 u32 prop;
1211};
1212
1213
1214
1215struct filer_table {
1216 u32 index;
1217 struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20];
1218};
1219
1220
1221extern int gfar_phc_index;
1222
1223#endif
1224