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28#ifndef _E1000_HW_H_
29#define _E1000_HW_H_
30
31#include <linux/types.h>
32#include <linux/delay.h>
33#include <linux/io.h>
34#include <linux/netdevice.h>
35
36#include "e1000_regs.h"
37#include "e1000_defines.h"
38
39struct e1000_hw;
40
41#define E1000_DEV_ID_82576 0x10C9
42#define E1000_DEV_ID_82576_FIBER 0x10E6
43#define E1000_DEV_ID_82576_SERDES 0x10E7
44#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
45#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
46#define E1000_DEV_ID_82576_NS 0x150A
47#define E1000_DEV_ID_82576_NS_SERDES 0x1518
48#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
49#define E1000_DEV_ID_82575EB_COPPER 0x10A7
50#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
51#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
52#define E1000_DEV_ID_82580_COPPER 0x150E
53#define E1000_DEV_ID_82580_FIBER 0x150F
54#define E1000_DEV_ID_82580_SERDES 0x1510
55#define E1000_DEV_ID_82580_SGMII 0x1511
56#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
57#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
58#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
59#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
60#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
61#define E1000_DEV_ID_DH89XXCC_SFP 0x0440
62#define E1000_DEV_ID_I350_COPPER 0x1521
63#define E1000_DEV_ID_I350_FIBER 0x1522
64#define E1000_DEV_ID_I350_SERDES 0x1523
65#define E1000_DEV_ID_I350_SGMII 0x1524
66#define E1000_DEV_ID_I210_COPPER 0x1533
67#define E1000_DEV_ID_I210_FIBER 0x1536
68#define E1000_DEV_ID_I210_SERDES 0x1537
69#define E1000_DEV_ID_I210_SGMII 0x1538
70#define E1000_DEV_ID_I211_COPPER 0x1539
71#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
72#define E1000_DEV_ID_I354_SGMII 0x1F41
73#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
74
75#define E1000_REVISION_2 2
76#define E1000_REVISION_4 4
77
78#define E1000_FUNC_0 0
79#define E1000_FUNC_1 1
80#define E1000_FUNC_2 2
81#define E1000_FUNC_3 3
82
83#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
84#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
85#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
86#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
87
88enum e1000_mac_type {
89 e1000_undefined = 0,
90 e1000_82575,
91 e1000_82576,
92 e1000_82580,
93 e1000_i350,
94 e1000_i354,
95 e1000_i210,
96 e1000_i211,
97 e1000_num_macs
98};
99
100enum e1000_media_type {
101 e1000_media_type_unknown = 0,
102 e1000_media_type_copper = 1,
103 e1000_media_type_fiber = 2,
104 e1000_media_type_internal_serdes = 3,
105 e1000_num_media_types
106};
107
108enum e1000_nvm_type {
109 e1000_nvm_unknown = 0,
110 e1000_nvm_none,
111 e1000_nvm_eeprom_spi,
112 e1000_nvm_flash_hw,
113 e1000_nvm_flash_sw
114};
115
116enum e1000_nvm_override {
117 e1000_nvm_override_none = 0,
118 e1000_nvm_override_spi_small,
119 e1000_nvm_override_spi_large,
120};
121
122enum e1000_phy_type {
123 e1000_phy_unknown = 0,
124 e1000_phy_none,
125 e1000_phy_m88,
126 e1000_phy_igp,
127 e1000_phy_igp_2,
128 e1000_phy_gg82563,
129 e1000_phy_igp_3,
130 e1000_phy_ife,
131 e1000_phy_82580,
132 e1000_phy_i210,
133};
134
135enum e1000_bus_type {
136 e1000_bus_type_unknown = 0,
137 e1000_bus_type_pci,
138 e1000_bus_type_pcix,
139 e1000_bus_type_pci_express,
140 e1000_bus_type_reserved
141};
142
143enum e1000_bus_speed {
144 e1000_bus_speed_unknown = 0,
145 e1000_bus_speed_33,
146 e1000_bus_speed_66,
147 e1000_bus_speed_100,
148 e1000_bus_speed_120,
149 e1000_bus_speed_133,
150 e1000_bus_speed_2500,
151 e1000_bus_speed_5000,
152 e1000_bus_speed_reserved
153};
154
155enum e1000_bus_width {
156 e1000_bus_width_unknown = 0,
157 e1000_bus_width_pcie_x1,
158 e1000_bus_width_pcie_x2,
159 e1000_bus_width_pcie_x4 = 4,
160 e1000_bus_width_pcie_x8 = 8,
161 e1000_bus_width_32,
162 e1000_bus_width_64,
163 e1000_bus_width_reserved
164};
165
166enum e1000_1000t_rx_status {
167 e1000_1000t_rx_status_not_ok = 0,
168 e1000_1000t_rx_status_ok,
169 e1000_1000t_rx_status_undefined = 0xFF
170};
171
172enum e1000_rev_polarity {
173 e1000_rev_polarity_normal = 0,
174 e1000_rev_polarity_reversed,
175 e1000_rev_polarity_undefined = 0xFF
176};
177
178enum e1000_fc_mode {
179 e1000_fc_none = 0,
180 e1000_fc_rx_pause,
181 e1000_fc_tx_pause,
182 e1000_fc_full,
183 e1000_fc_default = 0xFF
184};
185
186
187struct e1000_hw_stats {
188 u64 crcerrs;
189 u64 algnerrc;
190 u64 symerrs;
191 u64 rxerrc;
192 u64 mpc;
193 u64 scc;
194 u64 ecol;
195 u64 mcc;
196 u64 latecol;
197 u64 colc;
198 u64 dc;
199 u64 tncrs;
200 u64 sec;
201 u64 cexterr;
202 u64 rlec;
203 u64 xonrxc;
204 u64 xontxc;
205 u64 xoffrxc;
206 u64 xofftxc;
207 u64 fcruc;
208 u64 prc64;
209 u64 prc127;
210 u64 prc255;
211 u64 prc511;
212 u64 prc1023;
213 u64 prc1522;
214 u64 gprc;
215 u64 bprc;
216 u64 mprc;
217 u64 gptc;
218 u64 gorc;
219 u64 gotc;
220 u64 rnbc;
221 u64 ruc;
222 u64 rfc;
223 u64 roc;
224 u64 rjc;
225 u64 mgprc;
226 u64 mgpdc;
227 u64 mgptc;
228 u64 tor;
229 u64 tot;
230 u64 tpr;
231 u64 tpt;
232 u64 ptc64;
233 u64 ptc127;
234 u64 ptc255;
235 u64 ptc511;
236 u64 ptc1023;
237 u64 ptc1522;
238 u64 mptc;
239 u64 bptc;
240 u64 tsctc;
241 u64 tsctfc;
242 u64 iac;
243 u64 icrxptc;
244 u64 icrxatc;
245 u64 ictxptc;
246 u64 ictxatc;
247 u64 ictxqec;
248 u64 ictxqmtc;
249 u64 icrxdmtc;
250 u64 icrxoc;
251 u64 cbtmpc;
252 u64 htdpmc;
253 u64 cbrdpc;
254 u64 cbrmpc;
255 u64 rpthc;
256 u64 hgptc;
257 u64 htcbdpc;
258 u64 hgorc;
259 u64 hgotc;
260 u64 lenerrs;
261 u64 scvpc;
262 u64 hrmpc;
263 u64 doosync;
264 u64 o2bgptc;
265 u64 o2bspc;
266 u64 b2ospc;
267 u64 b2ogprc;
268};
269
270struct e1000_phy_stats {
271 u32 idle_errors;
272 u32 receive_errors;
273};
274
275struct e1000_host_mng_dhcp_cookie {
276 u32 signature;
277 u8 status;
278 u8 reserved0;
279 u16 vlan_id;
280 u32 reserved1;
281 u16 reserved2;
282 u8 reserved3;
283 u8 checksum;
284};
285
286
287struct e1000_host_command_header {
288 u8 command_id;
289 u8 command_length;
290 u8 command_options;
291 u8 checksum;
292};
293
294#define E1000_HI_MAX_DATA_LENGTH 252
295struct e1000_host_command_info {
296 struct e1000_host_command_header command_header;
297 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
298};
299
300
301struct e1000_host_mng_command_header {
302 u8 command_id;
303 u8 checksum;
304 u16 reserved1;
305 u16 reserved2;
306 u16 command_length;
307};
308
309#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
310struct e1000_host_mng_command_info {
311 struct e1000_host_mng_command_header command_header;
312 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
313};
314
315#include "e1000_mac.h"
316#include "e1000_phy.h"
317#include "e1000_nvm.h"
318#include "e1000_mbx.h"
319
320struct e1000_mac_operations {
321 s32 (*check_for_link)(struct e1000_hw *);
322 s32 (*reset_hw)(struct e1000_hw *);
323 s32 (*init_hw)(struct e1000_hw *);
324 bool (*check_mng_mode)(struct e1000_hw *);
325 s32 (*setup_physical_interface)(struct e1000_hw *);
326 void (*rar_set)(struct e1000_hw *, u8 *, u32);
327 s32 (*read_mac_addr)(struct e1000_hw *);
328 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
329 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
330 void (*release_swfw_sync)(struct e1000_hw *, u16);
331#ifdef CONFIG_IGB_HWMON
332 s32 (*get_thermal_sensor_data)(struct e1000_hw *);
333 s32 (*init_thermal_sensor_thresh)(struct e1000_hw *);
334#endif
335
336};
337
338struct e1000_phy_operations {
339 s32 (*acquire)(struct e1000_hw *);
340 s32 (*check_polarity)(struct e1000_hw *);
341 s32 (*check_reset_block)(struct e1000_hw *);
342 s32 (*force_speed_duplex)(struct e1000_hw *);
343 s32 (*get_cfg_done)(struct e1000_hw *hw);
344 s32 (*get_cable_length)(struct e1000_hw *);
345 s32 (*get_phy_info)(struct e1000_hw *);
346 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
347 void (*release)(struct e1000_hw *);
348 s32 (*reset)(struct e1000_hw *);
349 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
350 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
351 s32 (*write_reg)(struct e1000_hw *, u32, u16);
352 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
353 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
354};
355
356struct e1000_nvm_operations {
357 s32 (*acquire)(struct e1000_hw *);
358 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
359 void (*release)(struct e1000_hw *);
360 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
361 s32 (*update)(struct e1000_hw *);
362 s32 (*validate)(struct e1000_hw *);
363 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
364};
365
366#define E1000_MAX_SENSORS 3
367
368struct e1000_thermal_diode_data {
369 u8 location;
370 u8 temp;
371 u8 caution_thresh;
372 u8 max_op_thresh;
373};
374
375struct e1000_thermal_sensor_data {
376 struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];
377};
378
379struct e1000_info {
380 s32 (*get_invariants)(struct e1000_hw *);
381 struct e1000_mac_operations *mac_ops;
382 struct e1000_phy_operations *phy_ops;
383 struct e1000_nvm_operations *nvm_ops;
384};
385
386extern const struct e1000_info e1000_82575_info;
387
388struct e1000_mac_info {
389 struct e1000_mac_operations ops;
390
391 u8 addr[6];
392 u8 perm_addr[6];
393
394 enum e1000_mac_type type;
395
396 u32 ledctl_default;
397 u32 ledctl_mode1;
398 u32 ledctl_mode2;
399 u32 mc_filter_type;
400 u32 txcw;
401
402 u16 mta_reg_count;
403 u16 uta_reg_count;
404
405
406 #define MAX_MTA_REG 128
407 u32 mta_shadow[MAX_MTA_REG];
408 u16 rar_entry_count;
409
410 u8 forced_speed_duplex;
411
412 bool adaptive_ifs;
413 bool arc_subsystem_valid;
414 bool asf_firmware_present;
415 bool autoneg;
416 bool autoneg_failed;
417 bool disable_hw_init_bits;
418 bool get_link_status;
419 bool ifs_params_forced;
420 bool in_ifs_mode;
421 bool report_tx_early;
422 bool serdes_has_link;
423 bool tx_pkt_filtering;
424 struct e1000_thermal_sensor_data thermal_sensor_data;
425};
426
427struct e1000_phy_info {
428 struct e1000_phy_operations ops;
429
430 enum e1000_phy_type type;
431
432 enum e1000_1000t_rx_status local_rx;
433 enum e1000_1000t_rx_status remote_rx;
434 enum e1000_ms_type ms_type;
435 enum e1000_ms_type original_ms_type;
436 enum e1000_rev_polarity cable_polarity;
437 enum e1000_smart_speed smart_speed;
438
439 u32 addr;
440 u32 id;
441 u32 reset_delay_us;
442 u32 revision;
443
444 enum e1000_media_type media_type;
445
446 u16 autoneg_advertised;
447 u16 autoneg_mask;
448 u16 cable_length;
449 u16 max_cable_length;
450 u16 min_cable_length;
451
452 u8 mdix;
453
454 bool disable_polarity_correction;
455 bool is_mdix;
456 bool polarity_correction;
457 bool reset_disable;
458 bool speed_downgraded;
459 bool autoneg_wait_to_complete;
460};
461
462struct e1000_nvm_info {
463 struct e1000_nvm_operations ops;
464 enum e1000_nvm_type type;
465 enum e1000_nvm_override override;
466
467 u32 flash_bank_size;
468 u32 flash_base_addr;
469
470 u16 word_size;
471 u16 delay_usec;
472 u16 address_bits;
473 u16 opcode_bits;
474 u16 page_size;
475};
476
477struct e1000_bus_info {
478 enum e1000_bus_type type;
479 enum e1000_bus_speed speed;
480 enum e1000_bus_width width;
481
482 u32 snoop;
483
484 u16 func;
485 u16 pci_cmd_word;
486};
487
488struct e1000_fc_info {
489 u32 high_water;
490 u32 low_water;
491 u16 pause_time;
492 bool send_xon;
493 bool strict_ieee;
494 enum e1000_fc_mode current_mode;
495 enum e1000_fc_mode requested_mode;
496};
497
498struct e1000_mbx_operations {
499 s32 (*init_params)(struct e1000_hw *hw);
500 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
501 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
502 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
503 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
504 s32 (*check_for_msg)(struct e1000_hw *, u16);
505 s32 (*check_for_ack)(struct e1000_hw *, u16);
506 s32 (*check_for_rst)(struct e1000_hw *, u16);
507};
508
509struct e1000_mbx_stats {
510 u32 msgs_tx;
511 u32 msgs_rx;
512
513 u32 acks;
514 u32 reqs;
515 u32 rsts;
516};
517
518struct e1000_mbx_info {
519 struct e1000_mbx_operations ops;
520 struct e1000_mbx_stats stats;
521 u32 timeout;
522 u32 usec_delay;
523 u16 size;
524};
525
526struct e1000_dev_spec_82575 {
527 bool sgmii_active;
528 bool global_device_reset;
529 bool eee_disable;
530 bool clear_semaphore_once;
531};
532
533struct e1000_hw {
534 void *back;
535
536 u8 __iomem *hw_addr;
537 u8 __iomem *flash_address;
538 unsigned long io_base;
539
540 struct e1000_mac_info mac;
541 struct e1000_fc_info fc;
542 struct e1000_phy_info phy;
543 struct e1000_nvm_info nvm;
544 struct e1000_bus_info bus;
545 struct e1000_mbx_info mbx;
546 struct e1000_host_mng_dhcp_cookie mng_cookie;
547
548 union {
549 struct e1000_dev_spec_82575 _82575;
550 } dev_spec;
551
552 u16 device_id;
553 u16 subsystem_vendor_id;
554 u16 subsystem_device_id;
555 u16 vendor_id;
556
557 u8 revision_id;
558};
559
560extern struct net_device *igb_get_hw_dev(struct e1000_hw *hw);
561#define hw_dbg(format, arg...) \
562 netdev_dbg(igb_get_hw_dev(hw), format, ##arg)
563
564
565s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
566s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
567#endif
568
