LXR linux/drivers/net/ethernet/intel/ixgbe/ixgbe

   1/*******************************************************************************
   2
   3  Intel 10 Gigabit PCI Express Linux driver
   4  Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6  This program is free software; you can redistribute it and/or modify it
   7  under the terms and conditions of the GNU General Public License,
   8  version 2, as published by the Free Software Foundation.
   9
  10  This program is distributed in the hope it will be useful, but WITHOUT
  11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  more details.
  14
  15  You should have received a copy of the GNU General Public License along with
  16  this program; if not, write to the Free Software Foundation, Inc.,
  17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19  The full GNU General Public License is included in this distribution in
  20  the file called "COPYING".
  21
  22  Contact Information:
  23  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26*******************************************************************************/
  27
  28#ifndef _IXGBE_TYPE_H_
  29#define _IXGBE_TYPE_H_
  30
  31#include <linux/types.h>
  32#include <linux/mdio.h>
  33#include <linux/netdevice.h>
  34
  35/* Device IDs */
  36#define IXGBE_DEV_ID_82598               0x10B6
  37#define IXGBE_DEV_ID_82598_BX            0x1508
  38#define IXGBE_DEV_ID_82598AF_DUAL_PORT   0x10C6
  39#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
  40#define IXGBE_DEV_ID_82598EB_SFP_LOM     0x10DB
  41#define IXGBE_DEV_ID_82598AT             0x10C8
  42#define IXGBE_DEV_ID_82598AT2            0x150B
  43#define IXGBE_DEV_ID_82598EB_CX4         0x10DD
  44#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
  45#define IXGBE_DEV_ID_82598_DA_DUAL_PORT  0x10F1
  46#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM      0x10E1
  47#define IXGBE_DEV_ID_82598EB_XF_LR       0x10F4
  48#define IXGBE_DEV_ID_82599_KX4           0x10F7
  49#define IXGBE_DEV_ID_82599_KX4_MEZZ      0x1514
  50#define IXGBE_DEV_ID_82599_KR            0x1517
  51#define IXGBE_DEV_ID_82599_T3_LOM        0x151C
  52#define IXGBE_DEV_ID_82599_CX4           0x10F9
  53#define IXGBE_DEV_ID_82599_SFP           0x10FB
  54#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE       0x152a
  55#define IXGBE_DEV_ID_82599_SFP_FCOE      0x1529
  56#define IXGBE_SUBDEV_ID_82599_SFP        0x11A9
  57#define IXGBE_SUBDEV_ID_82599_RNDC       0x1F72
  58#define IXGBE_SUBDEV_ID_82599_560FLR     0x17D0
  59#define IXGBE_SUBDEV_ID_82599_SP_560FLR  0x211B
  60#define IXGBE_SUBDEV_ID_82599_ECNA_DP    0x0470
  61#define IXGBE_SUBDEV_ID_82599_LOM_SFP    0x8976
  62#define IXGBE_DEV_ID_82599_SFP_EM        0x1507
  63#define IXGBE_DEV_ID_82599_SFP_SF2       0x154D
  64#define IXGBE_DEV_ID_82599EN_SFP         0x1557
  65#define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001
  66#define IXGBE_DEV_ID_82599_XAUI_LOM      0x10FC
  67#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
  68#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ  0x000C
  69#define IXGBE_DEV_ID_82599_LS            0x154F
  70#define IXGBE_DEV_ID_X540T               0x1528
  71#define IXGBE_DEV_ID_82599_SFP_SF_QP     0x154A
  72#define IXGBE_DEV_ID_X540T1              0x1560
  73
  74/* VF Device IDs */
  75#define IXGBE_DEV_ID_82599_VF           0x10ED
  76#define IXGBE_DEV_ID_X540_VF            0x1515
  77
  78/* General Registers */
  79#define IXGBE_CTRL      0x00000
  80#define IXGBE_STATUS    0x00008
  81#define IXGBE_CTRL_EXT  0x00018
  82#define IXGBE_ESDP      0x00020
  83#define IXGBE_EODSDP    0x00028
  84#define IXGBE_I2CCTL    0x00028
  85#define IXGBE_LEDCTL    0x00200
  86#define IXGBE_FRTIMER   0x00048
  87#define IXGBE_TCPTIMER  0x0004C
  88#define IXGBE_CORESPARE 0x00600
  89#define IXGBE_EXVET     0x05078
  90
  91/* NVM Registers */
  92#define IXGBE_EEC       0x10010
  93#define IXGBE_EERD      0x10014
  94#define IXGBE_EEWR      0x10018
  95#define IXGBE_FLA       0x1001C
  96#define IXGBE_EEMNGCTL  0x10110
  97#define IXGBE_EEMNGDATA 0x10114
  98#define IXGBE_FLMNGCTL  0x10118
  99#define IXGBE_FLMNGDATA 0x1011C
 100#define IXGBE_FLMNGCNT  0x10120
 101#define IXGBE_FLOP      0x1013C
 102#define IXGBE_GRC       0x10200
 103
 104/* General Receive Control */
 105#define IXGBE_GRC_MNG  0x00000001 /* Manageability Enable */
 106#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
 107
 108#define IXGBE_VPDDIAG0  0x10204
 109#define IXGBE_VPDDIAG1  0x10208
 110
 111/* I2CCTL Bit Masks */
 112#define IXGBE_I2C_CLK_IN    0x00000001
 113#define IXGBE_I2C_CLK_OUT   0x00000002
 114#define IXGBE_I2C_DATA_IN   0x00000004
 115#define IXGBE_I2C_DATA_OUT  0x00000008
 116#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT      500
 117
 118#define IXGBE_I2C_THERMAL_SENSOR_ADDR   0xF8
 119#define IXGBE_EMC_INTERNAL_DATA         0x00
 120#define IXGBE_EMC_INTERNAL_THERM_LIMIT  0x20
 121#define IXGBE_EMC_DIODE1_DATA           0x01
 122#define IXGBE_EMC_DIODE1_THERM_LIMIT    0x19
 123#define IXGBE_EMC_DIODE2_DATA           0x23
 124#define IXGBE_EMC_DIODE2_THERM_LIMIT    0x1A
 125
 126#define IXGBE_MAX_SENSORS               3
 127
 128struct ixgbe_thermal_diode_data {
 129        u8 location;
 130        u8 temp;
 131        u8 caution_thresh;
 132        u8 max_op_thresh;
 133};
 134
 135struct ixgbe_thermal_sensor_data {
 136        struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];
 137};
 138
 139/* Interrupt Registers */
 140#define IXGBE_EICR      0x00800
 141#define IXGBE_EICS      0x00808
 142#define IXGBE_EIMS      0x00880
 143#define IXGBE_EIMC      0x00888
 144#define IXGBE_EIAC      0x00810
 145#define IXGBE_EIAM      0x00890
 146#define IXGBE_EICS_EX(_i)   (0x00A90 + (_i) * 4)
 147#define IXGBE_EIMS_EX(_i)   (0x00AA0 + (_i) * 4)
 148#define IXGBE_EIMC_EX(_i)   (0x00AB0 + (_i) * 4)
 149#define IXGBE_EIAM_EX(_i)   (0x00AD0 + (_i) * 4)
 150/*
 151 * 82598 EITR is 16 bits but set the limits based on the max
 152 * supported by all ixgbe hardware.  82599 EITR is only 12 bits,
 153 * with the lower 3 always zero.
 154 */
 155#define IXGBE_MAX_INT_RATE 488281
 156#define IXGBE_MIN_INT_RATE 956
 157#define IXGBE_MAX_EITR     0x00000FF8
 158#define IXGBE_MIN_EITR     8
 159#define IXGBE_EITR(_i)  (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
 160                         (0x012300 + (((_i) - 24) * 4)))
 161#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
 162#define IXGBE_EITR_LLI_MOD      0x00008000
 163#define IXGBE_EITR_CNT_WDIS     0x80000000
 164#define IXGBE_IVAR(_i)  (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
 165#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
 166#define IXGBE_EITRSEL   0x00894
 167#define IXGBE_MSIXT     0x00000 /* MSI-X Table. 0x0000 - 0x01C */
 168#define IXGBE_MSIXPBA   0x02000 /* MSI-X Pending bit array */
 169#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
 170#define IXGBE_GPIE      0x00898
 171
 172/* Flow Control Registers */
 173#define IXGBE_FCADBUL   0x03210
 174#define IXGBE_FCADBUH   0x03214
 175#define IXGBE_FCAMACL   0x04328
 176#define IXGBE_FCAMACH   0x0432C
 177#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
 178#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
 179#define IXGBE_PFCTOP    0x03008
 180#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
 181#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
 182#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
 183#define IXGBE_FCRTV     0x032A0
 184#define IXGBE_FCCFG     0x03D00
 185#define IXGBE_TFCS      0x0CE00
 186
 187/* Receive DMA Registers */
 188#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
 189                         (0x0D000 + (((_i) - 64) * 0x40)))
 190#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
 191                         (0x0D004 + (((_i) - 64) * 0x40)))
 192#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
 193                         (0x0D008 + (((_i) - 64) * 0x40)))
 194#define IXGBE_RDH(_i)   (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
 195                         (0x0D010 + (((_i) - 64) * 0x40)))
 196#define IXGBE_RDT(_i)   (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
 197                         (0x0D018 + (((_i) - 64) * 0x40)))
 198#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
 199                         (0x0D028 + (((_i) - 64) * 0x40)))
 200#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
 201                         (0x0D02C + (((_i) - 64) * 0x40)))
 202#define IXGBE_RSCDBU     0x03028
 203#define IXGBE_RDDCC      0x02F20
 204#define IXGBE_RXMEMWRAP  0x03190
 205#define IXGBE_STARCTRL   0x03024
 206/*
 207 * Split and Replication Receive Control Registers
 208 * 00-15 : 0x02100 + n*4
 209 * 16-64 : 0x01014 + n*0x40
 210 * 64-127: 0x0D014 + (n-64)*0x40
 211 */
 212#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
 213                          (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
 214                          (0x0D014 + (((_i) - 64) * 0x40))))
 215/*
 216 * Rx DCA Control Register:
 217 * 00-15 : 0x02200 + n*4
 218 * 16-64 : 0x0100C + n*0x40
 219 * 64-127: 0x0D00C + (n-64)*0x40
 220 */
 221#define IXGBE_DCA_RXCTRL(_i)    (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
 222                                 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
 223                                 (0x0D00C + (((_i) - 64) * 0x40))))
 224#define IXGBE_RDRXCTL           0x02F00
 225#define IXGBE_RXPBSIZE(_i)      (0x03C00 + ((_i) * 4))
 226                                             /* 8 of these 0x03C00 - 0x03C1C */
 227#define IXGBE_RXCTRL    0x03000
 228#define IXGBE_DROPEN    0x03D04
 229#define IXGBE_RXPBSIZE_SHIFT 10
 230
 231/* Receive Registers */
 232#define IXGBE_RXCSUM    0x05000
 233#define IXGBE_RFCTL     0x05008
 234#define IXGBE_DRECCCTL  0x02F08
 235#define IXGBE_DRECCCTL_DISABLE 0
 236/* Multicast Table Array - 128 entries */
 237#define IXGBE_MTA(_i)   (0x05200 + ((_i) * 4))
 238#define IXGBE_RAL(_i)   (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
 239                         (0x0A200 + ((_i) * 8)))
 240#define IXGBE_RAH(_i)   (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
 241                         (0x0A204 + ((_i) * 8)))
 242#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
 243#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
 244/* Packet split receive type */
 245#define IXGBE_PSRTYPE(_i)    (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
 246                              (0x0EA00 + ((_i) * 4)))
 247/* array of 4096 1-bit vlan filters */
 248#define IXGBE_VFTA(_i)  (0x0A000 + ((_i) * 4))
 249/*array of 4096 4-bit vlan vmdq indices */
 250#define IXGBE_VFTAVIND(_j, _i)  (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
 251#define IXGBE_FCTRL     0x05080
 252#define IXGBE_VLNCTRL   0x05088
 253#define IXGBE_MCSTCTRL  0x05090
 254#define IXGBE_MRQC      0x05818
 255#define IXGBE_SAQF(_i)  (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
 256#define IXGBE_DAQF(_i)  (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
 257#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
 258#define IXGBE_FTQF(_i)  (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
 259#define IXGBE_ETQF(_i)  (0x05128 + ((_i) * 4)) /* EType Queue Filter */
 260#define IXGBE_ETQS(_i)  (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
 261#define IXGBE_SYNQF     0x0EC30 /* SYN Packet Queue Filter */
 262#define IXGBE_RQTC      0x0EC70
 263#define IXGBE_MTQC      0x08120
 264#define IXGBE_VLVF(_i)  (0x0F100 + ((_i) * 4))  /* 64 of these (0-63) */
 265#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))  /* 128 of these (0-127) */
 266#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))  /* 64 of these (0-63) */
 267#define IXGBE_VT_CTL         0x051B0
 268#define IXGBE_PFMAILBOX(_i)  (0x04B00 + (4 * (_i))) /* 64 total */
 269#define IXGBE_PFMBMEM(_i)    (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */
 270#define IXGBE_PFMBICR(_i)    (0x00710 + (4 * (_i))) /* 4 total */
 271#define IXGBE_PFMBIMR(_i)    (0x00720 + (4 * (_i))) /* 4 total */
 272#define IXGBE_VFRE(_i)       (0x051E0 + ((_i) * 4))
 273#define IXGBE_VFTE(_i)       (0x08110 + ((_i) * 4))
 274#define IXGBE_VMECM(_i)      (0x08790 + ((_i) * 4))
 275#define IXGBE_QDE            0x2F04
 276#define IXGBE_VMTXSW(_i)     (0x05180 + ((_i) * 4)) /* 2 total */
 277#define IXGBE_VMOLR(_i)      (0x0F000 + ((_i) * 4)) /* 64 total */
 278#define IXGBE_UTA(_i)        (0x0F400 + ((_i) * 4))
 279#define IXGBE_MRCTL(_i)      (0x0F600 + ((_i) * 4))
 280#define IXGBE_VMRVLAN(_i)    (0x0F610 + ((_i) * 4))
 281#define IXGBE_VMRVM(_i)      (0x0F630 + ((_i) * 4))
 282#define IXGBE_L34T_IMIR(_i)  (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
 283#define IXGBE_RXFECCERR0         0x051B8
 284#define IXGBE_LLITHRESH 0x0EC90
 285#define IXGBE_IMIR(_i)  (0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
 286#define IXGBE_IMIREXT(_i)       (0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
 287#define IXGBE_IMIRVP    0x05AC0
 288#define IXGBE_VMD_CTL   0x0581C
 289#define IXGBE_RETA(_i)  (0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
 290#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
 291
 292/* Flow Director registers */
 293#define IXGBE_FDIRCTRL  0x0EE00
 294#define IXGBE_FDIRHKEY  0x0EE68
 295#define IXGBE_FDIRSKEY  0x0EE6C
 296#define IXGBE_FDIRDIP4M 0x0EE3C
 297#define IXGBE_FDIRSIP4M 0x0EE40
 298#define IXGBE_FDIRTCPM  0x0EE44
 299#define IXGBE_FDIRUDPM  0x0EE48
 300#define IXGBE_FDIRIP6M  0x0EE74
 301#define IXGBE_FDIRM     0x0EE70
 302
 303/* Flow Director Stats registers */
 304#define IXGBE_FDIRFREE  0x0EE38
 305#define IXGBE_FDIRLEN   0x0EE4C
 306#define IXGBE_FDIRUSTAT 0x0EE50
 307#define IXGBE_FDIRFSTAT 0x0EE54
 308#define IXGBE_FDIRMATCH 0x0EE58
 309#define IXGBE_FDIRMISS  0x0EE5C
 310
 311/* Flow Director Programming registers */
 312#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
 313#define IXGBE_FDIRIPSA      0x0EE18
 314#define IXGBE_FDIRIPDA      0x0EE1C
 315#define IXGBE_FDIRPORT      0x0EE20
 316#define IXGBE_FDIRVLAN      0x0EE24
 317#define IXGBE_FDIRHASH      0x0EE28
 318#define IXGBE_FDIRCMD       0x0EE2C
 319
 320/* Transmit DMA registers */
 321#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
 322#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
 323#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
 324#define IXGBE_TDH(_i)   (0x06010 + ((_i) * 0x40))
 325#define IXGBE_TDT(_i)   (0x06018 + ((_i) * 0x40))
 326#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
 327#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
 328#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
 329#define IXGBE_DTXCTL    0x07E00
 330
 331#define IXGBE_DMATXCTL      0x04A80
 332#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
 333#define IXGBE_PFDTXGSWC     0x08220
 334#define IXGBE_DTXMXSZRQ     0x08100
 335#define IXGBE_DTXTCPFLGL    0x04A88
 336#define IXGBE_DTXTCPFLGH    0x04A8C
 337#define IXGBE_LBDRPEN       0x0CA00
 338#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
 339
 340#define IXGBE_DMATXCTL_TE       0x1 /* Transmit Enable */
 341#define IXGBE_DMATXCTL_NS       0x2 /* No Snoop LSO hdr buffer */
 342#define IXGBE_DMATXCTL_GDV      0x8 /* Global Double VLAN */
 343#define IXGBE_DMATXCTL_VT_SHIFT 16  /* VLAN EtherType */
 344
 345#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
 346
 347/* Anti-spoofing defines */
 348#define IXGBE_SPOOF_MACAS_MASK          0xFF
 349#define IXGBE_SPOOF_VLANAS_MASK         0xFF00
 350#define IXGBE_SPOOF_VLANAS_SHIFT        8
 351#define IXGBE_PFVFSPOOF_REG_COUNT       8
 352
 353#define IXGBE_DCA_TXCTRL(_i)    (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
 354/* Tx DCA Control register : 128 of these (0-127) */
 355#define IXGBE_DCA_TXCTRL_82599(_i)  (0x0600C + ((_i) * 0x40))
 356#define IXGBE_TIPG      0x0CB00
 357#define IXGBE_TXPBSIZE(_i)      (0x0CC00 + ((_i) * 4)) /* 8 of these */
 358#define IXGBE_MNGTXMAP  0x0CD10
 359#define IXGBE_TIPG_FIBER_DEFAULT 3
 360#define IXGBE_TXPBSIZE_SHIFT    10
 361
 362/* Wake up registers */
 363#define IXGBE_WUC       0x05800
 364#define IXGBE_WUFC      0x05808
 365#define IXGBE_WUS       0x05810
 366#define IXGBE_IPAV      0x05838
 367#define IXGBE_IP4AT     0x05840 /* IPv4 table 0x5840-0x5858 */
 368#define IXGBE_IP6AT     0x05880 /* IPv6 table 0x5880-0x588F */
 369
 370#define IXGBE_WUPL      0x05900
 371#define IXGBE_WUPM      0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
 372#define IXGBE_FHFT(_n)  (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
 373#define IXGBE_FHFT_EXT(_n)      (0x09800 + ((_n) * 0x100)) /* Ext Flexible Host
 374                                                            * Filter Table */
 375
 376#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX         4
 377#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
 378
 379/* Each Flexible Filter is at most 128 (0x80) bytes in length */
 380#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX  128
 381#define IXGBE_FHFT_LENGTH_OFFSET        0xFC  /* Length byte in FHFT */
 382#define IXGBE_FHFT_LENGTH_MASK          0x0FF /* Length in lower byte */
 383
 384/* Definitions for power management and wakeup registers */
 385/* Wake Up Control */
 386#define IXGBE_WUC_PME_EN     0x00000002 /* PME Enable */
 387#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
 388#define IXGBE_WUC_WKEN       0x00000010 /* Enable PE_WAKE_N pin assertion  */
 389
 390/* Wake Up Filter Control */
 391#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
 392#define IXGBE_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
 393#define IXGBE_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
 394#define IXGBE_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
 395#define IXGBE_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
 396#define IXGBE_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
 397#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
 398#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
 399#define IXGBE_WUFC_MNG  0x00000100 /* Directed Mgmt Packet Wakeup Enable */
 400
 401#define IXGBE_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
 402#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
 403#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
 404#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
 405#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
 406#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
 407#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
 408#define IXGBE_WUFC_FLX_FILTERS     0x000F0000 /* Mask for 4 flex filters */
 409#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
 410#define IXGBE_WUFC_ALL_FILTERS     0x003F00FF /* Mask for all wakeup filters */
 411#define IXGBE_WUFC_FLX_OFFSET      16 /* Offset to the Flexible Filters bits */
 412
 413/* Wake Up Status */
 414#define IXGBE_WUS_LNKC  IXGBE_WUFC_LNKC
 415#define IXGBE_WUS_MAG   IXGBE_WUFC_MAG
 416#define IXGBE_WUS_EX    IXGBE_WUFC_EX
 417#define IXGBE_WUS_MC    IXGBE_WUFC_MC
 418#define IXGBE_WUS_BC    IXGBE_WUFC_BC
 419#define IXGBE_WUS_ARP   IXGBE_WUFC_ARP
 420#define IXGBE_WUS_IPV4  IXGBE_WUFC_IPV4
 421#define IXGBE_WUS_IPV6  IXGBE_WUFC_IPV6
 422#define IXGBE_WUS_MNG   IXGBE_WUFC_MNG
 423#define IXGBE_WUS_FLX0  IXGBE_WUFC_FLX0
 424#define IXGBE_WUS_FLX1  IXGBE_WUFC_FLX1
 425#define IXGBE_WUS_FLX2  IXGBE_WUFC_FLX2
 426#define IXGBE_WUS_FLX3  IXGBE_WUFC_FLX3
 427#define IXGBE_WUS_FLX4  IXGBE_WUFC_FLX4
 428#define IXGBE_WUS_FLX5  IXGBE_WUFC_FLX5
 429#define IXGBE_WUS_FLX_FILTERS  IXGBE_WUFC_FLX_FILTERS
 430
 431/* Wake Up Packet Length */
 432#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
 433
 434/* DCB registers */
 435#define MAX_TRAFFIC_CLASS        8
 436#define X540_TRAFFIC_CLASS       4
 437#define IXGBE_RMCS      0x03D00
 438#define IXGBE_DPMCS     0x07F40
 439#define IXGBE_PDPMCS    0x0CD00
 440#define IXGBE_RUPPBMR   0x050A0
 441#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
 442#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
 443#define IXGBE_TDTQ2TCCR(_i)     (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
 444#define IXGBE_TDTQ2TCSR(_i)     (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
 445#define IXGBE_TDPT2TCCR(_i)     (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 446#define IXGBE_TDPT2TCSR(_i)     (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 447
 448
 449/* Security Control Registers */
 450#define IXGBE_SECTXCTRL         0x08800
 451#define IXGBE_SECTXSTAT         0x08804
 452#define IXGBE_SECTXBUFFAF       0x08808
 453#define IXGBE_SECTXMINIFG       0x08810
 454#define IXGBE_SECRXCTRL         0x08D00
 455#define IXGBE_SECRXSTAT         0x08D04
 456
 457/* Security Bit Fields and Masks */
 458#define IXGBE_SECTXCTRL_SECTX_DIS       0x00000001
 459#define IXGBE_SECTXCTRL_TX_DIS          0x00000002
 460#define IXGBE_SECTXCTRL_STORE_FORWARD   0x00000004
 461
 462#define IXGBE_SECTXSTAT_SECTX_RDY       0x00000001
 463#define IXGBE_SECTXSTAT_ECC_TXERR       0x00000002
 464
 465#define IXGBE_SECRXCTRL_SECRX_DIS       0x00000001
 466#define IXGBE_SECRXCTRL_RX_DIS          0x00000002
 467
 468#define IXGBE_SECRXSTAT_SECRX_RDY       0x00000001
 469#define IXGBE_SECRXSTAT_ECC_RXERR       0x00000002
 470
 471/* LinkSec (MacSec) Registers */
 472#define IXGBE_LSECTXCAP         0x08A00
 473#define IXGBE_LSECRXCAP         0x08F00
 474#define IXGBE_LSECTXCTRL        0x08A04
 475#define IXGBE_LSECTXSCL         0x08A08 /* SCI Low */
 476#define IXGBE_LSECTXSCH         0x08A0C /* SCI High */
 477#define IXGBE_LSECTXSA          0x08A10
 478#define IXGBE_LSECTXPN0         0x08A14
 479#define IXGBE_LSECTXPN1         0x08A18
 480#define IXGBE_LSECTXKEY0(_n)    (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
 481#define IXGBE_LSECTXKEY1(_n)    (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
 482#define IXGBE_LSECRXCTRL        0x08F04
 483#define IXGBE_LSECRXSCL         0x08F08
 484#define IXGBE_LSECRXSCH         0x08F0C
 485#define IXGBE_LSECRXSA(_i)      (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
 486#define IXGBE_LSECRXPN(_i)      (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
 487#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
 488#define IXGBE_LSECTXUT          0x08A3C /* OutPktsUntagged */
 489#define IXGBE_LSECTXPKTE        0x08A40 /* OutPktsEncrypted */
 490#define IXGBE_LSECTXPKTP        0x08A44 /* OutPktsProtected */
 491#define IXGBE_LSECTXOCTE        0x08A48 /* OutOctetsEncrypted */
 492#define IXGBE_LSECTXOCTP        0x08A4C /* OutOctetsProtected */
 493#define IXGBE_LSECRXUT          0x08F40 /* InPktsUntagged/InPktsNoTag */
 494#define IXGBE_LSECRXOCTD        0x08F44 /* InOctetsDecrypted */
 495#define IXGBE_LSECRXOCTV        0x08F48 /* InOctetsValidated */
 496#define IXGBE_LSECRXBAD         0x08F4C /* InPktsBadTag */
 497#define IXGBE_LSECRXNOSCI       0x08F50 /* InPktsNoSci */
 498#define IXGBE_LSECRXUNSCI       0x08F54 /* InPktsUnknownSci */
 499#define IXGBE_LSECRXUNCH        0x08F58 /* InPktsUnchecked */
 500#define IXGBE_LSECRXDELAY       0x08F5C /* InPktsDelayed */
 501#define IXGBE_LSECRXLATE        0x08F60 /* InPktsLate */
 502#define IXGBE_LSECRXOK(_n)      (0x08F64 + (0x04 * (_n))) /* InPktsOk */
 503#define IXGBE_LSECRXINV(_n)     (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
 504#define IXGBE_LSECRXNV(_n)      (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
 505#define IXGBE_LSECRXUNSA        0x08F7C /* InPktsUnusedSa */
 506#define IXGBE_LSECRXNUSA        0x08F80 /* InPktsNotUsingSa */
 507
 508/* LinkSec (MacSec) Bit Fields and Masks */
 509#define IXGBE_LSECTXCAP_SUM_MASK        0x00FF0000
 510#define IXGBE_LSECTXCAP_SUM_SHIFT       16
 511#define IXGBE_LSECRXCAP_SUM_MASK        0x00FF0000
 512#define IXGBE_LSECRXCAP_SUM_SHIFT       16
 513
 514#define IXGBE_LSECTXCTRL_EN_MASK        0x00000003
 515#define IXGBE_LSECTXCTRL_DISABLE        0x0
 516#define IXGBE_LSECTXCTRL_AUTH           0x1
 517#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT   0x2
 518#define IXGBE_LSECTXCTRL_AISCI          0x00000020
 519#define IXGBE_LSECTXCTRL_PNTHRSH_MASK   0xFFFFFF00
 520#define IXGBE_LSECTXCTRL_RSV_MASK       0x000000D8
 521
 522#define IXGBE_LSECRXCTRL_EN_MASK        0x0000000C
 523#define IXGBE_LSECRXCTRL_EN_SHIFT       2
 524#define IXGBE_LSECRXCTRL_DISABLE        0x0
 525#define IXGBE_LSECRXCTRL_CHECK          0x1
 526#define IXGBE_LSECRXCTRL_STRICT         0x2
 527#define IXGBE_LSECRXCTRL_DROP           0x3
 528#define IXGBE_LSECRXCTRL_PLSH           0x00000040
 529#define IXGBE_LSECRXCTRL_RP             0x00000080
 530#define IXGBE_LSECRXCTRL_RSV_MASK       0xFFFFFF33
 531
 532/* IpSec Registers */
 533#define IXGBE_IPSTXIDX          0x08900
 534#define IXGBE_IPSTXSALT         0x08904
 535#define IXGBE_IPSTXKEY(_i)      (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
 536#define IXGBE_IPSRXIDX          0x08E00
 537#define IXGBE_IPSRXIPADDR(_i)   (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
 538#define IXGBE_IPSRXSPI          0x08E14
 539#define IXGBE_IPSRXIPIDX        0x08E18
 540#define IXGBE_IPSRXKEY(_i)      (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
 541#define IXGBE_IPSRXSALT         0x08E2C
 542#define IXGBE_IPSRXMOD          0x08E30
 543
 544#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE    0x4
 545
 546/* DCB registers */
 547#define IXGBE_RTRPCS      0x02430
 548#define IXGBE_RTTDCS      0x04900
 549#define IXGBE_RTTDCS_ARBDIS     0x00000040 /* DCB arbiter disable */
 550#define IXGBE_RTTPCS      0x0CD00
 551#define IXGBE_RTRUP2TC    0x03020
 552#define IXGBE_RTTUP2TC    0x0C800
 553#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
 554#define IXGBE_TXLLQ(_i)   (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
 555#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
 556#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
 557#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
 558#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 559#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 560#define IXGBE_RTTDQSEL    0x04904
 561#define IXGBE_RTTDT1C     0x04908
 562#define IXGBE_RTTDT1S     0x0490C
 563#define IXGBE_RTTDTECC    0x04990
 564#define IXGBE_RTTDTECC_NO_BCN   0x00000100
 565#define IXGBE_RTTBCNRC    0x04984
 566#define IXGBE_RTTBCNRC_RS_ENA   0x80000000
 567#define IXGBE_RTTBCNRC_RF_DEC_MASK      0x00003FFF
 568#define IXGBE_RTTBCNRC_RF_INT_SHIFT     14
 569#define IXGBE_RTTBCNRC_RF_INT_MASK      \
 570        (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
 571#define IXGBE_RTTBCNRM    0x04980
 572
 573/* FCoE DMA Context Registers */
 574#define IXGBE_FCPTRL    0x02410 /* FC User Desc. PTR Low */
 575#define IXGBE_FCPTRH    0x02414 /* FC USer Desc. PTR High */
 576#define IXGBE_FCBUFF    0x02418 /* FC Buffer Control */
 577#define IXGBE_FCDMARW   0x02420 /* FC Receive DMA RW */
 578#define IXGBE_FCINVST0  0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
 579#define IXGBE_FCINVST(_i)       (IXGBE_FCINVST0 + ((_i) * 4))
 580#define IXGBE_FCBUFF_VALID      (1 << 0)   /* DMA Context Valid */
 581#define IXGBE_FCBUFF_BUFFSIZE   (3 << 3)   /* User Buffer Size */
 582#define IXGBE_FCBUFF_WRCONTX    (1 << 7)   /* 0: Initiator, 1: Target */
 583#define IXGBE_FCBUFF_BUFFCNT    0x0000ff00 /* Number of User Buffers */
 584#define IXGBE_FCBUFF_OFFSET     0xffff0000 /* User Buffer Offset */
 585#define IXGBE_FCBUFF_BUFFSIZE_SHIFT  3
 586#define IXGBE_FCBUFF_BUFFCNT_SHIFT   8
 587#define IXGBE_FCBUFF_OFFSET_SHIFT    16
 588#define IXGBE_FCDMARW_WE        (1 << 14)   /* Write enable */
 589#define IXGBE_FCDMARW_RE        (1 << 15)   /* Read enable */
 590#define IXGBE_FCDMARW_FCOESEL   0x000001ff  /* FC X_ID: 11 bits */
 591#define IXGBE_FCDMARW_LASTSIZE  0xffff0000  /* Last User Buffer Size */
 592#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
 593
 594/* FCoE SOF/EOF */
 595#define IXGBE_TEOFF     0x04A94 /* Tx FC EOF */
 596#define IXGBE_TSOFF     0x04A98 /* Tx FC SOF */
 597#define IXGBE_REOFF     0x05158 /* Rx FC EOF */
 598#define IXGBE_RSOFF     0x051F8 /* Rx FC SOF */
 599/* FCoE Filter Context Registers */
 600#define IXGBE_FCFLT     0x05108 /* FC FLT Context */
 601#define IXGBE_FCFLTRW   0x05110 /* FC Filter RW Control */
 602#define IXGBE_FCPARAM   0x051d8 /* FC Offset Parameter */
 603#define IXGBE_FCFLT_VALID       (1 << 0)   /* Filter Context Valid */
 604#define IXGBE_FCFLT_FIRST       (1 << 1)   /* Filter First */
 605#define IXGBE_FCFLT_SEQID       0x00ff0000 /* Sequence ID */
 606#define IXGBE_FCFLT_SEQCNT      0xff000000 /* Sequence Count */
 607#define IXGBE_FCFLTRW_RVALDT    (1 << 13)  /* Fast Re-Validation */
 608#define IXGBE_FCFLTRW_WE        (1 << 14)  /* Write Enable */
 609#define IXGBE_FCFLTRW_RE        (1 << 15)  /* Read Enable */
 610/* FCoE Receive Control */
 611#define IXGBE_FCRXCTRL  0x05100 /* FC Receive Control */
 612#define IXGBE_FCRXCTRL_FCOELLI  (1 << 0)   /* Low latency interrupt */
 613#define IXGBE_FCRXCTRL_SAVBAD   (1 << 1)   /* Save Bad Frames */
 614#define IXGBE_FCRXCTRL_FRSTRDH  (1 << 2)   /* EN 1st Read Header */
 615#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3)   /* EN Last Header in Seq */
 616#define IXGBE_FCRXCTRL_ALLH     (1 << 4)   /* EN All Headers */
 617#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5)   /* EN 1st Seq. Header */
 618#define IXGBE_FCRXCTRL_ICRC     (1 << 6)   /* Ignore Bad FC CRC */
 619#define IXGBE_FCRXCTRL_FCCRCBO  (1 << 7)   /* FC CRC Byte Ordering */
 620#define IXGBE_FCRXCTRL_FCOEVER  0x00000f00 /* FCoE Version: 4 bits */
 621#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
 622/* FCoE Redirection */
 623#define IXGBE_FCRECTL   0x0ED00 /* FC Redirection Control */
 624#define IXGBE_FCRETA0   0x0ED10 /* FC Redirection Table 0 */
 625#define IXGBE_FCRETA(_i)        (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
 626#define IXGBE_FCRECTL_ENA       0x1        /* FCoE Redir Table Enable */
 627#define IXGBE_FCRETA_SIZE       8          /* Max entries in FCRETA */
 628#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
 629
 630/* Stats registers */
 631#define IXGBE_CRCERRS   0x04000
 632#define IXGBE_ILLERRC   0x04004
 633#define IXGBE_ERRBC     0x04008
 634#define IXGBE_MSPDC     0x04010
 635#define IXGBE_MPC(_i)   (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
 636#define IXGBE_MLFC      0x04034
 637#define IXGBE_MRFC      0x04038
 638#define IXGBE_RLEC      0x04040
 639#define IXGBE_LXONTXC   0x03F60
 640#define IXGBE_LXONRXC   0x0CF60
 641#define IXGBE_LXOFFTXC  0x03F68
 642#define IXGBE_LXOFFRXC  0x0CF68
 643#define IXGBE_LXONRXCNT 0x041A4
 644#define IXGBE_LXOFFRXCNT 0x041A8
 645#define IXGBE_PXONRXCNT(_i)     (0x04140 + ((_i) * 4)) /* 8 of these */
 646#define IXGBE_PXOFFRXCNT(_i)    (0x04160 + ((_i) * 4)) /* 8 of these */
 647#define IXGBE_PXON2OFFCNT(_i)   (0x03240 + ((_i) * 4)) /* 8 of these */
 648#define IXGBE_PXONTXC(_i)       (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
 649#define IXGBE_PXONRXC(_i)       (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
 650#define IXGBE_PXOFFTXC(_i)      (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
 651#define IXGBE_PXOFFRXC(_i)      (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
 652#define IXGBE_PRC64     0x0405C
 653#define IXGBE_PRC127    0x04060
 654#define IXGBE_PRC255    0x04064
 655#define IXGBE_PRC511    0x04068
 656#define IXGBE_PRC1023   0x0406C
 657#define IXGBE_PRC1522   0x04070
 658#define IXGBE_GPRC      0x04074
 659#define IXGBE_BPRC      0x04078
 660#define IXGBE_MPRC      0x0407C
 661#define IXGBE_GPTC      0x04080
 662#define IXGBE_GORCL     0x04088
 663#define IXGBE_GORCH     0x0408C
 664#define IXGBE_GOTCL     0x04090
 665#define IXGBE_GOTCH     0x04094
 666#define IXGBE_RNBC(_i)  (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
 667#define IXGBE_RUC       0x040A4
 668#define IXGBE_RFC       0x040A8
 669#define IXGBE_ROC       0x040AC
 670#define IXGBE_RJC       0x040B0
 671#define IXGBE_MNGPRC    0x040B4
 672#define IXGBE_MNGPDC    0x040B8
 673#define IXGBE_MNGPTC    0x0CF90
 674#define IXGBE_TORL      0x040C0
 675#define IXGBE_TORH      0x040C4
 676#define IXGBE_TPR       0x040D0
 677#define IXGBE_TPT       0x040D4
 678#define IXGBE_PTC64     0x040D8
 679#define IXGBE_PTC127    0x040DC
 680#define IXGBE_PTC255    0x040E0
 681#define IXGBE_PTC511    0x040E4
 682#define IXGBE_PTC1023   0x040E8
 683#define IXGBE_PTC1522   0x040EC
 684#define IXGBE_MPTC      0x040F0
 685#define IXGBE_BPTC      0x040F4
 686#define IXGBE_XEC       0x04120
 687#define IXGBE_SSVPC     0x08780
 688
 689#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
 690#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
 691                         (0x08600 + ((_i) * 4)))
 692#define IXGBE_TQSM(_i)  (0x08600 + ((_i) * 4))
 693
 694#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
 695#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
 696#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
 697#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
 698#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
 699#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
 700#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
 701#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
 702#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
 703#define IXGBE_FCCRC     0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
 704#define IXGBE_FCOERPDC  0x0241C /* FCoE Rx Packets Dropped Count */
 705#define IXGBE_FCLAST    0x02424 /* FCoE Last Error Count */
 706#define IXGBE_FCOEPRC   0x02428 /* Number of FCoE Packets Received */
 707#define IXGBE_FCOEDWRC  0x0242C /* Number of FCoE DWords Received */
 708#define IXGBE_FCOEPTC   0x08784 /* Number of FCoE Packets Transmitted */
 709#define IXGBE_FCOEDWTC  0x08788 /* Number of FCoE DWords Transmitted */
 710#define IXGBE_O2BGPTC   0x041C4
 711#define IXGBE_O2BSPC    0x087B0
 712#define IXGBE_B2OSPC    0x041C0
 713#define IXGBE_B2OGPRC   0x02F90
 714#define IXGBE_PCRC8ECL  0x0E810
 715#define IXGBE_PCRC8ECH  0x0E811
 716#define IXGBE_PCRC8ECH_MASK     0x1F
 717#define IXGBE_LDPCECL   0x0E820
 718#define IXGBE_LDPCECH   0x0E821
 719
 720/* Management */
 721#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
 722#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
 723#define IXGBE_MANC      0x05820
 724#define IXGBE_MFVAL     0x05824
 725#define IXGBE_MANC2H    0x05860
 726#define IXGBE_MDEF(_i)  (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
 727#define IXGBE_MIPAF     0x058B0
 728#define IXGBE_MMAL(_i)  (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
 729#define IXGBE_MMAH(_i)  (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
 730#define IXGBE_FTFT      0x09400 /* 0x9400-0x97FC */
 731#define IXGBE_METF(_i)  (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
 732#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
 733#define IXGBE_LSWFW     0x15014
 734
 735/* Management Bit Fields and Masks */
 736#define IXGBE_MANC_RCV_TCO_EN   0x00020000 /* Rcv TCO packet enable */
 737
 738/* Firmware Semaphore Register */
 739#define IXGBE_FWSM_MODE_MASK    0xE
 740#define IXGBE_FWSM_FW_MODE_PT   0x4
 741
 742/* ARC Subsystem registers */
 743#define IXGBE_HICR      0x15F00
 744#define IXGBE_FWSTS     0x15F0C
 745#define IXGBE_HSMC0R    0x15F04
 746#define IXGBE_HSMC1R    0x15F08
 747#define IXGBE_SWSR      0x15F10
 748#define IXGBE_HFDR      0x15FE8
 749#define IXGBE_FLEX_MNG  0x15800 /* 0x15800 - 0x15EFC */
 750
 751#define IXGBE_HICR_EN              0x01  /* Enable bit - RO */
 752/* Driver sets this bit when done to put command in RAM */
 753#define IXGBE_HICR_C               0x02
 754#define IXGBE_HICR_SV              0x04  /* Status Validity */
 755#define IXGBE_HICR_FW_RESET_ENABLE 0x40
 756#define IXGBE_HICR_FW_RESET        0x80
 757
 758/* PCI-E registers */
 759#define IXGBE_GCR       0x11000
 760#define IXGBE_GTV       0x11004
 761#define IXGBE_FUNCTAG   0x11008
 762#define IXGBE_GLT       0x1100C
 763#define IXGBE_GSCL_1    0x11010
 764#define IXGBE_GSCL_2    0x11014
 765#define IXGBE_GSCL_3    0x11018
 766#define IXGBE_GSCL_4    0x1101C
 767#define IXGBE_GSCN_0    0x11020
 768#define IXGBE_GSCN_1    0x11024
 769#define IXGBE_GSCN_2    0x11028
 770#define IXGBE_GSCN_3    0x1102C
 771#define IXGBE_FACTPS    0x10150
 772#define IXGBE_PCIEANACTL  0x11040
 773#define IXGBE_SWSM      0x10140
 774#define IXGBE_FWSM      0x10148
 775#define IXGBE_GSSR      0x10160
 776#define IXGBE_MREVID    0x11064
 777#define IXGBE_DCA_ID    0x11070
 778#define IXGBE_DCA_CTRL  0x11074
 779#define IXGBE_SWFW_SYNC IXGBE_GSSR
 780
 781/* PCIe registers 82599-specific */
 782#define IXGBE_GCR_EXT           0x11050
 783#define IXGBE_GSCL_5_82599      0x11030
 784#define IXGBE_GSCL_6_82599      0x11034
 785#define IXGBE_GSCL_7_82599      0x11038
 786#define IXGBE_GSCL_8_82599      0x1103C
 787#define IXGBE_PHYADR_82599      0x11040
 788#define IXGBE_PHYDAT_82599      0x11044
 789#define IXGBE_PHYCTL_82599      0x11048
 790#define IXGBE_PBACLR_82599      0x11068
 791#define IXGBE_CIAA_82599        0x11088
 792#define IXGBE_CIAD_82599        0x1108C
 793#define IXGBE_PICAUSE           0x110B0
 794#define IXGBE_PIENA             0x110B8
 795#define IXGBE_CDQ_MBR_82599     0x110B4
 796#define IXGBE_PCIESPARE         0x110BC
 797#define IXGBE_MISC_REG_82599    0x110F0
 798#define IXGBE_ECC_CTRL_0_82599  0x11100
 799#define IXGBE_ECC_CTRL_1_82599  0x11104
 800#define IXGBE_ECC_STATUS_82599  0x110E0
 801#define IXGBE_BAR_CTRL_82599    0x110F4
 802
 803/* PCI Express Control */
 804#define IXGBE_GCR_CMPL_TMOUT_MASK       0x0000F000
 805#define IXGBE_GCR_CMPL_TMOUT_10ms       0x00001000
 806#define IXGBE_GCR_CMPL_TMOUT_RESEND     0x00010000
 807#define IXGBE_GCR_CAP_VER2              0x00040000
 808
 809#define IXGBE_GCR_EXT_MSIX_EN           0x80000000
 810#define IXGBE_GCR_EXT_BUFFERS_CLEAR     0x40000000
 811#define IXGBE_GCR_EXT_VT_MODE_16        0x00000001
 812#define IXGBE_GCR_EXT_VT_MODE_32        0x00000002
 813#define IXGBE_GCR_EXT_VT_MODE_64        0x00000003
 814#define IXGBE_GCR_EXT_SRIOV             (IXGBE_GCR_EXT_MSIX_EN | \
 815                                         IXGBE_GCR_EXT_VT_MODE_64)
 816
 817/* Time Sync Registers */
 818#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
 819#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
 820#define IXGBE_RXSTMPL    0x051E8 /* Rx timestamp Low - RO */
 821#define IXGBE_RXSTMPH    0x051A4 /* Rx timestamp High - RO */
 822#define IXGBE_RXSATRL    0x051A0 /* Rx timestamp attribute low - RO */
 823#define IXGBE_RXSATRH    0x051A8 /* Rx timestamp attribute high - RO */
 824#define IXGBE_RXMTRL     0x05120 /* RX message type register low - RW */
 825#define IXGBE_TXSTMPL    0x08C04 /* Tx timestamp value Low - RO */
 826#define IXGBE_TXSTMPH    0x08C08 /* Tx timestamp value High - RO */
 827#define IXGBE_SYSTIML    0x08C0C /* System time register Low - RO */
 828#define IXGBE_SYSTIMH    0x08C10 /* System time register High - RO */
 829#define IXGBE_TIMINCA    0x08C14 /* Increment attributes register - RW */
 830#define IXGBE_TIMADJL    0x08C18 /* Time Adjustment Offset register Low - RW */
 831#define IXGBE_TIMADJH    0x08C1C /* Time Adjustment Offset register High - RW */
 832#define IXGBE_TSAUXC     0x08C20 /* TimeSync Auxiliary Control register - RW */
 833#define IXGBE_TRGTTIML0  0x08C24 /* Target Time Register 0 Low - RW */
 834#define IXGBE_TRGTTIMH0  0x08C28 /* Target Time Register 0 High - RW */
 835#define IXGBE_TRGTTIML1  0x08C2C /* Target Time Register 1 Low - RW */
 836#define IXGBE_TRGTTIMH1  0x08C30 /* Target Time Register 1 High - RW */
 837#define IXGBE_CLKTIML    0x08C34 /* Clock Out Time Register Low - RW */
 838#define IXGBE_CLKTIMH    0x08C38 /* Clock Out Time Register High - RW */
 839#define IXGBE_FREQOUT0   0x08C34 /* Frequency Out 0 Control register - RW */
 840#define IXGBE_FREQOUT1   0x08C38 /* Frequency Out 1 Control register - RW */
 841#define IXGBE_AUXSTMPL0  0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
 842#define IXGBE_AUXSTMPH0  0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
 843#define IXGBE_AUXSTMPL1  0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
 844#define IXGBE_AUXSTMPH1  0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
 845
 846/* Diagnostic Registers */
 847#define IXGBE_RDSTATCTL   0x02C20
 848#define IXGBE_RDSTAT(_i)  (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
 849#define IXGBE_RDHMPN      0x02F08
 850#define IXGBE_RIC_DW(_i)  (0x02F10 + ((_i) * 4))
 851#define IXGBE_RDPROBE     0x02F20
 852#define IXGBE_RDMAM       0x02F30
 853#define IXGBE_RDMAD       0x02F34
 854#define IXGBE_TDSTATCTL   0x07C20
 855#define IXGBE_TDSTAT(_i)  (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
 856#define IXGBE_TDHMPN      0x07F08
 857#define IXGBE_TDHMPN2     0x082FC
 858#define IXGBE_TXDESCIC    0x082CC
 859#define IXGBE_TIC_DW(_i)  (0x07F10 + ((_i) * 4))
 860#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
 861#define IXGBE_TDPROBE     0x07F20
 862#define IXGBE_TXBUFCTRL   0x0C600
 863#define IXGBE_TXBUFDATA0  0x0C610
 864#define IXGBE_TXBUFDATA1  0x0C614
 865#define IXGBE_TXBUFDATA2  0x0C618
 866#define IXGBE_TXBUFDATA3  0x0C61C
 867#define IXGBE_RXBUFCTRL   0x03600
 868#define IXGBE_RXBUFDATA0  0x03610
 869#define IXGBE_RXBUFDATA1  0x03614
 870#define IXGBE_RXBUFDATA2  0x03618
 871#define IXGBE_RXBUFDATA3  0x0361C
 872#define IXGBE_PCIE_DIAG(_i)     (0x11090 + ((_i) * 4)) /* 8 of these */
 873#define IXGBE_RFVAL     0x050A4
 874#define IXGBE_MDFTC1    0x042B8
 875#define IXGBE_MDFTC2    0x042C0
 876#define IXGBE_MDFTFIFO1 0x042C4
 877#define IXGBE_MDFTFIFO2 0x042C8
 878#define IXGBE_MDFTS     0x042CC
 879#define IXGBE_RXDATAWRPTR(_i)   (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
 880#define IXGBE_RXDESCWRPTR(_i)   (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
 881#define IXGBE_RXDATARDPTR(_i)   (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
 882#define IXGBE_RXDESCRDPTR(_i)   (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
 883#define IXGBE_TXDATAWRPTR(_i)   (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
 884#define IXGBE_TXDESCWRPTR(_i)   (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
 885#define IXGBE_TXDATARDPTR(_i)   (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
 886#define IXGBE_TXDESCRDPTR(_i)   (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
 887#define IXGBE_PCIEECCCTL 0x1106C
 888#define IXGBE_RXWRPTR(_i)       (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
 889#define IXGBE_RXUSED(_i)        (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
 890#define IXGBE_RXRDPTR(_i)       (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
 891#define IXGBE_RXRDWRPTR(_i)     (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
 892#define IXGBE_TXWRPTR(_i)       (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
 893#define IXGBE_TXUSED(_i)        (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
 894#define IXGBE_TXRDPTR(_i)       (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
 895#define IXGBE_TXRDWRPTR(_i)     (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
 896#define IXGBE_PCIEECCCTL0 0x11100
 897#define IXGBE_PCIEECCCTL1 0x11104
 898#define IXGBE_RXDBUECC  0x03F70
 899#define IXGBE_TXDBUECC  0x0CF70
 900#define IXGBE_RXDBUEST 0x03F74
 901#define IXGBE_TXDBUEST 0x0CF74
 902#define IXGBE_PBTXECC   0x0C300
 903#define IXGBE_PBRXECC   0x03300
 904#define IXGBE_GHECCR    0x110B0
 905
 906/* MAC Registers */
 907#define IXGBE_PCS1GCFIG 0x04200
 908#define IXGBE_PCS1GLCTL 0x04208
 909#define IXGBE_PCS1GLSTA 0x0420C
 910#define IXGBE_PCS1GDBG0 0x04210
 911#define IXGBE_PCS1GDBG1 0x04214
 912#define IXGBE_PCS1GANA  0x04218
 913#define IXGBE_PCS1GANLP 0x0421C
 914#define IXGBE_PCS1GANNP 0x04220
 915#define IXGBE_PCS1GANLPNP 0x04224
 916#define IXGBE_HLREG0    0x04240
 917#define IXGBE_HLREG1    0x04244
 918#define IXGBE_PAP       0x04248
 919#define IXGBE_MACA      0x0424C
 920#define IXGBE_APAE      0x04250
 921#define IXGBE_ARD       0x04254
 922#define IXGBE_AIS       0x04258
 923#define IXGBE_MSCA      0x0425C
 924#define IXGBE_MSRWD     0x04260
 925#define IXGBE_MLADD     0x04264
 926#define IXGBE_MHADD     0x04268
 927#define IXGBE_MAXFRS    0x04268
 928#define IXGBE_TREG      0x0426C
 929#define IXGBE_PCSS1     0x04288
 930#define IXGBE_PCSS2     0x0428C
 931#define IXGBE_XPCSS     0x04290
 932#define IXGBE_MFLCN     0x04294
 933#define IXGBE_SERDESC   0x04298
 934#define IXGBE_MACS      0x0429C
 935#define IXGBE_AUTOC     0x042A0
 936#define IXGBE_LINKS     0x042A4
 937#define IXGBE_LINKS2    0x04324
 938#define IXGBE_AUTOC2    0x042A8
 939#define IXGBE_AUTOC3    0x042AC
 940#define IXGBE_ANLP1     0x042B0
 941#define IXGBE_ANLP2     0x042B4
 942#define IXGBE_MACC      0x04330
 943#define IXGBE_ATLASCTL  0x04800
 944#define IXGBE_MMNGC     0x042D0
 945#define IXGBE_ANLPNP1   0x042D4
 946#define IXGBE_ANLPNP2   0x042D8
 947#define IXGBE_KRPCSFC   0x042E0
 948#define IXGBE_KRPCSS    0x042E4
 949#define IXGBE_FECS1     0x042E8
 950#define IXGBE_FECS2     0x042EC
 951#define IXGBE_SMADARCTL 0x14F10
 952#define IXGBE_MPVC      0x04318
 953#define IXGBE_SGMIIC    0x04314
 954
 955/* Statistics Registers */
 956#define IXGBE_RXNFGPC      0x041B0
 957#define IXGBE_RXNFGBCL     0x041B4
 958#define IXGBE_RXNFGBCH     0x041B8
 959#define IXGBE_RXDGPC       0x02F50
 960#define IXGBE_RXDGBCL      0x02F54
 961#define IXGBE_RXDGBCH      0x02F58
 962#define IXGBE_RXDDGPC      0x02F5C
 963#define IXGBE_RXDDGBCL     0x02F60
 964#define IXGBE_RXDDGBCH     0x02F64
 965#define IXGBE_RXLPBKGPC    0x02F68
 966#define IXGBE_RXLPBKGBCL   0x02F6C
 967#define IXGBE_RXLPBKGBCH   0x02F70
 968#define IXGBE_RXDLPBKGPC   0x02F74
 969#define IXGBE_RXDLPBKGBCL  0x02F78
 970#define IXGBE_RXDLPBKGBCH  0x02F7C
 971#define IXGBE_TXDGPC       0x087A0
 972#define IXGBE_TXDGBCL      0x087A4
 973#define IXGBE_TXDGBCH      0x087A8
 974
 975#define IXGBE_RXDSTATCTRL 0x02F40
 976
 977/* Copper Pond 2 link timeout */
 978#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
 979
 980/* Omer CORECTL */
 981#define IXGBE_CORECTL           0x014F00
 982/* BARCTRL */
 983#define IXGBE_BARCTRL               0x110F4
 984#define IXGBE_BARCTRL_FLSIZE        0x0700
 985#define IXGBE_BARCTRL_FLSIZE_SHIFT  8
 986#define IXGBE_BARCTRL_CSRSIZE       0x2000
 987
 988/* RSCCTL Bit Masks */
 989#define IXGBE_RSCCTL_RSCEN          0x01
 990#define IXGBE_RSCCTL_MAXDESC_1      0x00
 991#define IXGBE_RSCCTL_MAXDESC_4      0x04
 992#define IXGBE_RSCCTL_MAXDESC_8      0x08
 993#define IXGBE_RSCCTL_MAXDESC_16     0x0C
 994
 995/* RSCDBU Bit Masks */
 996#define IXGBE_RSCDBU_RSCSMALDIS_MASK    0x0000007F
 997#define IXGBE_RSCDBU_RSCACKDIS          0x00000080
 998
 999/* RDRXCTL Bit Masks */
1000#define IXGBE_RDRXCTL_RDMTS_1_2     0x00000000 /* Rx Desc Min Threshold Size */

1001#define IXGBE_RDRXCTL_CRCSTRIP      0x00000002 /* CRC Strip */
1002#define IXGBE_RDRXCTL_MVMEN         0x00000020
1003#define IXGBE_RDRXCTL_DMAIDONE      0x00000008 /* DMA init cycle done */
1004#define IXGBE_RDRXCTL_AGGDIS        0x00010000 /* Aggregation disable */
1005#define IXGBE_RDRXCTL_RSCFRSTSIZE   0x003E0000 /* RSC First packet size */
1006#define IXGBE_RDRXCTL_RSCLLIDIS     0x00800000 /* Disable RSC compl on LLI */
1007#define IXGBE_RDRXCTL_RSCACKC       0x02000000 /* must set 1 when RSC enabled */
1008#define IXGBE_RDRXCTL_FCOE_WRFIX    0x04000000 /* must set 1 when RSC enabled */
1009
1010/* RQTC Bit Masks and Shifts */
1011#define IXGBE_RQTC_SHIFT_TC(_i)     ((_i) * 4)
1012#define IXGBE_RQTC_TC0_MASK         (0x7 << 0)
1013#define IXGBE_RQTC_TC1_MASK         (0x7 << 4)
1014#define IXGBE_RQTC_TC2_MASK         (0x7 << 8)
1015#define IXGBE_RQTC_TC3_MASK         (0x7 << 12)
1016#define IXGBE_RQTC_TC4_MASK         (0x7 << 16)
1017#define IXGBE_RQTC_TC5_MASK         (0x7 << 20)
1018#define IXGBE_RQTC_TC6_MASK         (0x7 << 24)
1019#define IXGBE_RQTC_TC7_MASK         (0x7 << 28)
1020
1021/* PSRTYPE.RQPL Bit masks and shift */
1022#define IXGBE_PSRTYPE_RQPL_MASK     0x7
1023#define IXGBE_PSRTYPE_RQPL_SHIFT    29
1024
1025/* CTRL Bit Masks */
1026#define IXGBE_CTRL_GIO_DIS      0x00000004 /* Global IO Master Disable bit */
1027#define IXGBE_CTRL_LNK_RST      0x00000008 /* Link Reset. Resets everything. */
1028#define IXGBE_CTRL_RST          0x04000000 /* Reset (SW) */
1029#define IXGBE_CTRL_RST_MASK     (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1030
1031/* FACTPS */
1032#define IXGBE_FACTPS_MNGCG      0x20000000 /* Manageblility Clock Gated */
1033#define IXGBE_FACTPS_LFS        0x40000000 /* LAN Function Select */
1034
1035/* MHADD Bit Masks */
1036#define IXGBE_MHADD_MFS_MASK    0xFFFF0000
1037#define IXGBE_MHADD_MFS_SHIFT   16
1038
1039/* Extended Device Control */
1040#define IXGBE_CTRL_EXT_PFRSTD   0x00004000 /* Physical Function Reset Done */
1041#define IXGBE_CTRL_EXT_NS_DIS   0x00010000 /* No Snoop disable */
1042#define IXGBE_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */
1043#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1044
1045/* Direct Cache Access (DCA) definitions */
1046#define IXGBE_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
1047#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
1048
1049#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
1050#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
1051
1052#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
1053#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599  0xFF000000 /* Rx CPUID Mask */
1054#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
1055#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
1056#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
1057#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
1058#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
1059#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */
1060#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */
1061
1062#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
1063#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599  0xFF000000 /* Tx CPUID Mask */
1064#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
1065#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
1066#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
1067#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */
1068#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
1069#define IXGBE_DCA_MAX_QUEUES_82598   16 /* DCA regs only on 16 queues */
1070
1071/* MSCA Bit Masks */
1072#define IXGBE_MSCA_NP_ADDR_MASK      0x0000FFFF /* MDI Address (new protocol) */
1073#define IXGBE_MSCA_NP_ADDR_SHIFT     0
1074#define IXGBE_MSCA_DEV_TYPE_MASK     0x001F0000 /* Device Type (new protocol) */
1075#define IXGBE_MSCA_DEV_TYPE_SHIFT    16 /* Register Address (old protocol */
1076#define IXGBE_MSCA_PHY_ADDR_MASK     0x03E00000 /* PHY Address mask */
1077#define IXGBE_MSCA_PHY_ADDR_SHIFT    21 /* PHY Address shift*/
1078#define IXGBE_MSCA_OP_CODE_MASK      0x0C000000 /* OP CODE mask */
1079#define IXGBE_MSCA_OP_CODE_SHIFT     26 /* OP CODE shift */
1080#define IXGBE_MSCA_ADDR_CYCLE        0x00000000 /* OP CODE 00 (addr cycle) */
1081#define IXGBE_MSCA_WRITE             0x04000000 /* OP CODE 01 (write) */
1082#define IXGBE_MSCA_READ              0x0C000000 /* OP CODE 11 (read) */
1083#define IXGBE_MSCA_READ_AUTOINC      0x08000000 /* OP CODE 10 (read, auto inc)*/
1084#define IXGBE_MSCA_ST_CODE_MASK      0x30000000 /* ST Code mask */
1085#define IXGBE_MSCA_ST_CODE_SHIFT     28 /* ST Code shift */
1086#define IXGBE_MSCA_NEW_PROTOCOL      0x00000000 /* ST CODE 00 (new protocol) */
1087#define IXGBE_MSCA_OLD_PROTOCOL      0x10000000 /* ST CODE 01 (old protocol) */
1088#define IXGBE_MSCA_MDI_COMMAND       0x40000000 /* Initiate MDI command */
1089#define IXGBE_MSCA_MDI_IN_PROG_EN    0x80000000 /* MDI in progress enable */
1090
1091/* MSRWD bit masks */
1092#define IXGBE_MSRWD_WRITE_DATA_MASK     0x0000FFFF
1093#define IXGBE_MSRWD_WRITE_DATA_SHIFT    0
1094#define IXGBE_MSRWD_READ_DATA_MASK      0xFFFF0000
1095#define IXGBE_MSRWD_READ_DATA_SHIFT     16
1096
1097/* Atlas registers */
1098#define IXGBE_ATLAS_PDN_LPBK    0x24
1099#define IXGBE_ATLAS_PDN_10G     0xB
1100#define IXGBE_ATLAS_PDN_1G      0xC
1101#define IXGBE_ATLAS_PDN_AN      0xD
1102
1103/* Atlas bit masks */
1104#define IXGBE_ATLASCTL_WRITE_CMD        0x00010000
1105#define IXGBE_ATLAS_PDN_TX_REG_EN       0x10
1106#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL   0xF0
1107#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL    0xF0
1108#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL    0xF0
1109
1110/* Omer bit masks */
1111#define IXGBE_CORECTL_WRITE_CMD         0x00010000
1112
1113/* MDIO definitions */
1114
1115#define IXGBE_MDIO_COMMAND_TIMEOUT     100 /* PHY Timeout for 1 GB mode */
1116
1117#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL      0x0    /* VS1 Control Reg */
1118#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS       0x1    /* VS1 Status Reg */
1119#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS  0x0008 /* 1 = Link Up */
1120#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
1121#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED    0x0018
1122#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED     0x0010
1123
1124#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR     0xC30A /* PHY_XS SDA/SCL Addr Reg */
1125#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA     0xC30B /* PHY_XS SDA/SCL Data Reg */
1126#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT     0xC30C /* PHY_XS SDA/SCL Status Reg */
1127
1128/* MII clause 22/28 definitions */
1129#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1130#define IXGBE_MII_AUTONEG_XNP_TX_REG             0x17   /* 1G XNP Transmit */
1131#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX      0x4000 /* full duplex, bit:14*/
1132#define IXGBE_MII_1GBASE_T_ADVERTISE             0x8000 /* full duplex, bit:15*/
1133#define IXGBE_MII_AUTONEG_REG                    0x0
1134
1135#define IXGBE_PHY_REVISION_MASK        0xFFFFFFF0
1136#define IXGBE_MAX_PHY_ADDR             32
1137
1138/* PHY IDs*/
1139#define TN1010_PHY_ID    0x00A19410
1140#define TNX_FW_REV       0xB
1141#define X540_PHY_ID      0x01540200
1142#define QT2022_PHY_ID    0x0043A400
1143#define ATH_PHY_ID       0x03429050
1144#define AQ_FW_REV        0x20
1145
1146/* PHY Types */
1147#define IXGBE_M88E1145_E_PHY_ID  0x01410CD0
1148
1149/* Special PHY Init Routine */
1150#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1151#define IXGBE_PHY_INIT_END_NL    0xFFFF
1152#define IXGBE_CONTROL_MASK_NL    0xF000
1153#define IXGBE_DATA_MASK_NL       0x0FFF
1154#define IXGBE_CONTROL_SHIFT_NL   12
1155#define IXGBE_DELAY_NL           0
1156#define IXGBE_DATA_NL            1
1157#define IXGBE_CONTROL_NL         0x000F
1158#define IXGBE_CONTROL_EOL_NL     0x0FFF
1159#define IXGBE_CONTROL_SOL_NL     0x0000
1160
1161/* General purpose Interrupt Enable */
1162#define IXGBE_SDP0_GPIEN         0x00000001 /* SDP0 */
1163#define IXGBE_SDP1_GPIEN         0x00000002 /* SDP1 */
1164#define IXGBE_SDP2_GPIEN         0x00000004 /* SDP2 */
1165#define IXGBE_GPIE_MSIX_MODE     0x00000010 /* MSI-X mode */
1166#define IXGBE_GPIE_OCD           0x00000020 /* Other Clear Disable */
1167#define IXGBE_GPIE_EIMEN         0x00000040 /* Immediate Interrupt Enable */
1168#define IXGBE_GPIE_EIAME         0x40000000
1169#define IXGBE_GPIE_PBA_SUPPORT   0x80000000
1170#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
1171#define IXGBE_GPIE_VTMODE_MASK   0x0000C000 /* VT Mode Mask */
1172#define IXGBE_GPIE_VTMODE_16     0x00004000 /* 16 VFs 8 queues per VF */
1173#define IXGBE_GPIE_VTMODE_32     0x00008000 /* 32 VFs 4 queues per VF */
1174#define IXGBE_GPIE_VTMODE_64     0x0000C000 /* 64 VFs 2 queues per VF */
1175
1176/* Packet Buffer Initialization */
1177#define IXGBE_TXPBSIZE_20KB     0x00005000 /* 20KB Packet Buffer */
1178#define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
1179#define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
1180#define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
1181#define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
1182#define IXGBE_RXPBSIZE_128KB    0x00020000 /* 128KB Packet Buffer */
1183#define IXGBE_RXPBSIZE_MAX      0x00080000 /* 512KB Packet Buffer*/
1184#define IXGBE_TXPBSIZE_MAX      0x00028000 /* 160KB Packet Buffer*/
1185
1186#define IXGBE_TXPKT_SIZE_MAX    0xA        /* Max Tx Packet size  */
1187#define IXGBE_MAX_PB            8
1188
1189/* Packet buffer allocation strategies */
1190enum {
1191        PBA_STRATEGY_EQUAL      = 0,    /* Distribute PB space equally */
1192#define PBA_STRATEGY_EQUAL      PBA_STRATEGY_EQUAL
1193        PBA_STRATEGY_WEIGHTED   = 1,    /* Weight front half of TCs */
1194#define PBA_STRATEGY_WEIGHTED   PBA_STRATEGY_WEIGHTED
1195};
1196
1197/* Transmit Flow Control status */
1198#define IXGBE_TFCS_TXOFF         0x00000001
1199#define IXGBE_TFCS_TXOFF0        0x00000100
1200#define IXGBE_TFCS_TXOFF1        0x00000200
1201#define IXGBE_TFCS_TXOFF2        0x00000400
1202#define IXGBE_TFCS_TXOFF3        0x00000800
1203#define IXGBE_TFCS_TXOFF4        0x00001000
1204#define IXGBE_TFCS_TXOFF5        0x00002000
1205#define IXGBE_TFCS_TXOFF6        0x00004000
1206#define IXGBE_TFCS_TXOFF7        0x00008000
1207
1208/* TCP Timer */
1209#define IXGBE_TCPTIMER_KS            0x00000100
1210#define IXGBE_TCPTIMER_COUNT_ENABLE  0x00000200
1211#define IXGBE_TCPTIMER_COUNT_FINISH  0x00000400
1212#define IXGBE_TCPTIMER_LOOP          0x00000800
1213#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1214
1215/* HLREG0 Bit Masks */
1216#define IXGBE_HLREG0_TXCRCEN      0x00000001   /* bit  0 */
1217#define IXGBE_HLREG0_RXCRCSTRP    0x00000002   /* bit  1 */
1218#define IXGBE_HLREG0_JUMBOEN      0x00000004   /* bit  2 */
1219#define IXGBE_HLREG0_TXPADEN      0x00000400   /* bit 10 */
1220#define IXGBE_HLREG0_TXPAUSEEN    0x00001000   /* bit 12 */
1221#define IXGBE_HLREG0_RXPAUSEEN    0x00004000   /* bit 14 */
1222#define IXGBE_HLREG0_LPBK         0x00008000   /* bit 15 */
1223#define IXGBE_HLREG0_MDCSPD       0x00010000   /* bit 16 */
1224#define IXGBE_HLREG0_CONTMDC      0x00020000   /* bit 17 */
1225#define IXGBE_HLREG0_CTRLFLTR     0x00040000   /* bit 18 */
1226#define IXGBE_HLREG0_PREPEND      0x00F00000   /* bits 20-23 */
1227#define IXGBE_HLREG0_PRIPAUSEEN   0x01000000   /* bit 24 */
1228#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000   /* bits 25-26 */
1229#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000   /* bit 27 */
1230#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000   /* bit 28 */
1231
1232/* VMD_CTL bitmasks */
1233#define IXGBE_VMD_CTL_VMDQ_EN     0x00000001
1234#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1235
1236/* VT_CTL bitmasks */
1237#define IXGBE_VT_CTL_DIS_DEFPL  0x20000000 /* disable default pool */
1238#define IXGBE_VT_CTL_REPLEN     0x40000000 /* replication enabled */
1239#define IXGBE_VT_CTL_VT_ENABLE  0x00000001  /* Enable VT Mode */
1240#define IXGBE_VT_CTL_POOL_SHIFT 7
1241#define IXGBE_VT_CTL_POOL_MASK  (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1242
1243/* VMOLR bitmasks */
1244#define IXGBE_VMOLR_AUPE        0x01000000 /* accept untagged packets */
1245#define IXGBE_VMOLR_ROMPE       0x02000000 /* accept packets in MTA tbl */
1246#define IXGBE_VMOLR_ROPE        0x04000000 /* accept packets in UC tbl */
1247#define IXGBE_VMOLR_BAM         0x08000000 /* accept broadcast packets */
1248#define IXGBE_VMOLR_MPE         0x10000000 /* multicast promiscuous */
1249
1250/* VFRE bitmask */
1251#define IXGBE_VFRE_ENABLE_ALL   0xFFFFFFFF
1252
1253#define IXGBE_VF_INIT_TIMEOUT   200 /* Number of retries to clear RSTI */
1254
1255/* RDHMPN and TDHMPN bitmasks */
1256#define IXGBE_RDHMPN_RDICADDR       0x007FF800
1257#define IXGBE_RDHMPN_RDICRDREQ      0x00800000
1258#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1259#define IXGBE_TDHMPN_TDICADDR       0x003FF800
1260#define IXGBE_TDHMPN_TDICRDREQ      0x00800000
1261#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1262
1263#define IXGBE_RDMAM_MEM_SEL_SHIFT   13
1264#define IXGBE_RDMAM_DWORD_SHIFT     9
1265#define IXGBE_RDMAM_DESC_COMP_FIFO  1
1266#define IXGBE_RDMAM_DFC_CMD_FIFO    2
1267#define IXGBE_RDMAM_TCN_STATUS_RAM  4
1268#define IXGBE_RDMAM_WB_COLL_FIFO    5
1269#define IXGBE_RDMAM_QSC_CNT_RAM     6
1270#define IXGBE_RDMAM_QSC_QUEUE_CNT   8
1271#define IXGBE_RDMAM_QSC_QUEUE_RAM   0xA
1272#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE     135
1273#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT     4
1274#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE      48
1275#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT      7
1276#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE    256
1277#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT    9
1278#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE      8
1279#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT      4
1280#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE       64
1281#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT       4
1282#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE     32
1283#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT     4
1284#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE     128
1285#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT     8
1286
1287#define IXGBE_TXDESCIC_READY        0x80000000
1288
1289/* Receive Checksum Control */
1290#define IXGBE_RXCSUM_IPPCSE     0x00001000   /* IP payload checksum enable */
1291#define IXGBE_RXCSUM_PCSD       0x00002000   /* packet checksum disabled */
1292
1293/* FCRTL Bit Masks */
1294#define IXGBE_FCRTL_XONE        0x80000000  /* XON enable */
1295#define IXGBE_FCRTH_FCEN        0x80000000  /* Packet buffer fc enable */
1296
1297/* PAP bit masks*/
1298#define IXGBE_PAP_TXPAUSECNT_MASK   0x0000FFFF /* Pause counter mask */
1299
1300/* RMCS Bit Masks */
1301#define IXGBE_RMCS_RRM          0x00000002 /* Receive Recycle Mode enable */
1302/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1303#define IXGBE_RMCS_RAC          0x00000004
1304#define IXGBE_RMCS_DFP          IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
1305#define IXGBE_RMCS_TFCE_802_3X         0x00000008 /* Tx Priority FC ena */
1306#define IXGBE_RMCS_TFCE_PRIORITY       0x00000010 /* Tx Priority FC ena */
1307#define IXGBE_RMCS_ARBDIS       0x00000040 /* Arbitration disable bit */
1308
1309/* FCCFG Bit Masks */
1310#define IXGBE_FCCFG_TFCE_802_3X         0x00000008 /* Tx link FC enable */
1311#define IXGBE_FCCFG_TFCE_PRIORITY       0x00000010 /* Tx priority FC enable */
1312
1313/* Interrupt register bitmasks */
1314
1315/* Extended Interrupt Cause Read */
1316#define IXGBE_EICR_RTX_QUEUE    0x0000FFFF /* RTx Queue Interrupt */
1317#define IXGBE_EICR_FLOW_DIR     0x00010000 /* FDir Exception */
1318#define IXGBE_EICR_RX_MISS      0x00020000 /* Packet Buffer Overrun */
1319#define IXGBE_EICR_PCI          0x00040000 /* PCI Exception */
1320#define IXGBE_EICR_MAILBOX      0x00080000 /* VF to PF Mailbox Interrupt */
1321#define IXGBE_EICR_LSC          0x00100000 /* Link Status Change */
1322#define IXGBE_EICR_LINKSEC      0x00200000 /* PN Threshold */
1323#define IXGBE_EICR_MNG          0x00400000 /* Manageability Event Interrupt */
1324#define IXGBE_EICR_TS           0x00800000 /* Thermal Sensor Event */
1325#define IXGBE_EICR_TIMESYNC     0x01000000 /* Timesync Event */
1326#define IXGBE_EICR_GPI_SDP0     0x01000000 /* Gen Purpose Interrupt on SDP0 */
1327#define IXGBE_EICR_GPI_SDP1     0x02000000 /* Gen Purpose Interrupt on SDP1 */
1328#define IXGBE_EICR_GPI_SDP2     0x04000000 /* Gen Purpose Interrupt on SDP2 */
1329#define IXGBE_EICR_ECC          0x10000000 /* ECC Error */
1330#define IXGBE_EICR_PBUR         0x10000000 /* Packet Buffer Handler Error */
1331#define IXGBE_EICR_DHER         0x20000000 /* Descriptor Handler Error */
1332#define IXGBE_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
1333#define IXGBE_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
1334
1335/* Extended Interrupt Cause Set */
1336#define IXGBE_EICS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1337#define IXGBE_EICS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1338#define IXGBE_EICS_RX_MISS      IXGBE_EICR_RX_MISS   /* Pkt Buffer Overrun */
1339#define IXGBE_EICS_PCI          IXGBE_EICR_PCI       /* PCI Exception */
1340#define IXGBE_EICS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1341#define IXGBE_EICS_LSC          IXGBE_EICR_LSC       /* Link Status Change */
1342#define IXGBE_EICS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
1343#define IXGBE_EICS_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
1344#define IXGBE_EICS_GPI_SDP0     IXGBE_EICR_GPI_SDP0  /* SDP0 Gen Purpose Int */
1345#define IXGBE_EICS_GPI_SDP1     IXGBE_EICR_GPI_SDP1  /* SDP1 Gen Purpose Int */
1346#define IXGBE_EICS_GPI_SDP2     IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
1347#define IXGBE_EICS_ECC          IXGBE_EICR_ECC       /* ECC Error */
1348#define IXGBE_EICS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
1349#define IXGBE_EICS_DHER         IXGBE_EICR_DHER      /* Desc Handler Error */
1350#define IXGBE_EICS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1351#define IXGBE_EICS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
1352
1353/* Extended Interrupt Mask Set */
1354#define IXGBE_EIMS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1355#define IXGBE_EIMS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1356#define IXGBE_EIMS_RX_MISS      IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
1357#define IXGBE_EIMS_PCI          IXGBE_EICR_PCI       /* PCI Exception */
1358#define IXGBE_EIMS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1359#define IXGBE_EIMS_LSC          IXGBE_EICR_LSC       /* Link Status Change */
1360#define IXGBE_EIMS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
1361#define IXGBE_EIMS_TS           IXGBE_EICR_TS        /* Thermel Sensor Event */
1362#define IXGBE_EIMS_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
1363#define IXGBE_EIMS_GPI_SDP0     IXGBE_EICR_GPI_SDP0  /* SDP0 Gen Purpose Int */
1364#define IXGBE_EIMS_GPI_SDP1     IXGBE_EICR_GPI_SDP1  /* SDP1 Gen Purpose Int */
1365#define IXGBE_EIMS_GPI_SDP2     IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
1366#define IXGBE_EIMS_ECC          IXGBE_EICR_ECC       /* ECC Error */
1367#define IXGBE_EIMS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
1368#define IXGBE_EIMS_DHER         IXGBE_EICR_DHER      /* Descr Handler Error */
1369#define IXGBE_EIMS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1370#define IXGBE_EIMS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
1371
1372/* Extended Interrupt Mask Clear */
1373#define IXGBE_EIMC_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1374#define IXGBE_EIMC_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1375#define IXGBE_EIMC_RX_MISS      IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
1376#define IXGBE_EIMC_PCI          IXGBE_EICR_PCI       /* PCI Exception */
1377#define IXGBE_EIMC_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1378#define IXGBE_EIMC_LSC          IXGBE_EICR_LSC       /* Link Status Change */
1379#define IXGBE_EIMC_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
1380#define IXGBE_EIMC_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
1381#define IXGBE_EIMC_GPI_SDP0     IXGBE_EICR_GPI_SDP0  /* SDP0 Gen Purpose Int */
1382#define IXGBE_EIMC_GPI_SDP1     IXGBE_EICR_GPI_SDP1  /* SDP1 Gen Purpose Int */
1383#define IXGBE_EIMC_GPI_SDP2     IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
1384#define IXGBE_EIMC_ECC          IXGBE_EICR_ECC       /* ECC Error */
1385#define IXGBE_EIMC_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
1386#define IXGBE_EIMC_DHER         IXGBE_EICR_DHER      /* Desc Handler Err */
1387#define IXGBE_EIMC_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1388#define IXGBE_EIMC_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
1389
1390#define IXGBE_EIMS_ENABLE_MASK ( \
1391                                IXGBE_EIMS_RTX_QUEUE       | \
1392                                IXGBE_EIMS_LSC             | \
1393                                IXGBE_EIMS_TCP_TIMER       | \
1394                                IXGBE_EIMS_OTHER)
1395
1396/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1397#define IXGBE_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
1398#define IXGBE_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
1399#define IXGBE_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
1400#define IXGBE_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
1401#define IXGBE_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
1402#define IXGBE_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
1403#define IXGBE_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
1404#define IXGBE_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
1405#define IXGBE_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
1406#define IXGBE_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of control bits */
1407#define IXGBE_IMIR_SIZE_BP_82599  0x00001000 /* Packet size bypass */
1408#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1409#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1410#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1411#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1412#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1413#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1414#define IXGBE_IMIR_CTRL_BP_82599  0x00080000 /* Bypass check of control bits */
1415#define IXGBE_IMIR_LLI_EN_82599   0x00100000 /* Enables low latency Int */
1416#define IXGBE_IMIR_RX_QUEUE_MASK_82599  0x0000007F /* Rx Queue Mask */
1417#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1418#define IXGBE_IMIRVP_PRIORITY_MASK      0x00000007 /* VLAN priority mask */
1419#define IXGBE_IMIRVP_PRIORITY_EN        0x00000008 /* VLAN priority enable */
1420
1421#define IXGBE_MAX_FTQF_FILTERS          128
1422#define IXGBE_FTQF_PROTOCOL_MASK        0x00000003
1423#define IXGBE_FTQF_PROTOCOL_TCP         0x00000000
1424#define IXGBE_FTQF_PROTOCOL_UDP         0x00000001
1425#define IXGBE_FTQF_PROTOCOL_SCTP        2
1426#define IXGBE_FTQF_PRIORITY_MASK        0x00000007
1427#define IXGBE_FTQF_PRIORITY_SHIFT       2
1428#define IXGBE_FTQF_POOL_MASK            0x0000003F
1429#define IXGBE_FTQF_POOL_SHIFT           8
1430#define IXGBE_FTQF_5TUPLE_MASK_MASK     0x0000001F
1431#define IXGBE_FTQF_5TUPLE_MASK_SHIFT    25
1432#define IXGBE_FTQF_SOURCE_ADDR_MASK     0x1E
1433#define IXGBE_FTQF_DEST_ADDR_MASK       0x1D
1434#define IXGBE_FTQF_SOURCE_PORT_MASK     0x1B
1435#define IXGBE_FTQF_DEST_PORT_MASK       0x17
1436#define IXGBE_FTQF_PROTOCOL_COMP_MASK   0x0F
1437#define IXGBE_FTQF_POOL_MASK_EN         0x40000000
1438#define IXGBE_FTQF_QUEUE_ENABLE         0x80000000
1439
1440/* Interrupt clear mask */
1441#define IXGBE_IRQ_CLEAR_MASK    0xFFFFFFFF
1442
1443/* Interrupt Vector Allocation Registers */
1444#define IXGBE_IVAR_REG_NUM      25
1445#define IXGBE_IVAR_REG_NUM_82599       64
1446#define IXGBE_IVAR_TXRX_ENTRY   96
1447#define IXGBE_IVAR_RX_ENTRY     64
1448#define IXGBE_IVAR_RX_QUEUE(_i)    (0 + (_i))
1449#define IXGBE_IVAR_TX_QUEUE(_i)    (64 + (_i))
1450#define IXGBE_IVAR_TX_ENTRY     32
1451
1452#define IXGBE_IVAR_TCP_TIMER_INDEX       96 /* 0 based index */
1453#define IXGBE_IVAR_OTHER_CAUSES_INDEX    97 /* 0 based index */
1454
1455#define IXGBE_MSIX_VECTOR(_i)   (0 + (_i))
1456
1457#define IXGBE_IVAR_ALLOC_VAL    0x80 /* Interrupt Allocation valid */
1458
1459/* ETYPE Queue Filter/Select Bit Masks */
1460#define IXGBE_MAX_ETQF_FILTERS  8
1461#define IXGBE_ETQF_FCOE         0x08000000 /* bit 27 */
1462#define IXGBE_ETQF_BCN          0x10000000 /* bit 28 */
1463#define IXGBE_ETQF_1588         0x40000000 /* bit 30 */
1464#define IXGBE_ETQF_FILTER_EN    0x80000000 /* bit 31 */
1465#define IXGBE_ETQF_POOL_ENABLE   (1 << 26) /* bit 26 */
1466#define IXGBE_ETQF_POOL_SHIFT           20
1467
1468#define IXGBE_ETQS_RX_QUEUE     0x007F0000 /* bits 22:16 */
1469#define IXGBE_ETQS_RX_QUEUE_SHIFT       16
1470#define IXGBE_ETQS_LLI          0x20000000 /* bit 29 */
1471#define IXGBE_ETQS_QUEUE_EN     0x80000000 /* bit 31 */
1472
1473/*
1474 * ETQF filter list: one static filter per filter consumer. This is
1475 *                   to avoid filter collisions later. Add new filters
1476 *                   here!!
1477 *
1478 * Current filters:
1479 *    EAPOL 802.1x (0x888e): Filter 0
1480 *    FCoE (0x8906):         Filter 2
1481 *    1588 (0x88f7):         Filter 3
1482 *    FIP  (0x8914):         Filter 4
1483 */
1484#define IXGBE_ETQF_FILTER_EAPOL          0
1485#define IXGBE_ETQF_FILTER_FCOE           2
1486#define IXGBE_ETQF_FILTER_1588           3
1487#define IXGBE_ETQF_FILTER_FIP            4
1488/* VLAN Control Bit Masks */
1489#define IXGBE_VLNCTRL_VET       0x0000FFFF  /* bits 0-15 */
1490#define IXGBE_VLNCTRL_CFI       0x10000000  /* bit 28 */
1491#define IXGBE_VLNCTRL_CFIEN     0x20000000  /* bit 29 */
1492#define IXGBE_VLNCTRL_VFE       0x40000000  /* bit 30 */
1493#define IXGBE_VLNCTRL_VME       0x80000000  /* bit 31 */
1494
1495/* VLAN pool filtering masks */
1496#define IXGBE_VLVF_VIEN         0x80000000  /* filter is valid */
1497#define IXGBE_VLVF_ENTRIES      64
1498#define IXGBE_VLVF_VLANID_MASK  0x00000FFF
1499
1500/* Per VF Port VLAN insertion rules */
1501#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
1502#define IXGBE_VMVIR_VLANA_NEVER   0x80000000 /* Never insert VLAN tag */
1503
1504#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.1q protocol */
1505
1506/* STATUS Bit Masks */
1507#define IXGBE_STATUS_LAN_ID         0x0000000C /* LAN ID */
1508#define IXGBE_STATUS_LAN_ID_SHIFT   2          /* LAN ID Shift*/
1509#define IXGBE_STATUS_GIO            0x00080000 /* GIO Master Enable Status */
1510
1511#define IXGBE_STATUS_LAN_ID_0   0x00000000 /* LAN ID 0 */
1512#define IXGBE_STATUS_LAN_ID_1   0x00000004 /* LAN ID 1 */
1513
1514/* ESDP Bit Masks */
1515#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
1516#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
1517#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1518#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
1519#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1520#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1521#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
1522#define IXGBE_ESDP_SDP0_DIR     0x00000100 /* SDP0 IO direction */
1523#define IXGBE_ESDP_SDP4_DIR     0x00000004 /* SDP4 IO direction */
1524#define IXGBE_ESDP_SDP5_DIR     0x00002000 /* SDP5 IO direction */
1525#define IXGBE_ESDP_SDP0_NATIVE  0x00010000 /* SDP0 Native Function */
1526
1527/* LEDCTL Bit Masks */
1528#define IXGBE_LED_IVRT_BASE      0x00000040
1529#define IXGBE_LED_BLINK_BASE     0x00000080
1530#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1531#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1532#define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i))
1533#define IXGBE_LED_IVRT(_i)       IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1534#define IXGBE_LED_BLINK(_i)      IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1535#define IXGBE_LED_MODE_MASK(_i)  IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1536
1537/* LED modes */
1538#define IXGBE_LED_LINK_UP       0x0
1539#define IXGBE_LED_LINK_10G      0x1
1540#define IXGBE_LED_MAC           0x2
1541#define IXGBE_LED_FILTER        0x3
1542#define IXGBE_LED_LINK_ACTIVE   0x4
1543#define IXGBE_LED_LINK_1G       0x5
1544#define IXGBE_LED_ON            0xE
1545#define IXGBE_LED_OFF           0xF
1546
1547/* AUTOC Bit Masks */
1548#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1549#define IXGBE_AUTOC_KX4_SUPP    0x80000000
1550#define IXGBE_AUTOC_KX_SUPP     0x40000000
1551#define IXGBE_AUTOC_PAUSE       0x30000000
1552#define IXGBE_AUTOC_ASM_PAUSE   0x20000000
1553#define IXGBE_AUTOC_SYM_PAUSE   0x10000000
1554#define IXGBE_AUTOC_RF          0x08000000
1555#define IXGBE_AUTOC_PD_TMR      0x06000000
1556#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1557#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1558#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1559#define IXGBE_AUTOC_FECA        0x00040000
1560#define IXGBE_AUTOC_FECR        0x00020000
1561#define IXGBE_AUTOC_KR_SUPP     0x00010000
1562#define IXGBE_AUTOC_AN_RESTART  0x00001000
1563#define IXGBE_AUTOC_FLU         0x00000001
1564#define IXGBE_AUTOC_LMS_SHIFT   13
1565#define IXGBE_AUTOC_LMS_10G_SERIAL      (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1566#define IXGBE_AUTOC_LMS_KX4_KX_KR       (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1567#define IXGBE_AUTOC_LMS_SGMII_1G_100M   (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1568#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1569#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1570#define IXGBE_AUTOC_LMS_MASK            (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1571#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN   (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1572#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN  (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1573#define IXGBE_AUTOC_LMS_1G_AN           (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1574#define IXGBE_AUTOC_LMS_KX4_AN          (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1575#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN    (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1576#define IXGBE_AUTOC_LMS_ATTACH_TYPE     (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1577
1578#define IXGBE_AUTOC_1G_PMA_PMD_MASK    0x00000200
1579#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT   9
1580#define IXGBE_AUTOC_10G_PMA_PMD_MASK   0x00000180
1581#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT  7
1582#define IXGBE_AUTOC_10G_XAUI   (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1583#define IXGBE_AUTOC_10G_KX4    (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1584#define IXGBE_AUTOC_10G_CX4    (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1585#define IXGBE_AUTOC_1G_BX      (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1586#define IXGBE_AUTOC_1G_KX      (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1587#define IXGBE_AUTOC_1G_SFI     (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1588#define IXGBE_AUTOC_1G_KX_BX   (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1589
1590#define IXGBE_AUTOC2_UPPER_MASK  0xFFFF0000
1591#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK  0x00030000
1592#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1593#define IXGBE_AUTOC2_10G_KR  (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1594#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1595#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1596#define IXGBE_AUTOC2_LINK_DISABLE_MASK        0x70000000
1597
1598#define IXGBE_MACC_FLU       0x00000001
1599#define IXGBE_MACC_FSV_10G   0x00030000
1600#define IXGBE_MACC_FS        0x00040000
1601#define IXGBE_MAC_RX2TX_LPBK 0x00000002
1602
1603/* LINKS Bit Masks */
1604#define IXGBE_LINKS_KX_AN_COMP  0x80000000
1605#define IXGBE_LINKS_UP          0x40000000
1606#define IXGBE_LINKS_SPEED       0x20000000
1607#define IXGBE_LINKS_MODE        0x18000000
1608#define IXGBE_LINKS_RX_MODE     0x06000000
1609#define IXGBE_LINKS_TX_MODE     0x01800000
1610#define IXGBE_LINKS_XGXS_EN     0x00400000
1611#define IXGBE_LINKS_SGMII_EN    0x02000000
1612#define IXGBE_LINKS_PCS_1G_EN   0x00200000
1613#define IXGBE_LINKS_1G_AN_EN    0x00100000
1614#define IXGBE_LINKS_KX_AN_IDLE  0x00080000
1615#define IXGBE_LINKS_1G_SYNC     0x00040000
1616#define IXGBE_LINKS_10G_ALIGN   0x00020000
1617#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1618#define IXGBE_LINKS_TL_FAULT    0x00001000
1619#define IXGBE_LINKS_SIGNAL      0x00000F00
1620
1621#define IXGBE_LINKS_SPEED_82599     0x30000000
1622#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1623#define IXGBE_LINKS_SPEED_1G_82599  0x20000000
1624#define IXGBE_LINKS_SPEED_100_82599 0x10000000
1625#define IXGBE_LINK_UP_TIME      90 /* 9.0 Seconds */
1626#define IXGBE_AUTO_NEG_TIME     45 /* 4.5 Seconds */
1627
1628#define IXGBE_LINKS2_AN_SUPPORTED   0x00000040
1629
1630/* PCS1GLSTA Bit Masks */
1631#define IXGBE_PCS1GLSTA_LINK_OK         1
1632#define IXGBE_PCS1GLSTA_SYNK_OK         0x10
1633#define IXGBE_PCS1GLSTA_AN_COMPLETE     0x10000
1634#define IXGBE_PCS1GLSTA_AN_PAGE_RX      0x20000
1635#define IXGBE_PCS1GLSTA_AN_TIMED_OUT    0x40000
1636#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1637#define IXGBE_PCS1GLSTA_AN_ERROR_RWS    0x100000
1638
1639#define IXGBE_PCS1GANA_SYM_PAUSE        0x80
1640#define IXGBE_PCS1GANA_ASM_PAUSE        0x100
1641
1642/* PCS1GLCTL Bit Masks */
1643#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN  0x00040000 /* PCS 1G autoneg to en */
1644#define IXGBE_PCS1GLCTL_FLV_LINK_UP     1
1645#define IXGBE_PCS1GLCTL_FORCE_LINK      0x20
1646#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH  0x40
1647#define IXGBE_PCS1GLCTL_AN_ENABLE       0x10000
1648#define IXGBE_PCS1GLCTL_AN_RESTART      0x20000
1649
1650/* ANLP1 Bit Masks */
1651#define IXGBE_ANLP1_PAUSE               0x0C00
1652#define IXGBE_ANLP1_SYM_PAUSE           0x0400
1653#define IXGBE_ANLP1_ASM_PAUSE           0x0800
1654#define IXGBE_ANLP1_AN_STATE_MASK       0x000f0000
1655
1656/* SW Semaphore Register bitmasks */
1657#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1658#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1659#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1660#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
1661
1662/* SW_FW_SYNC/GSSR definitions */
1663#define IXGBE_GSSR_EEP_SM     0x0001
1664#define IXGBE_GSSR_PHY0_SM    0x0002
1665#define IXGBE_GSSR_PHY1_SM    0x0004
1666#define IXGBE_GSSR_MAC_CSR_SM 0x0008
1667#define IXGBE_GSSR_FLASH_SM   0x0010
1668#define IXGBE_GSSR_SW_MNG_SM  0x0400
1669
1670/* FW Status register bitmask */
1671#define IXGBE_FWSTS_FWRI    0x00000200 /* Firmware Reset Indication */
1672
1673/* EEC Register */
1674#define IXGBE_EEC_SK        0x00000001 /* EEPROM Clock */
1675#define IXGBE_EEC_CS        0x00000002 /* EEPROM Chip Select */
1676#define IXGBE_EEC_DI        0x00000004 /* EEPROM Data In */
1677#define IXGBE_EEC_DO        0x00000008 /* EEPROM Data Out */
1678#define IXGBE_EEC_FWE_MASK  0x00000030 /* FLASH Write Enable */
1679#define IXGBE_EEC_FWE_DIS   0x00000010 /* Disable FLASH writes */
1680#define IXGBE_EEC_FWE_EN    0x00000020 /* Enable FLASH writes */
1681#define IXGBE_EEC_FWE_SHIFT 4
1682#define IXGBE_EEC_REQ       0x00000040 /* EEPROM Access Request */
1683#define IXGBE_EEC_GNT       0x00000080 /* EEPROM Access Grant */
1684#define IXGBE_EEC_PRES      0x00000100 /* EEPROM Present */
1685#define IXGBE_EEC_ARD       0x00000200 /* EEPROM Auto Read Done */
1686#define IXGBE_EEC_FLUP      0x00800000 /* Flash update command */
1687#define IXGBE_EEC_SEC1VAL   0x02000000 /* Sector 1 Valid */
1688#define IXGBE_EEC_FLUDONE   0x04000000 /* Flash update done */
1689/* EEPROM Addressing bits based on type (0-small, 1-large) */
1690#define IXGBE_EEC_ADDR_SIZE 0x00000400
1691#define IXGBE_EEC_SIZE      0x00007800 /* EEPROM Size */
1692#define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */
1693
1694#define IXGBE_EEC_SIZE_SHIFT          11
1695#define IXGBE_EEPROM_WORD_SIZE_SHIFT  6
1696#define IXGBE_EEPROM_OPCODE_BITS      8
1697
1698/* Part Number String Length */
1699#define IXGBE_PBANUM_LENGTH 11
1700
1701/* Checksum and EEPROM pointers */
1702#define IXGBE_PBANUM_PTR_GUARD  0xFAFA
1703#define IXGBE_EEPROM_CHECKSUM   0x3F
1704#define IXGBE_EEPROM_SUM        0xBABA
1705#define IXGBE_PCIE_ANALOG_PTR   0x03
1706#define IXGBE_ATLAS0_CONFIG_PTR 0x04
1707#define IXGBE_PHY_PTR           0x04
1708#define IXGBE_ATLAS1_CONFIG_PTR 0x05
1709#define IXGBE_OPTION_ROM_PTR    0x05
1710#define IXGBE_PCIE_GENERAL_PTR  0x06
1711#define IXGBE_PCIE_CONFIG0_PTR  0x07
1712#define IXGBE_PCIE_CONFIG1_PTR  0x08
1713#define IXGBE_CORE0_PTR         0x09
1714#define IXGBE_CORE1_PTR         0x0A
1715#define IXGBE_MAC0_PTR          0x0B
1716#define IXGBE_MAC1_PTR          0x0C
1717#define IXGBE_CSR0_CONFIG_PTR   0x0D
1718#define IXGBE_CSR1_CONFIG_PTR   0x0E
1719#define IXGBE_FW_PTR            0x0F
1720#define IXGBE_PBANUM0_PTR       0x15
1721#define IXGBE_PBANUM1_PTR       0x16
1722#define IXGBE_FREE_SPACE_PTR    0X3E
1723
1724/* External Thermal Sensor Config */
1725#define IXGBE_ETS_CFG                   0x26
1726#define IXGBE_ETS_LTHRES_DELTA_MASK     0x07C0
1727#define IXGBE_ETS_LTHRES_DELTA_SHIFT    6
1728#define IXGBE_ETS_TYPE_MASK             0x0038
1729#define IXGBE_ETS_TYPE_SHIFT            3
1730#define IXGBE_ETS_TYPE_EMC              0x000
1731#define IXGBE_ETS_TYPE_EMC_SHIFTED      0x000
1732#define IXGBE_ETS_NUM_SENSORS_MASK      0x0007
1733#define IXGBE_ETS_DATA_LOC_MASK         0x3C00
1734#define IXGBE_ETS_DATA_LOC_SHIFT        10
1735#define IXGBE_ETS_DATA_INDEX_MASK       0x0300
1736#define IXGBE_ETS_DATA_INDEX_SHIFT      8
1737#define IXGBE_ETS_DATA_HTHRESH_MASK     0x00FF
1738
1739#define IXGBE_SAN_MAC_ADDR_PTR  0x28
1740#define IXGBE_DEVICE_CAPS       0x2C
1741#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
1742#define IXGBE_PCIE_MSIX_82599_CAPS  0x72
1743#define IXGBE_MAX_MSIX_VECTORS_82599    0x40
1744#define IXGBE_PCIE_MSIX_82598_CAPS  0x62
1745#define IXGBE_MAX_MSIX_VECTORS_82598    0x13
1746
1747/* MSI-X capability fields masks */
1748#define IXGBE_PCIE_MSIX_TBL_SZ_MASK     0x7FF
1749
1750/* Legacy EEPROM word offsets */
1751#define IXGBE_ISCSI_BOOT_CAPS           0x0033
1752#define IXGBE_ISCSI_SETUP_PORT_0        0x0030
1753#define IXGBE_ISCSI_SETUP_PORT_1        0x0034
1754
1755/* EEPROM Commands - SPI */
1756#define IXGBE_EEPROM_MAX_RETRY_SPI      5000 /* Max wait 5ms for RDY signal */
1757#define IXGBE_EEPROM_STATUS_RDY_SPI     0x01
1758#define IXGBE_EEPROM_READ_OPCODE_SPI    0x03  /* EEPROM read opcode */
1759#define IXGBE_EEPROM_WRITE_OPCODE_SPI   0x02  /* EEPROM write opcode */
1760#define IXGBE_EEPROM_A8_OPCODE_SPI      0x08  /* opcode bit-3 = addr bit-8 */
1761#define IXGBE_EEPROM_WREN_OPCODE_SPI    0x06  /* EEPROM set Write Ena latch */
1762/* EEPROM reset Write Enable latch */
1763#define IXGBE_EEPROM_WRDI_OPCODE_SPI    0x04
1764#define IXGBE_EEPROM_RDSR_OPCODE_SPI    0x05  /* EEPROM read Status reg */
1765#define IXGBE_EEPROM_WRSR_OPCODE_SPI    0x01  /* EEPROM write Status reg */
1766#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20  /* EEPROM ERASE 4KB */
1767#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI  0xD8  /* EEPROM ERASE 64KB */
1768#define IXGBE_EEPROM_ERASE256_OPCODE_SPI  0xDB  /* EEPROM ERASE 256B */
1769
1770/* EEPROM Read Register */
1771#define IXGBE_EEPROM_RW_REG_DATA   16 /* data offset in EEPROM read reg */
1772#define IXGBE_EEPROM_RW_REG_DONE   2  /* Offset to READ done bit */
1773#define IXGBE_EEPROM_RW_REG_START  1  /* First bit to start operation */
1774#define IXGBE_EEPROM_RW_ADDR_SHIFT 2  /* Shift to the address bits */
1775#define IXGBE_NVM_POLL_WRITE       1  /* Flag for polling for write complete */
1776#define IXGBE_NVM_POLL_READ        0  /* Flag for polling for read complete */
1777
1778#define IXGBE_EEPROM_PAGE_SIZE_MAX       128
1779#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */
1780#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */
1781
1782#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1783#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1784#endif
1785
1786#ifndef IXGBE_EERD_EEWR_ATTEMPTS
1787/* Number of 5 microseconds we wait for EERD read and
1788 * EERW write to complete */
1789#define IXGBE_EERD_EEWR_ATTEMPTS 100000
1790#endif
1791
1792#ifndef IXGBE_FLUDONE_ATTEMPTS
1793/* # attempts we wait for flush update to complete */
1794#define IXGBE_FLUDONE_ATTEMPTS 20000
1795#endif
1796
1797#define IXGBE_PCIE_CTRL2                 0x5   /* PCIe Control 2 Offset */
1798#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE    0x8   /* Dummy Function Enable */
1799#define IXGBE_PCIE_CTRL2_LAN_DISABLE     0x2   /* LAN PCI Disable */
1800#define IXGBE_PCIE_CTRL2_DISABLE_SELECT  0x1   /* LAN Disable Select */
1801
1802#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET  0x0
1803#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET  0x3
1804#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP  0x1
1805#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS  0x2
1806#define IXGBE_FW_LESM_PARAMETERS_PTR     0x2
1807#define IXGBE_FW_LESM_STATE_1            0x1
1808#define IXGBE_FW_LESM_STATE_ENABLED      0x8000 /* LESM Enable bit */
1809#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR   0x4
1810#define IXGBE_FW_PATCH_VERSION_4         0x7
1811#define IXGBE_FCOE_IBA_CAPS_BLK_PTR         0x33 /* iSCSI/FCOE block */
1812#define IXGBE_FCOE_IBA_CAPS_FCOE            0x20 /* FCOE flags */
1813#define IXGBE_ISCSI_FCOE_BLK_PTR            0x17 /* iSCSI/FCOE block */
1814#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET       0x0  /* FCOE flags */
1815#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE       0x1  /* FCOE flags enable bit */
1816#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR      0x27 /* Alt. SAN MAC block */
1817#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET  0x0 /* Alt. SAN MAC capability */
1818#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
1819#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
1820#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET  0x7 /* Alt. WWNN prefix offset */
1821#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET  0x8 /* Alt. WWPN prefix offset */
1822#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC  0x0 /* Alt. SAN MAC exists */
1823#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN  0x1 /* Alt. WWN base exists */
1824
1825#define IXGBE_DEVICE_CAPS_WOL_PORT0_1  0x4 /* WoL supported on ports 0 & 1 */
1826#define IXGBE_DEVICE_CAPS_WOL_PORT0    0x8 /* WoL supported on port 0 */
1827#define IXGBE_DEVICE_CAPS_WOL_MASK     0xC /* Mask for WoL capabilities */
1828
1829/* PCI Bus Info */
1830#define IXGBE_PCI_DEVICE_STATUS   0xAA
1831#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING   0x0020
1832#define IXGBE_PCI_LINK_STATUS     0xB2
1833#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
1834#define IXGBE_PCI_LINK_WIDTH      0x3F0
1835#define IXGBE_PCI_LINK_WIDTH_1    0x10
1836#define IXGBE_PCI_LINK_WIDTH_2    0x20
1837#define IXGBE_PCI_LINK_WIDTH_4    0x40
1838#define IXGBE_PCI_LINK_WIDTH_8    0x80
1839#define IXGBE_PCI_LINK_SPEED      0xF
1840#define IXGBE_PCI_LINK_SPEED_2500 0x1
1841#define IXGBE_PCI_LINK_SPEED_5000 0x2
1842#define IXGBE_PCI_LINK_SPEED_8000 0x3
1843#define IXGBE_PCI_HEADER_TYPE_REGISTER  0x0E
1844#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
1845#define IXGBE_PCI_DEVICE_CONTROL2_16ms  0x0005
1846
1847/* Number of 100 microseconds we wait for PCI Express master disable */
1848#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
1849
1850/* RAH */
1851#define IXGBE_RAH_VIND_MASK     0x003C0000
1852#define IXGBE_RAH_VIND_SHIFT    18
1853#define IXGBE_RAH_AV            0x80000000
1854#define IXGBE_CLEAR_VMDQ_ALL    0xFFFFFFFF
1855
1856/* Header split receive */
1857#define IXGBE_RFCTL_ISCSI_DIS       0x00000001
1858#define IXGBE_RFCTL_ISCSI_DWC_MASK  0x0000003E
1859#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
1860#define IXGBE_RFCTL_NFSW_DIS        0x00000040
1861#define IXGBE_RFCTL_NFSR_DIS        0x00000080
1862#define IXGBE_RFCTL_NFS_VER_MASK    0x00000300
1863#define IXGBE_RFCTL_NFS_VER_SHIFT   8
1864#define IXGBE_RFCTL_NFS_VER_2       0
1865#define IXGBE_RFCTL_NFS_VER_3       1
1866#define IXGBE_RFCTL_NFS_VER_4       2
1867#define IXGBE_RFCTL_IPV6_DIS        0x00000400
1868#define IXGBE_RFCTL_IPV6_XSUM_DIS   0x00000800
1869#define IXGBE_RFCTL_IPFRSP_DIS      0x00004000
1870#define IXGBE_RFCTL_IPV6_EX_DIS     0x00010000
1871#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1872
1873/* Transmit Config masks */
1874#define IXGBE_TXDCTL_ENABLE     0x02000000 /* Enable specific Tx Queue */
1875#define IXGBE_TXDCTL_SWFLSH     0x04000000 /* Tx Desc. write-back flushing */
1876#define IXGBE_TXDCTL_WTHRESH_SHIFT      16 /* shift to WTHRESH bits */
1877/* Enable short packet padding to 64 bytes */
1878#define IXGBE_TX_PAD_ENABLE     0x00000400
1879#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004  /* Allow jumbo frames */
1880/* This allows for 16K packets + 4k for vlan */
1881#define IXGBE_MAX_FRAME_SZ      0x40040000
1882
1883#define IXGBE_TDWBAL_HEAD_WB_ENABLE   0x1      /* Tx head write-back enable */
1884#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2      /* Tx seq# write-back enable */
1885
1886/* Receive Config masks */
1887#define IXGBE_RXCTRL_RXEN       0x00000001  /* Enable Receiver */
1888#define IXGBE_RXCTRL_DMBYPS     0x00000002  /* Descriptor Monitor Bypass */
1889#define IXGBE_RXDCTL_ENABLE     0x02000000  /* Enable specific Rx Queue */
1890#define IXGBE_RXDCTL_SWFLSH     0x04000000  /* Rx Desc. write-back flushing */
1891#define IXGBE_RXDCTL_RLPMLMASK  0x00003FFF  /* Only supported on the X540 */
1892#define IXGBE_RXDCTL_RLPML_EN   0x00008000
1893#define IXGBE_RXDCTL_VME        0x40000000  /* VLAN mode enable */
1894
1895#define IXGBE_TSAUXC_EN_CLK   0x00000004
1896#define IXGBE_TSAUXC_SYNCLK   0x00000008
1897#define IXGBE_TSAUXC_SDP0_INT 0x00000040
1898
1899#define IXGBE_TSYNCTXCTL_VALID          0x00000001 /* Tx timestamp valid */
1900#define IXGBE_TSYNCTXCTL_ENABLED        0x00000010 /* Tx timestamping enabled */
1901
1902#define IXGBE_TSYNCRXCTL_VALID          0x00000001 /* Rx timestamp valid */
1903#define IXGBE_TSYNCRXCTL_TYPE_MASK      0x0000000E /* Rx type mask */
1904#define IXGBE_TSYNCRXCTL_TYPE_L2_V2     0x00
1905#define IXGBE_TSYNCRXCTL_TYPE_L4_V1     0x02
1906#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2  0x04
1907#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2  0x0A
1908#define IXGBE_TSYNCRXCTL_ENABLED        0x00000010 /* Rx Timestamping enabled */
1909
1910#define IXGBE_RXMTRL_V1_CTRLT_MASK      0x000000FF
1911#define IXGBE_RXMTRL_V1_SYNC_MSG        0x00
1912#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG   0x01
1913#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG    0x02
1914#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG  0x03
1915#define IXGBE_RXMTRL_V1_MGMT_MSG        0x04
1916
1917#define IXGBE_RXMTRL_V2_MSGID_MASK              0x0000FF00
1918#define IXGBE_RXMTRL_V2_SYNC_MSG                0x0000
1919#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG           0x0100
1920#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG          0x0200
1921#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG         0x0300
1922#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG            0x0800
1923#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG          0x0900
1924#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG     0x0A00
1925#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG            0x0B00
1926#define IXGBE_RXMTRL_V2_SIGNALING_MSG           0x0C00
1927#define IXGBE_RXMTRL_V2_MGMT_MSG                0x0D00
1928
1929#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
1930#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
1931#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
1932#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
1933#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
1934#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
1935/* Receive Priority Flow Control Enable */
1936#define IXGBE_FCTRL_RPFCE 0x00004000
1937#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
1938#define IXGBE_MFLCN_PMCF        0x00000001 /* Pass MAC Control Frames */
1939#define IXGBE_MFLCN_DPF         0x00000002 /* Discard Pause Frame */
1940#define IXGBE_MFLCN_RPFCE       0x00000004 /* Receive Priority FC Enable */
1941#define IXGBE_MFLCN_RFCE        0x00000008 /* Receive FC Enable */
1942#define IXGBE_MFLCN_RPFCE_MASK  0x00000FF4 /* Receive FC Mask */
1943
1944#define IXGBE_MFLCN_RPFCE_SHIFT          4
1945
1946/* Multiple Receive Queue Control */
1947#define IXGBE_MRQC_RSSEN                 0x00000001  /* RSS Enable */
1948#define IXGBE_MRQC_MRQE_MASK                    0xF /* Bits 3:0 */
1949#define IXGBE_MRQC_RT8TCEN               0x00000002 /* 8 TC no RSS */
1950#define IXGBE_MRQC_RT4TCEN               0x00000003 /* 4 TC no RSS */
1951#define IXGBE_MRQC_RTRSS8TCEN            0x00000004 /* 8 TC w/ RSS */
1952#define IXGBE_MRQC_RTRSS4TCEN            0x00000005 /* 4 TC w/ RSS */
1953#define IXGBE_MRQC_VMDQEN                0x00000008 /* VMDq2 64 pools no RSS */
1954#define IXGBE_MRQC_VMDQRSS32EN           0x0000000A /* VMDq2 32 pools w/ RSS */
1955#define IXGBE_MRQC_VMDQRSS64EN           0x0000000B /* VMDq2 64 pools w/ RSS */
1956#define IXGBE_MRQC_VMDQRT8TCEN           0x0000000C /* VMDq2/RT 16 pool 8 TC */
1957#define IXGBE_MRQC_VMDQRT4TCEN           0x0000000D /* VMDq2/RT 32 pool 4 TC */
1958#define IXGBE_MRQC_RSS_FIELD_MASK        0xFFFF0000
1959#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP    0x00010000
1960#define IXGBE_MRQC_RSS_FIELD_IPV4        0x00020000
1961#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
1962#define IXGBE_MRQC_RSS_FIELD_IPV6_EX     0x00080000
1963#define IXGBE_MRQC_RSS_FIELD_IPV6        0x00100000
1964#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP    0x00200000
1965#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP    0x00400000
1966#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP    0x00800000
1967#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
1968#define IXGBE_MRQC_L3L4TXSWEN            0x00008000
1969
1970#define IXGBE_FWSM_TS_ENABLED   0x1
1971
1972/* Queue Drop Enable */
1973#define IXGBE_QDE_ENABLE     0x00000001
1974#define IXGBE_QDE_IDX_MASK   0x00007F00
1975#define IXGBE_QDE_IDX_SHIFT           8
1976
1977#define IXGBE_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
1978#define IXGBE_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
1979#define IXGBE_TXD_CMD_EOP    0x01000000 /* End of Packet */
1980#define IXGBE_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
1981#define IXGBE_TXD_CMD_IC     0x04000000 /* Insert Checksum */
1982#define IXGBE_TXD_CMD_RS     0x08000000 /* Report Status */
1983#define IXGBE_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
1984#define IXGBE_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
1985#define IXGBE_TXD_STAT_DD    0x00000001 /* Descriptor Done */
1986
1987#define IXGBE_RXDADV_IPSEC_STATUS_SECP                  0x00020000
1988#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL       0x08000000
1989#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH         0x10000000
1990#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED            0x18000000
1991#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK               0x18000000
1992/* Multiple Transmit Queue Command Register */
1993#define IXGBE_MTQC_RT_ENA       0x1 /* DCB Enable */
1994#define IXGBE_MTQC_VT_ENA       0x2 /* VMDQ2 Enable */
1995#define IXGBE_MTQC_64Q_1PB      0x0 /* 64 queues 1 pack buffer */
1996#define IXGBE_MTQC_32VF         0x8 /* 4 TX Queues per pool w/32VF's */
1997#define IXGBE_MTQC_64VF         0x4 /* 2 TX Queues per pool w/64VF's */
1998#define IXGBE_MTQC_8TC_8TQ      0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
1999#define IXGBE_MTQC_4TC_4TQ      0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */
2000

2001/* Receive Descriptor bit definitions */
2002#define IXGBE_RXD_STAT_DD       0x01    /* Descriptor Done */
2003#define IXGBE_RXD_STAT_EOP      0x02    /* End of Packet */
2004#define IXGBE_RXD_STAT_FLM      0x04    /* FDir Match */
2005#define IXGBE_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
2006#define IXGBE_RXDADV_NEXTP_MASK   0x000FFFF0 /* Next Descriptor Index */
2007#define IXGBE_RXDADV_NEXTP_SHIFT  0x00000004
2008#define IXGBE_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
2009#define IXGBE_RXD_STAT_L4CS     0x20    /* L4 xsum calculated */
2010#define IXGBE_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
2011#define IXGBE_RXD_STAT_PIF      0x80    /* passed in-exact filter */
2012#define IXGBE_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */
2013#define IXGBE_RXD_STAT_VEXT     0x200   /* 1st VLAN found */
2014#define IXGBE_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
2015#define IXGBE_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
2016#define IXGBE_RXD_STAT_LLINT    0x800   /* Pkt caused Low Latency Interrupt */
2017#define IXGBE_RXD_STAT_TS       0x10000 /* Time Stamp */
2018#define IXGBE_RXD_STAT_SECP     0x20000 /* Security Processing */
2019#define IXGBE_RXD_STAT_LB       0x40000 /* Loopback Status */
2020#define IXGBE_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
2021#define IXGBE_RXD_ERR_CE        0x01    /* CRC Error */
2022#define IXGBE_RXD_ERR_LE        0x02    /* Length Error */
2023#define IXGBE_RXD_ERR_PE        0x08    /* Packet Error */
2024#define IXGBE_RXD_ERR_OSE       0x10    /* Oversize Error */
2025#define IXGBE_RXD_ERR_USE       0x20    /* Undersize Error */
2026#define IXGBE_RXD_ERR_TCPE      0x40    /* TCP/UDP Checksum Error */
2027#define IXGBE_RXD_ERR_IPE       0x80    /* IP Checksum Error */
2028#define IXGBE_RXDADV_ERR_MASK           0xfff00000 /* RDESC.ERRORS mask */
2029#define IXGBE_RXDADV_ERR_SHIFT          20         /* RDESC.ERRORS shift */
2030#define IXGBE_RXDADV_ERR_FCEOFE         0x80000000 /* FCoEFe/IPE */
2031#define IXGBE_RXDADV_ERR_FCERR          0x00700000 /* FCERR/FDIRERR */
2032#define IXGBE_RXDADV_ERR_FDIR_LEN       0x00100000 /* FDIR Length error */
2033#define IXGBE_RXDADV_ERR_FDIR_DROP      0x00200000 /* FDIR Drop error */
2034#define IXGBE_RXDADV_ERR_FDIR_COLL      0x00400000 /* FDIR Collision error */
2035#define IXGBE_RXDADV_ERR_HBO    0x00800000 /*Header Buffer Overflow */
2036#define IXGBE_RXDADV_ERR_CE     0x01000000 /* CRC Error */
2037#define IXGBE_RXDADV_ERR_LE     0x02000000 /* Length Error */
2038#define IXGBE_RXDADV_ERR_PE     0x08000000 /* Packet Error */
2039#define IXGBE_RXDADV_ERR_OSE    0x10000000 /* Oversize Error */
2040#define IXGBE_RXDADV_ERR_USE    0x20000000 /* Undersize Error */
2041#define IXGBE_RXDADV_ERR_TCPE   0x40000000 /* TCP/UDP Checksum Error */
2042#define IXGBE_RXDADV_ERR_IPE    0x80000000 /* IP Checksum Error */
2043#define IXGBE_RXD_VLAN_ID_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */
2044#define IXGBE_RXD_PRI_MASK      0xE000  /* Priority is in upper 3 bits */
2045#define IXGBE_RXD_PRI_SHIFT     13
2046#define IXGBE_RXD_CFI_MASK      0x1000  /* CFI is bit 12 */
2047#define IXGBE_RXD_CFI_SHIFT     12
2048
2049#define IXGBE_RXDADV_STAT_DD            IXGBE_RXD_STAT_DD  /* Done */
2050#define IXGBE_RXDADV_STAT_EOP           IXGBE_RXD_STAT_EOP /* End of Packet */
2051#define IXGBE_RXDADV_STAT_FLM           IXGBE_RXD_STAT_FLM /* FDir Match */
2052#define IXGBE_RXDADV_STAT_VP            IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
2053#define IXGBE_RXDADV_STAT_MASK          0x000fffff /* Stat/NEXTP: bit 0-19 */
2054#define IXGBE_RXDADV_STAT_FCEOFS        0x00000040 /* FCoE EOF/SOF Stat */
2055#define IXGBE_RXDADV_STAT_FCSTAT        0x00000030 /* FCoE Pkt Stat */
2056#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
2057#define IXGBE_RXDADV_STAT_FCSTAT_NODDP  0x00000010 /* 01: Ctxt w/o DDP */
2058#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
2059#define IXGBE_RXDADV_STAT_FCSTAT_DDP    0x00000030 /* 11: Ctxt w/ DDP */
2060#define IXGBE_RXDADV_STAT_TS            0x00010000 /* IEEE 1588 Time Stamp */
2061
2062/* PSRTYPE bit definitions */
2063#define IXGBE_PSRTYPE_TCPHDR    0x00000010
2064#define IXGBE_PSRTYPE_UDPHDR    0x00000020
2065#define IXGBE_PSRTYPE_IPV4HDR   0x00000100
2066#define IXGBE_PSRTYPE_IPV6HDR   0x00000200
2067#define IXGBE_PSRTYPE_L2HDR     0x00001000
2068
2069/* SRRCTL bit definitions */
2070#define IXGBE_SRRCTL_BSIZEPKT_SHIFT     10     /* so many KBs */
2071#define IXGBE_SRRCTL_RDMTS_SHIFT        22
2072#define IXGBE_SRRCTL_RDMTS_MASK         0x01C00000
2073#define IXGBE_SRRCTL_DROP_EN            0x10000000
2074#define IXGBE_SRRCTL_BSIZEPKT_MASK      0x0000007F
2075#define IXGBE_SRRCTL_BSIZEHDR_MASK      0x00003F00
2076#define IXGBE_SRRCTL_DESCTYPE_LEGACY    0x00000000
2077#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2078#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT  0x04000000
2079#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2080#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2081#define IXGBE_SRRCTL_DESCTYPE_MASK      0x0E000000
2082
2083#define IXGBE_RXDPS_HDRSTAT_HDRSP       0x00008000
2084#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2085
2086#define IXGBE_RXDADV_RSSTYPE_MASK       0x0000000F
2087#define IXGBE_RXDADV_PKTTYPE_MASK       0x0000FFF0
2088#define IXGBE_RXDADV_PKTTYPE_MASK_EX    0x0001FFF0
2089#define IXGBE_RXDADV_HDRBUFLEN_MASK     0x00007FE0
2090#define IXGBE_RXDADV_RSCCNT_MASK        0x001E0000
2091#define IXGBE_RXDADV_RSCCNT_SHIFT       17
2092#define IXGBE_RXDADV_HDRBUFLEN_SHIFT    5
2093#define IXGBE_RXDADV_SPLITHEADER_EN     0x00001000
2094#define IXGBE_RXDADV_SPH                0x8000
2095
2096/* RSS Hash results */
2097#define IXGBE_RXDADV_RSSTYPE_NONE       0x00000000
2098#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP   0x00000001
2099#define IXGBE_RXDADV_RSSTYPE_IPV4       0x00000002
2100#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP   0x00000003
2101#define IXGBE_RXDADV_RSSTYPE_IPV6_EX    0x00000004
2102#define IXGBE_RXDADV_RSSTYPE_IPV6       0x00000005
2103#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2104#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP   0x00000007
2105#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP   0x00000008
2106#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2107
2108/* RSS Packet Types as indicated in the receive descriptor. */
2109#define IXGBE_RXDADV_PKTTYPE_NONE       0x00000000
2110#define IXGBE_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPv4 hdr present */
2111#define IXGBE_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPv4 hdr + extensions */
2112#define IXGBE_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPv6 hdr present */
2113#define IXGBE_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPv6 hdr + extensions */
2114#define IXGBE_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */
2115#define IXGBE_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */
2116#define IXGBE_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */
2117#define IXGBE_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present */
2118#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 /* IPSec ESP */
2119#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 /* IPSec AH */
2120#define IXGBE_RXDADV_PKTTYPE_LINKSEC    0x00004000 /* LinkSec Encap */
2121#define IXGBE_RXDADV_PKTTYPE_ETQF       0x00008000 /* PKTTYPE is ETQF index */
2122#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK  0x00000070 /* ETQF has 8 indices */
2123#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4          /* Right-shift 4 bits */
2124
2125/* Security Processing bit Indication */
2126#define IXGBE_RXDADV_LNKSEC_STATUS_SECP         0x00020000
2127#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
2128#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
2129#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
2130#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
2131
2132/* Masks to determine if packets should be dropped due to frame errors */
2133#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2134                                      IXGBE_RXD_ERR_CE | \
2135                                      IXGBE_RXD_ERR_LE | \
2136                                      IXGBE_RXD_ERR_PE | \
2137                                      IXGBE_RXD_ERR_OSE | \
2138                                      IXGBE_RXD_ERR_USE)
2139
2140#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2141                                      IXGBE_RXDADV_ERR_CE | \
2142                                      IXGBE_RXDADV_ERR_LE | \
2143                                      IXGBE_RXDADV_ERR_PE | \
2144                                      IXGBE_RXDADV_ERR_OSE | \
2145                                      IXGBE_RXDADV_ERR_USE)
2146
2147/* Multicast bit mask */
2148#define IXGBE_MCSTCTRL_MFE      0x4
2149
2150/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2151#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE  8
2152#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE  8
2153#define IXGBE_REQ_TX_BUFFER_GRANULARITY   1024
2154
2155/* Vlan-specific macros */
2156#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK  0x0FFF /* VLAN ID in lower 12 bits */
2157#define IXGBE_RX_DESC_SPECIAL_PRI_MASK   0xE000 /* Priority in upper 3 bits */
2158#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT  0x000D /* Priority in upper 3 of 16 */
2159#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT  IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2160
2161/* SR-IOV specific macros */
2162#define IXGBE_MBVFICR_INDEX(vf_number)   (vf_number >> 4)
2163#define IXGBE_MBVFICR(_i)               (0x00710 + ((_i) * 4))
2164#define IXGBE_VFLRE(_i)         ((((_i) & 1) ? 0x001C0 : 0x00600))
2165#define IXGBE_VFLREC(_i)                (0x00700 + ((_i) * 4))
2166
2167enum ixgbe_fdir_pballoc_type {
2168        IXGBE_FDIR_PBALLOC_NONE = 0,
2169        IXGBE_FDIR_PBALLOC_64K  = 1,
2170        IXGBE_FDIR_PBALLOC_128K = 2,
2171        IXGBE_FDIR_PBALLOC_256K = 3,
2172};
2173#define IXGBE_FDIR_PBALLOC_SIZE_SHIFT           16
2174
2175/* Flow Director register values */
2176#define IXGBE_FDIRCTRL_PBALLOC_64K              0x00000001
2177#define IXGBE_FDIRCTRL_PBALLOC_128K             0x00000002
2178#define IXGBE_FDIRCTRL_PBALLOC_256K             0x00000003
2179#define IXGBE_FDIRCTRL_INIT_DONE                0x00000008
2180#define IXGBE_FDIRCTRL_PERFECT_MATCH            0x00000010
2181#define IXGBE_FDIRCTRL_REPORT_STATUS            0x00000020
2182#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS     0x00000080
2183#define IXGBE_FDIRCTRL_DROP_Q_SHIFT             8
2184#define IXGBE_FDIRCTRL_FLEX_SHIFT               16
2185#define IXGBE_FDIRCTRL_SEARCHLIM                0x00800000
2186#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT         24
2187#define IXGBE_FDIRCTRL_FULL_THRESH_MASK         0xF0000000
2188#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT        28
2189
2190#define IXGBE_FDIRTCPM_DPORTM_SHIFT             16
2191#define IXGBE_FDIRUDPM_DPORTM_SHIFT             16
2192#define IXGBE_FDIRIP6M_DIPM_SHIFT               16
2193#define IXGBE_FDIRM_VLANID                      0x00000001
2194#define IXGBE_FDIRM_VLANP                       0x00000002
2195#define IXGBE_FDIRM_POOL                        0x00000004
2196#define IXGBE_FDIRM_L4P                         0x00000008
2197#define IXGBE_FDIRM_FLEX                        0x00000010
2198#define IXGBE_FDIRM_DIPv6                       0x00000020
2199
2200#define IXGBE_FDIRFREE_FREE_MASK                0xFFFF
2201#define IXGBE_FDIRFREE_FREE_SHIFT               0
2202#define IXGBE_FDIRFREE_COLL_MASK                0x7FFF0000
2203#define IXGBE_FDIRFREE_COLL_SHIFT               16
2204#define IXGBE_FDIRLEN_MAXLEN_MASK               0x3F
2205#define IXGBE_FDIRLEN_MAXLEN_SHIFT              0
2206#define IXGBE_FDIRLEN_MAXHASH_MASK              0x7FFF0000
2207#define IXGBE_FDIRLEN_MAXHASH_SHIFT             16
2208#define IXGBE_FDIRUSTAT_ADD_MASK                0xFFFF
2209#define IXGBE_FDIRUSTAT_ADD_SHIFT               0
2210#define IXGBE_FDIRUSTAT_REMOVE_MASK             0xFFFF0000
2211#define IXGBE_FDIRUSTAT_REMOVE_SHIFT            16
2212#define IXGBE_FDIRFSTAT_FADD_MASK               0x00FF
2213#define IXGBE_FDIRFSTAT_FADD_SHIFT              0
2214#define IXGBE_FDIRFSTAT_FREMOVE_MASK            0xFF00
2215#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT           8
2216#define IXGBE_FDIRPORT_DESTINATION_SHIFT        16
2217#define IXGBE_FDIRVLAN_FLEX_SHIFT               16
2218#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT       15
2219#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT       16
2220
2221#define IXGBE_FDIRCMD_CMD_MASK                  0x00000003
2222#define IXGBE_FDIRCMD_CMD_ADD_FLOW              0x00000001
2223#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW           0x00000002
2224#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT        0x00000003
2225#define IXGBE_FDIRCMD_FILTER_VALID              0x00000004
2226#define IXGBE_FDIRCMD_FILTER_UPDATE             0x00000008
2227#define IXGBE_FDIRCMD_IPv6DMATCH                0x00000010
2228#define IXGBE_FDIRCMD_L4TYPE_UDP                0x00000020
2229#define IXGBE_FDIRCMD_L4TYPE_TCP                0x00000040
2230#define IXGBE_FDIRCMD_L4TYPE_SCTP               0x00000060
2231#define IXGBE_FDIRCMD_IPV6                      0x00000080
2232#define IXGBE_FDIRCMD_CLEARHT                   0x00000100
2233#define IXGBE_FDIRCMD_DROP                      0x00000200
2234#define IXGBE_FDIRCMD_INT                       0x00000400
2235#define IXGBE_FDIRCMD_LAST                      0x00000800
2236#define IXGBE_FDIRCMD_COLLISION                 0x00001000
2237#define IXGBE_FDIRCMD_QUEUE_EN                  0x00008000
2238#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT           5
2239#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT            16
2240#define IXGBE_FDIRCMD_VT_POOL_SHIFT             24
2241#define IXGBE_FDIR_INIT_DONE_POLL               10
2242#define IXGBE_FDIRCMD_CMD_POLL                  10
2243
2244#define IXGBE_FDIR_DROP_QUEUE                   127
2245
2246/* Manageablility Host Interface defines */
2247#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH       1792 /* Num of bytes in range */
2248#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH      448 /* Num of dwords in range */
2249#define IXGBE_HI_COMMAND_TIMEOUT             500 /* Process HI command limit */
2250
2251/* CEM Support */
2252#define FW_CEM_HDR_LEN                0x4
2253#define FW_CEM_CMD_DRIVER_INFO        0xDD
2254#define FW_CEM_CMD_DRIVER_INFO_LEN    0x5
2255#define FW_CEM_CMD_RESERVED           0x0
2256#define FW_CEM_UNUSED_VER             0x0
2257#define FW_CEM_MAX_RETRIES            3
2258#define FW_CEM_RESP_STATUS_SUCCESS    0x1
2259
2260/* Host Interface Command Structures */
2261struct ixgbe_hic_hdr {
2262        u8 cmd;
2263        u8 buf_len;
2264        union {
2265                u8 cmd_resv;
2266                u8 ret_status;
2267        } cmd_or_resp;
2268        u8 checksum;
2269};
2270
2271struct ixgbe_hic_drv_info {
2272        struct ixgbe_hic_hdr hdr;
2273        u8 port_num;
2274        u8 ver_sub;
2275        u8 ver_build;
2276        u8 ver_min;
2277        u8 ver_maj;
2278        u8 pad; /* end spacing to ensure length is mult. of dword */
2279        u16 pad2; /* end spacing to ensure length is mult. of dword2 */
2280};
2281
2282/* Transmit Descriptor - Advanced */
2283union ixgbe_adv_tx_desc {
2284        struct {
2285                __le64 buffer_addr;      /* Address of descriptor's data buf */
2286                __le32 cmd_type_len;
2287                __le32 olinfo_status;
2288        } read;
2289        struct {
2290                __le64 rsvd;       /* Reserved */
2291                __le32 nxtseq_seed;
2292                __le32 status;
2293        } wb;
2294};
2295
2296/* Receive Descriptor - Advanced */
2297union ixgbe_adv_rx_desc {
2298        struct {
2299                __le64 pkt_addr; /* Packet buffer address */
2300                __le64 hdr_addr; /* Header buffer address */
2301        } read;
2302        struct {
2303                struct {
2304                        union {
2305                                __le32 data;
2306                                struct {
2307                                        __le16 pkt_info; /* RSS, Pkt type */
2308                                        __le16 hdr_info; /* Splithdr, hdrlen */
2309                                } hs_rss;
2310                        } lo_dword;
2311                        union {
2312                                __le32 rss; /* RSS Hash */
2313                                struct {
2314                                        __le16 ip_id; /* IP id */
2315                                        __le16 csum; /* Packet Checksum */
2316                                } csum_ip;
2317                        } hi_dword;
2318                } lower;
2319                struct {
2320                        __le32 status_error; /* ext status/error */
2321                        __le16 length; /* Packet length */
2322                        __le16 vlan; /* VLAN tag */
2323                } upper;
2324        } wb;  /* writeback */
2325};
2326
2327/* Context descriptors */
2328struct ixgbe_adv_tx_context_desc {
2329        __le32 vlan_macip_lens;
2330        __le32 seqnum_seed;
2331        __le32 type_tucmd_mlhl;
2332        __le32 mss_l4len_idx;
2333};
2334
2335/* Adv Transmit Descriptor Config Masks */
2336#define IXGBE_ADVTXD_DTALEN_MASK      0x0000FFFF /* Data buf length(bytes) */
2337#define IXGBE_ADVTXD_MAC_LINKSEC      0x00040000 /* Insert LinkSec */
2338#define IXGBE_ADVTXD_MAC_TSTAMP       0x00080000 /* IEEE 1588 Time Stamp */
2339#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK   0x000003FF /* IPSec SA index */
2340#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK    0x000001FF /* IPSec ESP length */
2341#define IXGBE_ADVTXD_DTYP_MASK  0x00F00000 /* DTYP mask */
2342#define IXGBE_ADVTXD_DTYP_CTXT  0x00200000 /* Advanced Context Desc */
2343#define IXGBE_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */
2344#define IXGBE_ADVTXD_DCMD_EOP   IXGBE_TXD_CMD_EOP  /* End of Packet */
2345#define IXGBE_ADVTXD_DCMD_IFCS  IXGBE_TXD_CMD_IFCS /* Insert FCS */
2346#define IXGBE_ADVTXD_DCMD_RS    IXGBE_TXD_CMD_RS   /* Report Status */
2347#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000    /* DDP hdr type or iSCSI */
2348#define IXGBE_ADVTXD_DCMD_DEXT  IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
2349#define IXGBE_ADVTXD_DCMD_VLE   IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */
2350#define IXGBE_ADVTXD_DCMD_TSE   0x80000000 /* TCP Seg enable */
2351#define IXGBE_ADVTXD_STAT_DD    IXGBE_TXD_STAT_DD  /* Descriptor Done */
2352#define IXGBE_ADVTXD_STAT_SN_CRC      0x00000002 /* NXTSEQ/SEED pres in WB */
2353#define IXGBE_ADVTXD_STAT_RSV   0x0000000C /* STA Reserved */
2354#define IXGBE_ADVTXD_IDX_SHIFT  4 /* Adv desc Index shift */
2355#define IXGBE_ADVTXD_CC         0x00000080 /* Check Context */
2356#define IXGBE_ADVTXD_POPTS_SHIFT      8  /* Adv desc POPTS shift */
2357#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
2358                                 IXGBE_ADVTXD_POPTS_SHIFT)
2359#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
2360                                 IXGBE_ADVTXD_POPTS_SHIFT)
2361#define IXGBE_ADVTXD_POPTS_ISCO_1ST  0x00000000 /* 1st TSO of iSCSI PDU */
2362#define IXGBE_ADVTXD_POPTS_ISCO_MDL  0x00000800 /* Middle TSO of iSCSI PDU */
2363#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
2364#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
2365#define IXGBE_ADVTXD_POPTS_RSV       0x00002000 /* POPTS Reserved */
2366#define IXGBE_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
2367#define IXGBE_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
2368#define IXGBE_ADVTXD_VLAN_SHIFT      16  /* Adv ctxt vlan tag shift */
2369#define IXGBE_ADVTXD_TUCMD_IPV4      0x00000400  /* IP Packet Type: 1=IPv4 */
2370#define IXGBE_ADVTXD_TUCMD_IPV6      0x00000000  /* IP Packet Type: 0=IPv6 */
2371#define IXGBE_ADVTXD_TUCMD_L4T_UDP   0x00000000  /* L4 Packet TYPE of UDP */
2372#define IXGBE_ADVTXD_TUCMD_L4T_TCP   0x00000800  /* L4 Packet TYPE of TCP */
2373#define IXGBE_ADVTXD_TUCMD_L4T_SCTP  0x00001000  /* L4 Packet TYPE of SCTP */
2374#define IXGBE_ADVTXD_TUCMD_MKRREQ    0x00002000 /*Req requires Markers and CRC*/
2375#define IXGBE_ADVTXD_POPTS_IPSEC      0x00000400 /* IPSec offload request */
2376#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
2377#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
2378#define IXGBE_ADVTXT_TUCMD_FCOE      0x00008000       /* FCoE Frame Type */
2379#define IXGBE_ADVTXD_FCOEF_EOF_MASK  (0x3 << 10)      /* FC EOF index */
2380#define IXGBE_ADVTXD_FCOEF_SOF       ((1 << 2) << 10) /* FC SOF index */
2381#define IXGBE_ADVTXD_FCOEF_PARINC    ((1 << 3) << 10) /* Rel_Off in F_CTL */
2382#define IXGBE_ADVTXD_FCOEF_ORIE      ((1 << 4) << 10) /* Orientation: End */
2383#define IXGBE_ADVTXD_FCOEF_ORIS      ((1 << 5) << 10) /* Orientation: Start */
2384#define IXGBE_ADVTXD_FCOEF_EOF_N     (0x0 << 10)      /* 00: EOFn */
2385#define IXGBE_ADVTXD_FCOEF_EOF_T     (0x1 << 10)      /* 01: EOFt */
2386#define IXGBE_ADVTXD_FCOEF_EOF_NI    (0x2 << 10)      /* 10: EOFni */
2387#define IXGBE_ADVTXD_FCOEF_EOF_A     (0x3 << 10)      /* 11: EOFa */
2388#define IXGBE_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
2389#define IXGBE_ADVTXD_MSS_SHIFT       16  /* Adv ctxt MSS shift */
2390
2391/* Autonegotiation advertised speeds */
2392typedef u32 ixgbe_autoneg_advertised;
2393/* Link speed */
2394typedef u32 ixgbe_link_speed;
2395#define IXGBE_LINK_SPEED_UNKNOWN   0
2396#define IXGBE_LINK_SPEED_100_FULL  0x0008
2397#define IXGBE_LINK_SPEED_1GB_FULL  0x0020
2398#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
2399#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
2400                                        IXGBE_LINK_SPEED_10GB_FULL)
2401#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
2402                                        IXGBE_LINK_SPEED_1GB_FULL | \
2403                                        IXGBE_LINK_SPEED_10GB_FULL)
2404
2405
2406/* Physical layer type */
2407typedef u32 ixgbe_physical_layer;
2408#define IXGBE_PHYSICAL_LAYER_UNKNOWN      0
2409#define IXGBE_PHYSICAL_LAYER_10GBASE_T    0x0001
2410#define IXGBE_PHYSICAL_LAYER_1000BASE_T   0x0002
2411#define IXGBE_PHYSICAL_LAYER_100BASE_TX   0x0004
2412#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU  0x0008
2413#define IXGBE_PHYSICAL_LAYER_10GBASE_LR   0x0010
2414#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM  0x0020
2415#define IXGBE_PHYSICAL_LAYER_10GBASE_SR   0x0040
2416#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4  0x0080
2417#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4  0x0100
2418#define IXGBE_PHYSICAL_LAYER_1000BASE_KX  0x0200
2419#define IXGBE_PHYSICAL_LAYER_1000BASE_BX  0x0400
2420#define IXGBE_PHYSICAL_LAYER_10GBASE_KR   0x0800
2421#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
2422#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
2423
2424/* Flow Control Data Sheet defined values
2425 * Calculation and defines taken from 802.1bb Annex O
2426 */
2427
2428/* BitTimes (BT) conversion */
2429#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
2430#define IXGBE_B2BT(BT) (BT * 8)
2431
2432/* Calculate Delay to respond to PFC */
2433#define IXGBE_PFC_D     672
2434
2435/* Calculate Cable Delay */
2436#define IXGBE_CABLE_DC  5556 /* Delay Copper */
2437#define IXGBE_CABLE_DO  5000 /* Delay Optical */
2438
2439/* Calculate Interface Delay X540 */
2440#define IXGBE_PHY_DC    25600   /* Delay 10G BASET */
2441#define IXGBE_MAC_DC    8192    /* Delay Copper XAUI interface */
2442#define IXGBE_XAUI_DC   (2 * 2048) /* Delay Copper Phy */
2443
2444#define IXGBE_ID_X540   (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
2445
2446/* Calculate Interface Delay 82598, 82599 */
2447#define IXGBE_PHY_D     12800
2448#define IXGBE_MAC_D     4096
2449#define IXGBE_XAUI_D    (2 * 1024)
2450
2451#define IXGBE_ID        (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
2452
2453/* Calculate Delay incurred from higher layer */
2454#define IXGBE_HD        6144
2455
2456/* Calculate PCI Bus delay for low thresholds */
2457#define IXGBE_PCI_DELAY 10000
2458
2459/* Calculate X540 delay value in bit times */
2460#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
2461                        ((36 * \
2462                          (IXGBE_B2BT(_max_frame_link) + \
2463                           IXGBE_PFC_D + \
2464                           (2 * IXGBE_CABLE_DC) + \
2465                           (2 * IXGBE_ID_X540) + \
2466                           IXGBE_HD) / 25 + 1) + \
2467                         2 * IXGBE_B2BT(_max_frame_tc))
2468
2469/* Calculate 82599, 82598 delay value in bit times */
2470#define IXGBE_DV(_max_frame_link, _max_frame_tc) \
2471                        ((36 * \
2472                          (IXGBE_B2BT(_max_frame_link) + \
2473                           IXGBE_PFC_D + \
2474                           (2 * IXGBE_CABLE_DC) + \
2475                           (2 * IXGBE_ID) + \
2476                           IXGBE_HD) / 25 + 1) + \
2477                         2 * IXGBE_B2BT(_max_frame_tc))
2478
2479/* Calculate low threshold delay values */
2480#define IXGBE_LOW_DV_X540(_max_frame_tc) \
2481                        (2 * IXGBE_B2BT(_max_frame_tc) + \
2482                        (36 * IXGBE_PCI_DELAY / 25) + 1)
2483#define IXGBE_LOW_DV(_max_frame_tc) \
2484                        (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
2485
2486/* Software ATR hash keys */
2487#define IXGBE_ATR_BUCKET_HASH_KEY    0x3DAD14E2
2488#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
2489
2490/* Software ATR input stream values and masks */
2491#define IXGBE_ATR_HASH_MASK     0x7fff
2492#define IXGBE_ATR_L4TYPE_MASK      0x3
2493#define IXGBE_ATR_L4TYPE_UDP       0x1
2494#define IXGBE_ATR_L4TYPE_TCP       0x2
2495#define IXGBE_ATR_L4TYPE_SCTP      0x3
2496#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
2497enum ixgbe_atr_flow_type {
2498        IXGBE_ATR_FLOW_TYPE_IPV4   = 0x0,
2499        IXGBE_ATR_FLOW_TYPE_UDPV4  = 0x1,
2500        IXGBE_ATR_FLOW_TYPE_TCPV4  = 0x2,
2501        IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
2502        IXGBE_ATR_FLOW_TYPE_IPV6   = 0x4,
2503        IXGBE_ATR_FLOW_TYPE_UDPV6  = 0x5,
2504        IXGBE_ATR_FLOW_TYPE_TCPV6  = 0x6,
2505        IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
2506};
2507
2508/* Flow Director ATR input struct. */
2509union ixgbe_atr_input {
2510        /*
2511         * Byte layout in order, all values with MSB first:
2512         *
2513         * vm_pool    - 1 byte
2514         * flow_type  - 1 byte
2515         * vlan_id    - 2 bytes
2516         * src_ip     - 16 bytes
2517         * dst_ip     - 16 bytes
2518         * src_port   - 2 bytes
2519         * dst_port   - 2 bytes
2520         * flex_bytes - 2 bytes
2521         * bkt_hash   - 2 bytes
2522         */
2523        struct {
2524                u8     vm_pool;
2525                u8     flow_type;
2526                __be16 vlan_id;
2527                __be32 dst_ip[4];
2528                __be32 src_ip[4];
2529                __be16 src_port;
2530                __be16 dst_port;
2531                __be16 flex_bytes;
2532                __be16 bkt_hash;
2533        } formatted;
2534        __be32 dword_stream[11];
2535};
2536
2537/* Flow Director compressed ATR hash input struct */
2538union ixgbe_atr_hash_dword {
2539        struct {
2540                u8 vm_pool;
2541                u8 flow_type;
2542                __be16 vlan_id;
2543        } formatted;
2544        __be32 ip;
2545        struct {
2546                __be16 src;
2547                __be16 dst;
2548        } port;
2549        __be16 flex_bytes;
2550        __be32 dword;
2551};
2552
2553enum ixgbe_eeprom_type {
2554        ixgbe_eeprom_uninitialized = 0,
2555        ixgbe_eeprom_spi,
2556        ixgbe_flash,
2557        ixgbe_eeprom_none /* No NVM support */
2558};
2559
2560enum ixgbe_mac_type {
2561        ixgbe_mac_unknown = 0,
2562        ixgbe_mac_82598EB,
2563        ixgbe_mac_82599EB,
2564        ixgbe_mac_X540,
2565        ixgbe_num_macs
2566};
2567
2568enum ixgbe_phy_type {
2569        ixgbe_phy_unknown = 0,
2570        ixgbe_phy_none,
2571        ixgbe_phy_tn,
2572        ixgbe_phy_aq,
2573        ixgbe_phy_cu_unknown,
2574        ixgbe_phy_qt,
2575        ixgbe_phy_xaui,
2576        ixgbe_phy_nl,
2577        ixgbe_phy_sfp_passive_tyco,
2578        ixgbe_phy_sfp_passive_unknown,
2579        ixgbe_phy_sfp_active_unknown,
2580        ixgbe_phy_sfp_avago,
2581        ixgbe_phy_sfp_ftl,
2582        ixgbe_phy_sfp_ftl_active,
2583        ixgbe_phy_sfp_unknown,
2584        ixgbe_phy_sfp_intel,
2585        ixgbe_phy_sfp_unsupported,
2586        ixgbe_phy_generic
2587};
2588
2589/*
2590 * SFP+ module type IDs:
2591 *
2592 * ID   Module Type
2593 * =============
2594 * 0    SFP_DA_CU
2595 * 1    SFP_SR
2596 * 2    SFP_LR
2597 * 3    SFP_DA_CU_CORE0 - 82599-specific
2598 * 4    SFP_DA_CU_CORE1 - 82599-specific
2599 * 5    SFP_SR/LR_CORE0 - 82599-specific
2600 * 6    SFP_SR/LR_CORE1 - 82599-specific
2601 */
2602enum ixgbe_sfp_type {
2603        ixgbe_sfp_type_da_cu = 0,
2604        ixgbe_sfp_type_sr = 1,
2605        ixgbe_sfp_type_lr = 2,
2606        ixgbe_sfp_type_da_cu_core0 = 3,
2607        ixgbe_sfp_type_da_cu_core1 = 4,
2608        ixgbe_sfp_type_srlr_core0 = 5,
2609        ixgbe_sfp_type_srlr_core1 = 6,
2610        ixgbe_sfp_type_da_act_lmt_core0 = 7,
2611        ixgbe_sfp_type_da_act_lmt_core1 = 8,
2612        ixgbe_sfp_type_1g_cu_core0 = 9,
2613        ixgbe_sfp_type_1g_cu_core1 = 10,
2614        ixgbe_sfp_type_1g_sx_core0 = 11,
2615        ixgbe_sfp_type_1g_sx_core1 = 12,
2616        ixgbe_sfp_type_1g_lx_core0 = 13,
2617        ixgbe_sfp_type_1g_lx_core1 = 14,
2618        ixgbe_sfp_type_not_present = 0xFFFE,
2619        ixgbe_sfp_type_unknown = 0xFFFF
2620};
2621
2622enum ixgbe_media_type {
2623        ixgbe_media_type_unknown = 0,
2624        ixgbe_media_type_fiber,
2625        ixgbe_media_type_fiber_lco,
2626        ixgbe_media_type_copper,
2627        ixgbe_media_type_backplane,
2628        ixgbe_media_type_cx4,
2629        ixgbe_media_type_virtual
2630};
2631
2632/* Flow Control Settings */
2633enum ixgbe_fc_mode {
2634        ixgbe_fc_none = 0,
2635        ixgbe_fc_rx_pause,
2636        ixgbe_fc_tx_pause,
2637        ixgbe_fc_full,
2638        ixgbe_fc_default
2639};
2640
2641/* Smart Speed Settings */
2642#define IXGBE_SMARTSPEED_MAX_RETRIES    3
2643enum ixgbe_smart_speed {
2644        ixgbe_smart_speed_auto = 0,
2645        ixgbe_smart_speed_on,
2646        ixgbe_smart_speed_off
2647};
2648
2649/* PCI bus types */
2650enum ixgbe_bus_type {
2651        ixgbe_bus_type_unknown = 0,
2652        ixgbe_bus_type_pci,
2653        ixgbe_bus_type_pcix,
2654        ixgbe_bus_type_pci_express,
2655        ixgbe_bus_type_reserved
2656};
2657
2658/* PCI bus speeds */
2659enum ixgbe_bus_speed {
2660        ixgbe_bus_speed_unknown = 0,
2661        ixgbe_bus_speed_33      = 33,
2662        ixgbe_bus_speed_66      = 66,
2663        ixgbe_bus_speed_100     = 100,
2664        ixgbe_bus_speed_120     = 120,
2665        ixgbe_bus_speed_133     = 133,
2666        ixgbe_bus_speed_2500    = 2500,
2667        ixgbe_bus_speed_5000    = 5000,
2668        ixgbe_bus_speed_8000    = 8000,
2669        ixgbe_bus_speed_reserved
2670};
2671
2672/* PCI bus widths */
2673enum ixgbe_bus_width {
2674        ixgbe_bus_width_unknown = 0,
2675        ixgbe_bus_width_pcie_x1 = 1,
2676        ixgbe_bus_width_pcie_x2 = 2,
2677        ixgbe_bus_width_pcie_x4 = 4,
2678        ixgbe_bus_width_pcie_x8 = 8,
2679        ixgbe_bus_width_32      = 32,
2680        ixgbe_bus_width_64      = 64,
2681        ixgbe_bus_width_reserved
2682};
2683
2684struct ixgbe_addr_filter_info {
2685        u32 num_mc_addrs;
2686        u32 rar_used_count;
2687        u32 mta_in_use;
2688        u32 overflow_promisc;
2689        bool uc_set_promisc;
2690        bool user_set_promisc;
2691};
2692
2693/* Bus parameters */
2694struct ixgbe_bus_info {
2695        enum ixgbe_bus_speed speed;
2696        enum ixgbe_bus_width width;
2697        enum ixgbe_bus_type type;
2698
2699        u16 func;
2700        u16 lan_id;
2701};
2702
2703/* Flow control parameters */
2704struct ixgbe_fc_info {
2705        u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */
2706        u32 low_water; /* Flow Control Low-water */
2707        u16 pause_time; /* Flow Control Pause timer */
2708        bool send_xon; /* Flow control send XON */
2709        bool strict_ieee; /* Strict IEEE mode */
2710        bool disable_fc_autoneg; /* Do not autonegotiate FC */
2711        bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
2712        enum ixgbe_fc_mode current_mode; /* FC mode in effect */
2713        enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
2714};
2715
2716/* Statistics counters collected by the MAC */
2717struct ixgbe_hw_stats {
2718        u64 crcerrs;
2719        u64 illerrc;
2720        u64 errbc;
2721        u64 mspdc;
2722        u64 mpctotal;
2723        u64 mpc[8];
2724        u64 mlfc;
2725        u64 mrfc;
2726        u64 rlec;
2727        u64 lxontxc;
2728        u64 lxonrxc;
2729        u64 lxofftxc;
2730        u64 lxoffrxc;
2731        u64 pxontxc[8];
2732        u64 pxonrxc[8];
2733        u64 pxofftxc[8];
2734        u64 pxoffrxc[8];
2735        u64 prc64;
2736        u64 prc127;
2737        u64 prc255;
2738        u64 prc511;
2739        u64 prc1023;
2740        u64 prc1522;
2741        u64 gprc;
2742        u64 bprc;
2743        u64 mprc;
2744        u64 gptc;
2745        u64 gorc;
2746        u64 gotc;
2747        u64 rnbc[8];
2748        u64 ruc;
2749        u64 rfc;
2750        u64 roc;
2751        u64 rjc;
2752        u64 mngprc;
2753        u64 mngpdc;
2754        u64 mngptc;
2755        u64 tor;
2756        u64 tpr;
2757        u64 tpt;
2758        u64 ptc64;
2759        u64 ptc127;
2760        u64 ptc255;
2761        u64 ptc511;
2762        u64 ptc1023;
2763        u64 ptc1522;
2764        u64 mptc;
2765        u64 bptc;
2766        u64 xec;
2767        u64 rqsmr[16];
2768        u64 tqsmr[8];
2769        u64 qprc[16];
2770        u64 qptc[16];
2771        u64 qbrc[16];
2772        u64 qbtc[16];
2773        u64 qprdc[16];
2774        u64 pxon2offc[8];
2775        u64 fdirustat_add;
2776        u64 fdirustat_remove;
2777        u64 fdirfstat_fadd;
2778        u64 fdirfstat_fremove;
2779        u64 fdirmatch;
2780        u64 fdirmiss;
2781        u64 fccrc;
2782        u64 fcoerpdc;
2783        u64 fcoeprc;
2784        u64 fcoeptc;
2785        u64 fcoedwrc;
2786        u64 fcoedwtc;
2787        u64 fcoe_noddp;
2788        u64 fcoe_noddp_ext_buff;
2789        u64 b2ospc;
2790        u64 b2ogprc;
2791        u64 o2bgptc;
2792        u64 o2bspc;
2793};
2794
2795/* forward declaration */
2796struct ixgbe_hw;
2797
2798/* iterator type for walking multicast address lists */
2799typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
2800                                  u32 *vmdq);
2801
2802/* Function pointer table */
2803struct ixgbe_eeprom_operations {
2804        s32 (*init_params)(struct ixgbe_hw *);
2805        s32 (*read)(struct ixgbe_hw *, u16, u16 *);
2806        s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2807        s32 (*write)(struct ixgbe_hw *, u16, u16);
2808        s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2809        s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
2810        s32 (*update_checksum)(struct ixgbe_hw *);
2811        u16 (*calc_checksum)(struct ixgbe_hw *);
2812};
2813
2814struct ixgbe_mac_operations {
2815        s32 (*init_hw)(struct ixgbe_hw *);
2816        s32 (*reset_hw)(struct ixgbe_hw *);
2817        s32 (*start_hw)(struct ixgbe_hw *);
2818        s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
2819        enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
2820        u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
2821        s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
2822        s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
2823        s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
2824        s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
2825        s32 (*stop_adapter)(struct ixgbe_hw *);
2826        s32 (*get_bus_info)(struct ixgbe_hw *);
2827        void (*set_lan_id)(struct ixgbe_hw *);
2828        s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
2829        s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
2830        s32 (*setup_sfp)(struct ixgbe_hw *);
2831        s32 (*disable_rx_buff)(struct ixgbe_hw *);
2832        s32 (*enable_rx_buff)(struct ixgbe_hw *);
2833        s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
2834        s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
2835        void (*release_swfw_sync)(struct ixgbe_hw *, u16);
2836
2837        /* Link */
2838        void (*disable_tx_laser)(struct ixgbe_hw *);
2839        void (*enable_tx_laser)(struct ixgbe_hw *);
2840        void (*flap_tx_laser)(struct ixgbe_hw *);
2841        s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
2842        s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2843        s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2844                                     bool *);
2845
2846        /* Packet Buffer Manipulation */
2847        void (*set_rxpba)(struct ixgbe_hw *, int, u32, int);
2848
2849        /* LED */
2850        s32 (*led_on)(struct ixgbe_hw *, u32);
2851        s32 (*led_off)(struct ixgbe_hw *, u32);
2852        s32 (*blink_led_start)(struct ixgbe_hw *, u32);
2853        s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
2854
2855        /* RAR, Multicast, VLAN */
2856        s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
2857        s32 (*clear_rar)(struct ixgbe_hw *, u32);
2858        s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
2859        s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
2860        s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
2861        s32 (*init_rx_addrs)(struct ixgbe_hw *);
2862        s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
2863        s32 (*enable_mc)(struct ixgbe_hw *);
2864        s32 (*disable_mc)(struct ixgbe_hw *);
2865        s32 (*clear_vfta)(struct ixgbe_hw *);
2866        s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
2867        s32 (*init_uta_tables)(struct ixgbe_hw *);
2868        void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
2869        void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
2870
2871        /* Flow Control */
2872        s32 (*fc_enable)(struct ixgbe_hw *);
2873
2874        /* Manageability interface */
2875        s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
2876        s32 (*get_thermal_sensor_data)(struct ixgbe_hw *);
2877        s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);
2878        bool (*mng_fw_enabled)(struct ixgbe_hw *hw);
2879};
2880
2881struct ixgbe_phy_operations {
2882        s32 (*identify)(struct ixgbe_hw *);
2883        s32 (*identify_sfp)(struct ixgbe_hw *);
2884        s32 (*init)(struct ixgbe_hw *);
2885        s32 (*reset)(struct ixgbe_hw *);
2886        s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
2887        s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
2888        s32 (*setup_link)(struct ixgbe_hw *);
2889        s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
2890        s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
2891        s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
2892        s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
2893        s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
2894        s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
2895        s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
2896        s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
2897        s32 (*check_overtemp)(struct ixgbe_hw *);
2898};
2899
2900struct ixgbe_eeprom_info {
2901        struct ixgbe_eeprom_operations  ops;
2902        enum ixgbe_eeprom_type          type;
2903        u32                             semaphore_delay;
2904        u16                             word_size;
2905        u16                             address_bits;
2906        u16                             word_page_size;
2907};
2908
2909#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED       0x01
2910struct ixgbe_mac_info {
2911        struct ixgbe_mac_operations     ops;
2912        enum ixgbe_mac_type             type;
2913        u8                              addr[ETH_ALEN];
2914        u8                              perm_addr[ETH_ALEN];
2915        u8                              san_addr[ETH_ALEN];
2916        /* prefix for World Wide Node Name (WWNN) */
2917        u16                             wwnn_prefix;
2918        /* prefix for World Wide Port Name (WWPN) */
2919        u16                             wwpn_prefix;
2920        u16                             max_msix_vectors;
2921#define IXGBE_MAX_MTA                   128
2922        u32                             mta_shadow[IXGBE_MAX_MTA];
2923        s32                             mc_filter_type;
2924        u32                             mcft_size;
2925        u32                             vft_size;
2926        u32                             num_rar_entries;
2927        u32                             rar_highwater;
2928        u32                             rx_pb_size;
2929        u32                             max_tx_queues;
2930        u32                             max_rx_queues;
2931        u32                             orig_autoc;
2932        u32                             cached_autoc;
2933        u32                             orig_autoc2;
2934        bool                            orig_link_settings_stored;
2935        bool                            autotry_restart;
2936        u8                              flags;
2937        u8                              san_mac_rar_index;
2938        struct ixgbe_thermal_sensor_data  thermal_sensor_data;
2939};
2940
2941struct ixgbe_phy_info {
2942        struct ixgbe_phy_operations     ops;
2943        struct mdio_if_info             mdio;
2944        enum ixgbe_phy_type             type;
2945        u32                             id;
2946        enum ixgbe_sfp_type             sfp_type;
2947        bool                            sfp_setup_needed;
2948        u32                             revision;
2949        enum ixgbe_media_type           media_type;
2950        bool                            reset_disable;
2951        ixgbe_autoneg_advertised        autoneg_advertised;
2952        enum ixgbe_smart_speed          smart_speed;
2953        bool                            smart_speed_active;
2954        bool                            multispeed_fiber;
2955        bool                            reset_if_overtemp;
2956};
2957
2958#include "ixgbe_mbx.h"
2959
2960struct ixgbe_mbx_operations {
2961        s32 (*init_params)(struct ixgbe_hw *hw);
2962        s32 (*read)(struct ixgbe_hw *, u32 *, u16,  u16);
2963        s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
2964        s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16,  u16);
2965        s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
2966        s32 (*check_for_msg)(struct ixgbe_hw *, u16);
2967        s32 (*check_for_ack)(struct ixgbe_hw *, u16);
2968        s32 (*check_for_rst)(struct ixgbe_hw *, u16);
2969};
2970
2971struct ixgbe_mbx_stats {
2972        u32 msgs_tx;
2973        u32 msgs_rx;
2974
2975        u32 acks;
2976        u32 reqs;
2977        u32 rsts;
2978};
2979
2980struct ixgbe_mbx_info {
2981        struct ixgbe_mbx_operations ops;
2982        struct ixgbe_mbx_stats stats;
2983        u32 timeout;
2984        u32 usec_delay;
2985        u32 v2p_mailbox;
2986        u16 size;
2987};
2988
2989struct ixgbe_hw {
2990        u8 __iomem                      *hw_addr;
2991        void                            *back;
2992        struct ixgbe_mac_info           mac;
2993        struct ixgbe_addr_filter_info   addr_ctrl;
2994        struct ixgbe_fc_info            fc;
2995        struct ixgbe_phy_info           phy;
2996        struct ixgbe_eeprom_info        eeprom;
2997        struct ixgbe_bus_info           bus;
2998        struct ixgbe_mbx_info           mbx;
2999        u16                             device_id;
3000        u16                             vendor_id;

3001        u16                             subsystem_device_id;
3002        u16                             subsystem_vendor_id;
3003        u8                              revision_id;
3004        bool                            adapter_stopped;
3005        bool                            force_full_reset;
3006        bool                            allow_unsupported_sfp;
3007        bool                            mng_fw_enabled;
3008        bool                            wol_enabled;
3009};
3010
3011struct ixgbe_info {
3012        enum ixgbe_mac_type             mac;
3013        s32                             (*get_invariants)(struct ixgbe_hw *);
3014        struct ixgbe_mac_operations     *mac_ops;
3015        struct ixgbe_eeprom_operations  *eeprom_ops;
3016        struct ixgbe_phy_operations     *phy_ops;
3017        struct ixgbe_mbx_operations     *mbx_ops;
3018};
3019
3020
3021/* Error Codes */
3022#define IXGBE_ERR_EEPROM                        -1
3023#define IXGBE_ERR_EEPROM_CHECKSUM               -2
3024#define IXGBE_ERR_PHY                           -3
3025#define IXGBE_ERR_CONFIG                        -4
3026#define IXGBE_ERR_PARAM                         -5
3027#define IXGBE_ERR_MAC_TYPE                      -6
3028#define IXGBE_ERR_UNKNOWN_PHY                   -7
3029#define IXGBE_ERR_LINK_SETUP                    -8
3030#define IXGBE_ERR_ADAPTER_STOPPED               -9
3031#define IXGBE_ERR_INVALID_MAC_ADDR              -10
3032#define IXGBE_ERR_DEVICE_NOT_SUPPORTED          -11
3033#define IXGBE_ERR_MASTER_REQUESTS_PENDING       -12
3034#define IXGBE_ERR_INVALID_LINK_SETTINGS         -13
3035#define IXGBE_ERR_AUTONEG_NOT_COMPLETE          -14
3036#define IXGBE_ERR_RESET_FAILED                  -15
3037#define IXGBE_ERR_SWFW_SYNC                     -16
3038#define IXGBE_ERR_PHY_ADDR_INVALID              -17
3039#define IXGBE_ERR_I2C                           -18
3040#define IXGBE_ERR_SFP_NOT_SUPPORTED             -19
3041#define IXGBE_ERR_SFP_NOT_PRESENT               -20
3042#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT       -21
3043#define IXGBE_ERR_NO_SAN_ADDR_PTR               -22
3044#define IXGBE_ERR_FDIR_REINIT_FAILED            -23
3045#define IXGBE_ERR_EEPROM_VERSION                -24
3046#define IXGBE_ERR_NO_SPACE                      -25
3047#define IXGBE_ERR_OVERTEMP                      -26
3048#define IXGBE_ERR_FC_NOT_NEGOTIATED             -27
3049#define IXGBE_ERR_FC_NOT_SUPPORTED              -28
3050#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE        -30
3051#define IXGBE_ERR_PBA_SECTION                   -31
3052#define IXGBE_ERR_INVALID_ARGUMENT              -32
3053#define IXGBE_ERR_HOST_INTERFACE_COMMAND        -33
3054#define IXGBE_NOT_IMPLEMENTED                   0x7FFFFFFF
3055
3056#endif /* _IXGBE_TYPE_H_ */
3057