LXR linux/drivers/net/ethernet/rdc/r6040.c

   1/*
   2 * RDC R6040 Fast Ethernet MAC support
   3 *
   4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
   5 * Copyright (C) 2007
   6 *      Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
   7 * Copyright (C) 2007-2012 Florian Fainelli <florian@openwrt.org>
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License
  11 * as published by the Free Software Foundation; either version 2
  12 * of the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the
  21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  22 * Boston, MA  02110-1301, USA.
  23*/
  24
  25#include <linux/kernel.h>
  26#include <linux/module.h>
  27#include <linux/moduleparam.h>
  28#include <linux/string.h>
  29#include <linux/timer.h>
  30#include <linux/errno.h>
  31#include <linux/ioport.h>
  32#include <linux/interrupt.h>
  33#include <linux/pci.h>
  34#include <linux/netdevice.h>
  35#include <linux/etherdevice.h>
  36#include <linux/skbuff.h>
  37#include <linux/init.h>
  38#include <linux/delay.h>
  39#include <linux/mii.h>
  40#include <linux/ethtool.h>
  41#include <linux/crc32.h>
  42#include <linux/spinlock.h>
  43#include <linux/bitops.h>
  44#include <linux/io.h>
  45#include <linux/irq.h>
  46#include <linux/uaccess.h>
  47#include <linux/phy.h>
  48
  49#include <asm/processor.h>
  50
  51#define DRV_NAME        "r6040"
  52#define DRV_VERSION     "0.28"
  53#define DRV_RELDATE     "07Oct2011"
  54
  55/* Time in jiffies before concluding the transmitter is hung. */
  56#define TX_TIMEOUT      (6000 * HZ / 1000)
  57
  58/* RDC MAC I/O Size */
  59#define R6040_IO_SIZE   256
  60
  61/* MAX RDC MAC */
  62#define MAX_MAC         2
  63
  64/* MAC registers */
  65#define MCR0            0x00    /* Control register 0 */
  66#define  MCR0_RCVEN     0x0002  /* Receive enable */
  67#define  MCR0_PROMISC   0x0020  /* Promiscuous mode */
  68#define  MCR0_HASH_EN   0x0100  /* Enable multicast hash table function */
  69#define  MCR0_XMTEN     0x1000  /* Transmission enable */
  70#define  MCR0_FD        0x8000  /* Full/Half duplex */
  71#define MCR1            0x04    /* Control register 1 */
  72#define  MAC_RST        0x0001  /* Reset the MAC */
  73#define MBCR            0x08    /* Bus control */
  74#define MT_ICR          0x0C    /* TX interrupt control */
  75#define MR_ICR          0x10    /* RX interrupt control */
  76#define MTPR            0x14    /* TX poll command register */
  77#define  TM2TX          0x0001  /* Trigger MAC to transmit */
  78#define MR_BSR          0x18    /* RX buffer size */
  79#define MR_DCR          0x1A    /* RX descriptor control */
  80#define MLSR            0x1C    /* Last status */
  81#define  TX_FIFO_UNDR   0x0200  /* TX FIFO under-run */
  82#define  TX_EXCEEDC     0x2000  /* Transmit exceed collision */
  83#define  TX_LATEC       0x4000  /* Transmit late collision */
  84#define MMDIO           0x20    /* MDIO control register */
  85#define  MDIO_WRITE     0x4000  /* MDIO write */
  86#define  MDIO_READ      0x2000  /* MDIO read */
  87#define MMRD            0x24    /* MDIO read data register */
  88#define MMWD            0x28    /* MDIO write data register */
  89#define MTD_SA0         0x2C    /* TX descriptor start address 0 */
  90#define MTD_SA1         0x30    /* TX descriptor start address 1 */
  91#define MRD_SA0         0x34    /* RX descriptor start address 0 */
  92#define MRD_SA1         0x38    /* RX descriptor start address 1 */
  93#define MISR            0x3C    /* Status register */
  94#define MIER            0x40    /* INT enable register */
  95#define  MSK_INT        0x0000  /* Mask off interrupts */
  96#define  RX_FINISH      0x0001  /* RX finished */
  97#define  RX_NO_DESC     0x0002  /* No RX descriptor available */
  98#define  RX_FIFO_FULL   0x0004  /* RX FIFO full */
  99#define  RX_EARLY       0x0008  /* RX early */
 100#define  TX_FINISH      0x0010  /* TX finished */
 101#define  TX_EARLY       0x0080  /* TX early */
 102#define  EVENT_OVRFL    0x0100  /* Event counter overflow */
 103#define  LINK_CHANGED   0x0200  /* PHY link changed */
 104#define ME_CISR         0x44    /* Event counter INT status */
 105#define ME_CIER         0x48    /* Event counter INT enable  */
 106#define MR_CNT          0x50    /* Successfully received packet counter */
 107#define ME_CNT0         0x52    /* Event counter 0 */
 108#define ME_CNT1         0x54    /* Event counter 1 */
 109#define ME_CNT2         0x56    /* Event counter 2 */
 110#define ME_CNT3         0x58    /* Event counter 3 */
 111#define MT_CNT          0x5A    /* Successfully transmit packet counter */
 112#define ME_CNT4         0x5C    /* Event counter 4 */
 113#define MP_CNT          0x5E    /* Pause frame counter register */
 114#define MAR0            0x60    /* Hash table 0 */
 115#define MAR1            0x62    /* Hash table 1 */
 116#define MAR2            0x64    /* Hash table 2 */
 117#define MAR3            0x66    /* Hash table 3 */
 118#define MID_0L          0x68    /* Multicast address MID0 Low */
 119#define MID_0M          0x6A    /* Multicast address MID0 Medium */
 120#define MID_0H          0x6C    /* Multicast address MID0 High */
 121#define MID_1L          0x70    /* MID1 Low */
 122#define MID_1M          0x72    /* MID1 Medium */
 123#define MID_1H          0x74    /* MID1 High */
 124#define MID_2L          0x78    /* MID2 Low */
 125#define MID_2M          0x7A    /* MID2 Medium */
 126#define MID_2H          0x7C    /* MID2 High */
 127#define MID_3L          0x80    /* MID3 Low */
 128#define MID_3M          0x82    /* MID3 Medium */
 129#define MID_3H          0x84    /* MID3 High */
 130#define PHY_CC          0x88    /* PHY status change configuration register */
 131#define  SCEN           0x8000  /* PHY status change enable */
 132#define  PHYAD_SHIFT    8       /* PHY address shift */
 133#define  TMRDIV_SHIFT   0       /* Timer divider shift */
 134#define PHY_ST          0x8A    /* PHY status register */
 135#define MAC_SM          0xAC    /* MAC status machine */
 136#define  MAC_SM_RST     0x0002  /* MAC status machine reset */
 137#define MAC_ID          0xBE    /* Identifier register */
 138
 139#define TX_DCNT         0x80    /* TX descriptor count */
 140#define RX_DCNT         0x80    /* RX descriptor count */
 141#define MAX_BUF_SIZE    0x600
 142#define RX_DESC_SIZE    (RX_DCNT * sizeof(struct r6040_descriptor))
 143#define TX_DESC_SIZE    (TX_DCNT * sizeof(struct r6040_descriptor))
 144#define MBCR_DEFAULT    0x012A  /* MAC Bus Control Register */
 145#define MCAST_MAX       3       /* Max number multicast addresses to filter */
 146
 147#define MAC_DEF_TIMEOUT 2048    /* Default MAC read/write operation timeout */
 148
 149/* Descriptor status */
 150#define DSC_OWNER_MAC   0x8000  /* MAC is the owner of this descriptor */
 151#define DSC_RX_OK       0x4000  /* RX was successful */
 152#define DSC_RX_ERR      0x0800  /* RX PHY error */
 153#define DSC_RX_ERR_DRI  0x0400  /* RX dribble packet */
 154#define DSC_RX_ERR_BUF  0x0200  /* RX length exceeds buffer size */
 155#define DSC_RX_ERR_LONG 0x0100  /* RX length > maximum packet length */
 156#define DSC_RX_ERR_RUNT 0x0080  /* RX packet length < 64 byte */
 157#define DSC_RX_ERR_CRC  0x0040  /* RX CRC error */
 158#define DSC_RX_BCAST    0x0020  /* RX broadcast (no error) */
 159#define DSC_RX_MCAST    0x0010  /* RX multicast (no error) */
 160#define DSC_RX_MCH_HIT  0x0008  /* RX multicast hit in hash table (no error) */
 161#define DSC_RX_MIDH_HIT 0x0004  /* RX MID table hit (no error) */
 162#define DSC_RX_IDX_MID_MASK 3   /* RX mask for the index of matched MIDx */
 163
 164MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
 165        "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
 166        "Florian Fainelli <florian@openwrt.org>");
 167MODULE_LICENSE("GPL");
 168MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
 169MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
 170
 171/* RX and TX interrupts that we handle */
 172#define RX_INTS                 (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
 173#define TX_INTS                 (TX_FINISH)
 174#define INT_MASK                (RX_INTS | TX_INTS)
 175
 176struct r6040_descriptor {
 177        u16     status, len;            /* 0-3 */
 178        __le32  buf;                    /* 4-7 */
 179        __le32  ndesc;                  /* 8-B */
 180        u32     rev1;                   /* C-F */
 181        char    *vbufp;                 /* 10-13 */
 182        struct r6040_descriptor *vndescp;       /* 14-17 */
 183        struct sk_buff *skb_ptr;        /* 18-1B */
 184        u32     rev2;                   /* 1C-1F */
 185} __aligned(32);
 186
 187struct r6040_private {
 188        spinlock_t lock;                /* driver lock */
 189        struct pci_dev *pdev;
 190        struct r6040_descriptor *rx_insert_ptr;
 191        struct r6040_descriptor *rx_remove_ptr;
 192        struct r6040_descriptor *tx_insert_ptr;
 193        struct r6040_descriptor *tx_remove_ptr;
 194        struct r6040_descriptor *rx_ring;
 195        struct r6040_descriptor *tx_ring;
 196        dma_addr_t rx_ring_dma;
 197        dma_addr_t tx_ring_dma;
 198        u16     tx_free_desc;
 199        u16     mcr0;
 200        struct net_device *dev;
 201        struct mii_bus *mii_bus;
 202        struct napi_struct napi;
 203        void __iomem *base;
 204        struct phy_device *phydev;
 205        int old_link;
 206        int old_duplex;
 207};
 208
 209static char version[] = DRV_NAME
 210        ": RDC R6040 NAPI net driver,"
 211        "version "DRV_VERSION " (" DRV_RELDATE ")";
 212
 213/* Read a word data from PHY Chip */
 214static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
 215{
 216        int limit = MAC_DEF_TIMEOUT;
 217        u16 cmd;
 218
 219        iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
 220        /* Wait for the read bit to be cleared */
 221        while (limit--) {
 222                cmd = ioread16(ioaddr + MMDIO);
 223                if (!(cmd & MDIO_READ))
 224                        break;
 225        }
 226
 227        if (limit < 0)
 228                return -ETIMEDOUT;
 229
 230        return ioread16(ioaddr + MMRD);
 231}
 232
 233/* Write a word data from PHY Chip */
 234static int r6040_phy_write(void __iomem *ioaddr,
 235                                        int phy_addr, int reg, u16 val)
 236{
 237        int limit = MAC_DEF_TIMEOUT;
 238        u16 cmd;
 239
 240        iowrite16(val, ioaddr + MMWD);
 241        /* Write the command to the MDIO bus */
 242        iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
 243        /* Wait for the write bit to be cleared */
 244        while (limit--) {
 245                cmd = ioread16(ioaddr + MMDIO);
 246                if (!(cmd & MDIO_WRITE))
 247                        break;
 248        }
 249
 250        return (limit < 0) ? -ETIMEDOUT : 0;
 251}
 252
 253static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
 254{
 255        struct net_device *dev = bus->priv;
 256        struct r6040_private *lp = netdev_priv(dev);
 257        void __iomem *ioaddr = lp->base;
 258
 259        return r6040_phy_read(ioaddr, phy_addr, reg);
 260}
 261
 262static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
 263                                                int reg, u16 value)
 264{
 265        struct net_device *dev = bus->priv;
 266        struct r6040_private *lp = netdev_priv(dev);
 267        void __iomem *ioaddr = lp->base;
 268
 269        return r6040_phy_write(ioaddr, phy_addr, reg, value);
 270}
 271
 272static int r6040_mdiobus_reset(struct mii_bus *bus)
 273{
 274        return 0;
 275}
 276
 277static void r6040_free_txbufs(struct net_device *dev)
 278{
 279        struct r6040_private *lp = netdev_priv(dev);
 280        int i;
 281
 282        for (i = 0; i < TX_DCNT; i++) {
 283                if (lp->tx_insert_ptr->skb_ptr) {
 284                        pci_unmap_single(lp->pdev,
 285                                le32_to_cpu(lp->tx_insert_ptr->buf),
 286                                MAX_BUF_SIZE, PCI_DMA_TODEVICE);
 287                        dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
 288                        lp->tx_insert_ptr->skb_ptr = NULL;
 289                }
 290                lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
 291        }
 292}
 293
 294static void r6040_free_rxbufs(struct net_device *dev)
 295{
 296        struct r6040_private *lp = netdev_priv(dev);
 297        int i;
 298
 299        for (i = 0; i < RX_DCNT; i++) {
 300                if (lp->rx_insert_ptr->skb_ptr) {
 301                        pci_unmap_single(lp->pdev,
 302                                le32_to_cpu(lp->rx_insert_ptr->buf),
 303                                MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
 304                        dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
 305                        lp->rx_insert_ptr->skb_ptr = NULL;
 306                }
 307                lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
 308        }
 309}
 310
 311static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
 312                                 dma_addr_t desc_dma, int size)
 313{
 314        struct r6040_descriptor *desc = desc_ring;
 315        dma_addr_t mapping = desc_dma;
 316
 317        while (size-- > 0) {
 318                mapping += sizeof(*desc);
 319                desc->ndesc = cpu_to_le32(mapping);
 320                desc->vndescp = desc + 1;
 321                desc++;
 322        }
 323        desc--;
 324        desc->ndesc = cpu_to_le32(desc_dma);
 325        desc->vndescp = desc_ring;
 326}
 327
 328static void r6040_init_txbufs(struct net_device *dev)
 329{
 330        struct r6040_private *lp = netdev_priv(dev);
 331
 332        lp->tx_free_desc = TX_DCNT;
 333
 334        lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
 335        r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
 336}
 337
 338static int r6040_alloc_rxbufs(struct net_device *dev)
 339{
 340        struct r6040_private *lp = netdev_priv(dev);
 341        struct r6040_descriptor *desc;
 342        struct sk_buff *skb;
 343        int rc;
 344
 345        lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
 346        r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
 347
 348        /* Allocate skbs for the rx descriptors */
 349        desc = lp->rx_ring;
 350        do {
 351                skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
 352                if (!skb) {
 353                        rc = -ENOMEM;
 354                        goto err_exit;
 355                }
 356                desc->skb_ptr = skb;
 357                desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
 358                                        desc->skb_ptr->data,
 359                                        MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
 360                desc->status = DSC_OWNER_MAC;
 361                desc = desc->vndescp;
 362        } while (desc != lp->rx_ring);
 363
 364        return 0;
 365
 366err_exit:
 367        /* Deallocate all previously allocated skbs */
 368        r6040_free_rxbufs(dev);
 369        return rc;
 370}
 371
 372static void r6040_reset_mac(struct r6040_private *lp)
 373{
 374        void __iomem *ioaddr = lp->base;
 375        int limit = MAC_DEF_TIMEOUT;
 376        u16 cmd;
 377
 378        iowrite16(MAC_RST, ioaddr + MCR1);
 379        while (limit--) {
 380                cmd = ioread16(ioaddr + MCR1);
 381                if (cmd & MAC_RST)
 382                        break;
 383        }
 384
 385        /* Reset internal state machine */
 386        iowrite16(MAC_SM_RST, ioaddr + MAC_SM);
 387        iowrite16(0, ioaddr + MAC_SM);
 388        mdelay(5);
 389}
 390
 391static void r6040_init_mac_regs(struct net_device *dev)
 392{
 393        struct r6040_private *lp = netdev_priv(dev);
 394        void __iomem *ioaddr = lp->base;
 395
 396        /* Mask Off Interrupt */
 397        iowrite16(MSK_INT, ioaddr + MIER);
 398
 399        /* Reset RDC MAC */
 400        r6040_reset_mac(lp);
 401
 402        /* MAC Bus Control Register */
 403        iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
 404
 405        /* Buffer Size Register */
 406        iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
 407
 408        /* Write TX ring start address */
 409        iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
 410        iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
 411
 412        /* Write RX ring start address */
 413        iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
 414        iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
 415
 416        /* Set interrupt waiting time and packet numbers */
 417        iowrite16(0, ioaddr + MT_ICR);
 418        iowrite16(0, ioaddr + MR_ICR);
 419
 420        /* Enable interrupts */
 421        iowrite16(INT_MASK, ioaddr + MIER);
 422
 423        /* Enable TX and RX */
 424        iowrite16(lp->mcr0 | MCR0_RCVEN, ioaddr);
 425
 426        /* Let TX poll the descriptors
 427         * we may got called by r6040_tx_timeout which has left
 428         * some unsent tx buffers */
 429        iowrite16(TM2TX, ioaddr + MTPR);
 430}
 431
 432static void r6040_tx_timeout(struct net_device *dev)
 433{
 434        struct r6040_private *priv = netdev_priv(dev);
 435        void __iomem *ioaddr = priv->base;
 436
 437        netdev_warn(dev, "transmit timed out, int enable %4.4x "
 438                "status %4.4x\n",
 439                ioread16(ioaddr + MIER),
 440                ioread16(ioaddr + MISR));
 441
 442        dev->stats.tx_errors++;
 443
 444        /* Reset MAC and re-init all registers */
 445        r6040_init_mac_regs(dev);
 446}
 447
 448static struct net_device_stats *r6040_get_stats(struct net_device *dev)
 449{
 450        struct r6040_private *priv = netdev_priv(dev);
 451        void __iomem *ioaddr = priv->base;
 452        unsigned long flags;
 453
 454        spin_lock_irqsave(&priv->lock, flags);
 455        dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
 456        dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
 457        spin_unlock_irqrestore(&priv->lock, flags);
 458
 459        return &dev->stats;
 460}
 461
 462/* Stop RDC MAC and Free the allocated resource */
 463static void r6040_down(struct net_device *dev)
 464{
 465        struct r6040_private *lp = netdev_priv(dev);
 466        void __iomem *ioaddr = lp->base;
 467        u16 *adrp;
 468
 469        /* Stop MAC */
 470        iowrite16(MSK_INT, ioaddr + MIER);      /* Mask Off Interrupt */
 471
 472        /* Reset RDC MAC */
 473        r6040_reset_mac(lp);
 474
 475        /* Restore MAC Address to MIDx */
 476        adrp = (u16 *) dev->dev_addr;
 477        iowrite16(adrp[0], ioaddr + MID_0L);
 478        iowrite16(adrp[1], ioaddr + MID_0M);
 479        iowrite16(adrp[2], ioaddr + MID_0H);
 480
 481        phy_stop(lp->phydev);
 482}
 483
 484static int r6040_close(struct net_device *dev)
 485{
 486        struct r6040_private *lp = netdev_priv(dev);
 487        struct pci_dev *pdev = lp->pdev;
 488
 489        spin_lock_irq(&lp->lock);
 490        napi_disable(&lp->napi);
 491        netif_stop_queue(dev);
 492        r6040_down(dev);
 493
 494        free_irq(dev->irq, dev);
 495
 496        /* Free RX buffer */
 497        r6040_free_rxbufs(dev);
 498
 499        /* Free TX buffer */
 500        r6040_free_txbufs(dev);
 501
 502        spin_unlock_irq(&lp->lock);
 503
 504        /* Free Descriptor memory */
 505        if (lp->rx_ring) {
 506                pci_free_consistent(pdev,
 507                                RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
 508                lp->rx_ring = NULL;
 509        }
 510
 511        if (lp->tx_ring) {
 512                pci_free_consistent(pdev,
 513                                TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
 514                lp->tx_ring = NULL;
 515        }
 516
 517        return 0;
 518}
 519
 520static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 521{
 522        struct r6040_private *lp = netdev_priv(dev);
 523
 524        if (!lp->phydev)
 525                return -EINVAL;
 526
 527        return phy_mii_ioctl(lp->phydev, rq, cmd);
 528}
 529
 530static int r6040_rx(struct net_device *dev, int limit)
 531{
 532        struct r6040_private *priv = netdev_priv(dev);
 533        struct r6040_descriptor *descptr = priv->rx_remove_ptr;
 534        struct sk_buff *skb_ptr, *new_skb;
 535        int count = 0;
 536        u16 err;
 537
 538        /* Limit not reached and the descriptor belongs to the CPU */
 539        while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
 540                /* Read the descriptor status */
 541                err = descptr->status;
 542                /* Global error status set */
 543                if (err & DSC_RX_ERR) {
 544                        /* RX dribble */
 545                        if (err & DSC_RX_ERR_DRI)
 546                                dev->stats.rx_frame_errors++;
 547                        /* Buffer length exceeded */
 548                        if (err & DSC_RX_ERR_BUF)
 549                                dev->stats.rx_length_errors++;
 550                        /* Packet too long */
 551                        if (err & DSC_RX_ERR_LONG)
 552                                dev->stats.rx_length_errors++;
 553                        /* Packet < 64 bytes */
 554                        if (err & DSC_RX_ERR_RUNT)
 555                                dev->stats.rx_length_errors++;
 556                        /* CRC error */
 557                        if (err & DSC_RX_ERR_CRC) {
 558                                spin_lock(&priv->lock);
 559                                dev->stats.rx_crc_errors++;
 560                                spin_unlock(&priv->lock);
 561                        }
 562                        goto next_descr;
 563                }
 564
 565                /* Packet successfully received */
 566                new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
 567                if (!new_skb) {
 568                        dev->stats.rx_dropped++;
 569                        goto next_descr;
 570                }
 571                skb_ptr = descptr->skb_ptr;
 572                skb_ptr->dev = priv->dev;
 573
 574                /* Do not count the CRC */
 575                skb_put(skb_ptr, descptr->len - 4);
 576                pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
 577                                        MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
 578                skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
 579
 580                /* Send to upper layer */
 581                netif_receive_skb(skb_ptr);
 582                dev->stats.rx_packets++;
 583                dev->stats.rx_bytes += descptr->len - 4;
 584
 585                /* put new skb into descriptor */
 586                descptr->skb_ptr = new_skb;
 587                descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
 588                                                descptr->skb_ptr->data,
 589                                        MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
 590
 591next_descr:
 592                /* put the descriptor back to the MAC */
 593                descptr->status = DSC_OWNER_MAC;
 594                descptr = descptr->vndescp;
 595                count++;
 596        }
 597        priv->rx_remove_ptr = descptr;
 598
 599        return count;
 600}
 601
 602static void r6040_tx(struct net_device *dev)
 603{
 604        struct r6040_private *priv = netdev_priv(dev);
 605        struct r6040_descriptor *descptr;
 606        void __iomem *ioaddr = priv->base;
 607        struct sk_buff *skb_ptr;
 608        u16 err;
 609
 610        spin_lock(&priv->lock);
 611        descptr = priv->tx_remove_ptr;
 612        while (priv->tx_free_desc < TX_DCNT) {
 613                /* Check for errors */
 614                err = ioread16(ioaddr + MLSR);
 615
 616                if (err & TX_FIFO_UNDR)
 617                        dev->stats.tx_fifo_errors++;
 618                if (err & (TX_EXCEEDC | TX_LATEC))
 619                        dev->stats.tx_carrier_errors++;
 620
 621                if (descptr->status & DSC_OWNER_MAC)
 622                        break; /* Not complete */
 623                skb_ptr = descptr->skb_ptr;
 624                pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
 625                        skb_ptr->len, PCI_DMA_TODEVICE);
 626                /* Free buffer */
 627                dev_kfree_skb_irq(skb_ptr);
 628                descptr->skb_ptr = NULL;
 629                /* To next descriptor */
 630                descptr = descptr->vndescp;
 631                priv->tx_free_desc++;
 632        }
 633        priv->tx_remove_ptr = descptr;
 634
 635        if (priv->tx_free_desc)
 636                netif_wake_queue(dev);
 637        spin_unlock(&priv->lock);
 638}
 639
 640static int r6040_poll(struct napi_struct *napi, int budget)
 641{
 642        struct r6040_private *priv =
 643                container_of(napi, struct r6040_private, napi);
 644        struct net_device *dev = priv->dev;
 645        void __iomem *ioaddr = priv->base;
 646        int work_done;
 647
 648        work_done = r6040_rx(dev, budget);
 649
 650        if (work_done < budget) {
 651                napi_complete(napi);
 652                /* Enable RX interrupt */
 653                iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
 654        }
 655        return work_done;
 656}
 657
 658/* The RDC interrupt handler. */
 659static irqreturn_t r6040_interrupt(int irq, void *dev_id)
 660{
 661        struct net_device *dev = dev_id;
 662        struct r6040_private *lp = netdev_priv(dev);
 663        void __iomem *ioaddr = lp->base;
 664        u16 misr, status;
 665
 666        /* Save MIER */
 667        misr = ioread16(ioaddr + MIER);
 668        /* Mask off RDC MAC interrupt */
 669        iowrite16(MSK_INT, ioaddr + MIER);
 670        /* Read MISR status and clear */
 671        status = ioread16(ioaddr + MISR);
 672
 673        if (status == 0x0000 || status == 0xffff) {
 674                /* Restore RDC MAC interrupt */
 675                iowrite16(misr, ioaddr + MIER);
 676                return IRQ_NONE;
 677        }
 678
 679        /* RX interrupt request */
 680        if (status & RX_INTS) {
 681                if (status & RX_NO_DESC) {
 682                        /* RX descriptor unavailable */
 683                        dev->stats.rx_dropped++;
 684                        dev->stats.rx_missed_errors++;
 685                }
 686                if (status & RX_FIFO_FULL)
 687                        dev->stats.rx_fifo_errors++;
 688
 689                if (likely(napi_schedule_prep(&lp->napi))) {
 690                        /* Mask off RX interrupt */
 691                        misr &= ~RX_INTS;
 692                        __napi_schedule(&lp->napi);
 693                }
 694        }
 695
 696        /* TX interrupt request */
 697        if (status & TX_INTS)
 698                r6040_tx(dev);
 699
 700        /* Restore RDC MAC interrupt */
 701        iowrite16(misr, ioaddr + MIER);
 702
 703        return IRQ_HANDLED;
 704}
 705
 706#ifdef CONFIG_NET_POLL_CONTROLLER
 707static void r6040_poll_controller(struct net_device *dev)
 708{
 709        disable_irq(dev->irq);
 710        r6040_interrupt(dev->irq, dev);
 711        enable_irq(dev->irq);
 712}
 713#endif
 714
 715/* Init RDC MAC */
 716static int r6040_up(struct net_device *dev)
 717{
 718        struct r6040_private *lp = netdev_priv(dev);
 719        void __iomem *ioaddr = lp->base;
 720        int ret;
 721
 722        /* Initialise and alloc RX/TX buffers */
 723        r6040_init_txbufs(dev);
 724        ret = r6040_alloc_rxbufs(dev);
 725        if (ret)
 726                return ret;
 727
 728        /* improve performance (by RDC guys) */
 729        r6040_phy_write(ioaddr, 30, 17,
 730                        (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
 731        r6040_phy_write(ioaddr, 30, 17,
 732                        ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
 733        r6040_phy_write(ioaddr, 0, 19, 0x0000);
 734        r6040_phy_write(ioaddr, 0, 30, 0x01F0);
 735
 736        /* Initialize all MAC registers */
 737        r6040_init_mac_regs(dev);
 738
 739        phy_start(lp->phydev);
 740
 741        return 0;
 742}
 743
 744
 745/* Read/set MAC address routines */
 746static void r6040_mac_address(struct net_device *dev)
 747{
 748        struct r6040_private *lp = netdev_priv(dev);
 749        void __iomem *ioaddr = lp->base;
 750        u16 *adrp;
 751
 752        /* Reset MAC */
 753        r6040_reset_mac(lp);
 754
 755        /* Restore MAC Address */
 756        adrp = (u16 *) dev->dev_addr;
 757        iowrite16(adrp[0], ioaddr + MID_0L);
 758        iowrite16(adrp[1], ioaddr + MID_0M);
 759        iowrite16(adrp[2], ioaddr + MID_0H);
 760}
 761
 762static int r6040_open(struct net_device *dev)
 763{
 764        struct r6040_private *lp = netdev_priv(dev);
 765        int ret;
 766
 767        /* Request IRQ and Register interrupt handler */
 768        ret = request_irq(dev->irq, r6040_interrupt,
 769                IRQF_SHARED, dev->name, dev);
 770        if (ret)
 771                goto out;
 772
 773        /* Set MAC address */
 774        r6040_mac_address(dev);
 775
 776        /* Allocate Descriptor memory */
 777        lp->rx_ring =
 778                pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
 779        if (!lp->rx_ring) {
 780                ret = -ENOMEM;
 781                goto err_free_irq;
 782        }
 783
 784        lp->tx_ring =
 785                pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
 786        if (!lp->tx_ring) {
 787                ret = -ENOMEM;
 788                goto err_free_rx_ring;
 789        }
 790
 791        ret = r6040_up(dev);
 792        if (ret)
 793                goto err_free_tx_ring;
 794
 795        napi_enable(&lp->napi);
 796        netif_start_queue(dev);
 797
 798        return 0;
 799
 800err_free_tx_ring:
 801        pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
 802                        lp->tx_ring_dma);
 803err_free_rx_ring:
 804        pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
 805                        lp->rx_ring_dma);
 806err_free_irq:
 807        free_irq(dev->irq, dev);
 808out:
 809        return ret;
 810}
 811
 812static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
 813                                    struct net_device *dev)
 814{
 815        struct r6040_private *lp = netdev_priv(dev);
 816        struct r6040_descriptor *descptr;
 817        void __iomem *ioaddr = lp->base;
 818        unsigned long flags;
 819
 820        /* Critical Section */
 821        spin_lock_irqsave(&lp->lock, flags);
 822
 823        /* TX resource check */
 824        if (!lp->tx_free_desc) {
 825                spin_unlock_irqrestore(&lp->lock, flags);
 826                netif_stop_queue(dev);
 827                netdev_err(dev, ": no tx descriptor\n");
 828                return NETDEV_TX_BUSY;
 829        }
 830
 831        /* Statistic Counter */
 832        dev->stats.tx_packets++;
 833        dev->stats.tx_bytes += skb->len;
 834        /* Set TX descriptor & Transmit it */
 835        lp->tx_free_desc--;
 836        descptr = lp->tx_insert_ptr;
 837        if (skb->len < MISR)
 838                descptr->len = MISR;
 839        else
 840                descptr->len = skb->len;
 841
 842        descptr->skb_ptr = skb;
 843        descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
 844                skb->data, skb->len, PCI_DMA_TODEVICE));
 845        descptr->status = DSC_OWNER_MAC;
 846
 847        skb_tx_timestamp(skb);
 848
 849        /* Trigger the MAC to check the TX descriptor */
 850        iowrite16(TM2TX, ioaddr + MTPR);
 851        lp->tx_insert_ptr = descptr->vndescp;
 852
 853        /* If no tx resource, stop */
 854        if (!lp->tx_free_desc)
 855                netif_stop_queue(dev);
 856
 857        spin_unlock_irqrestore(&lp->lock, flags);
 858
 859        return NETDEV_TX_OK;
 860}
 861
 862static void r6040_multicast_list(struct net_device *dev)
 863{
 864        struct r6040_private *lp = netdev_priv(dev);
 865        void __iomem *ioaddr = lp->base;
 866        unsigned long flags;
 867        struct netdev_hw_addr *ha;
 868        int i;
 869        u16 *adrp;
 870        u16 hash_table[4] = { 0 };
 871
 872        spin_lock_irqsave(&lp->lock, flags);
 873
 874        /* Keep our MAC Address */
 875        adrp = (u16 *)dev->dev_addr;
 876        iowrite16(adrp[0], ioaddr + MID_0L);
 877        iowrite16(adrp[1], ioaddr + MID_0M);
 878        iowrite16(adrp[2], ioaddr + MID_0H);
 879
 880        /* Clear AMCP & PROM bits */
 881        lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
 882
 883        /* Promiscuous mode */
 884        if (dev->flags & IFF_PROMISC)
 885                lp->mcr0 |= MCR0_PROMISC;
 886
 887        /* Enable multicast hash table function to
 888         * receive all multicast packets. */
 889        else if (dev->flags & IFF_ALLMULTI) {
 890                lp->mcr0 |= MCR0_HASH_EN;
 891
 892                for (i = 0; i < MCAST_MAX ; i++) {
 893                        iowrite16(0, ioaddr + MID_1L + 8 * i);
 894                        iowrite16(0, ioaddr + MID_1M + 8 * i);
 895                        iowrite16(0, ioaddr + MID_1H + 8 * i);
 896                }
 897
 898                for (i = 0; i < 4; i++)
 899                        hash_table[i] = 0xffff;
 900        }
 901        /* Use internal multicast address registers if the number of
 902         * multicast addresses is not greater than MCAST_MAX. */
 903        else if (netdev_mc_count(dev) <= MCAST_MAX) {
 904                i = 0;
 905                netdev_for_each_mc_addr(ha, dev) {
 906                        u16 *adrp = (u16 *) ha->addr;
 907                        iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
 908                        iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
 909                        iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
 910                        i++;
 911                }
 912                while (i < MCAST_MAX) {
 913                        iowrite16(0, ioaddr + MID_1L + 8 * i);
 914                        iowrite16(0, ioaddr + MID_1M + 8 * i);
 915                        iowrite16(0, ioaddr + MID_1H + 8 * i);
 916                        i++;
 917                }
 918        }
 919        /* Otherwise, Enable multicast hash table function. */
 920        else {
 921                u32 crc;
 922
 923                lp->mcr0 |= MCR0_HASH_EN;
 924
 925                for (i = 0; i < MCAST_MAX ; i++) {
 926                        iowrite16(0, ioaddr + MID_1L + 8 * i);
 927                        iowrite16(0, ioaddr + MID_1M + 8 * i);
 928                        iowrite16(0, ioaddr + MID_1H + 8 * i);
 929                }
 930
 931                /* Build multicast hash table */
 932                netdev_for_each_mc_addr(ha, dev) {
 933                        u8 *addrs = ha->addr;
 934
 935                        crc = ether_crc(ETH_ALEN, addrs);
 936                        crc >>= 26;
 937                        hash_table[crc >> 4] |= 1 << (crc & 0xf);
 938                }
 939        }
 940
 941        iowrite16(lp->mcr0, ioaddr + MCR0);
 942
 943        /* Fill the MAC hash tables with their values */
 944        if (lp->mcr0 & MCR0_HASH_EN) {
 945                iowrite16(hash_table[0], ioaddr + MAR0);
 946                iowrite16(hash_table[1], ioaddr + MAR1);
 947                iowrite16(hash_table[2], ioaddr + MAR2);
 948                iowrite16(hash_table[3], ioaddr + MAR3);
 949        }
 950
 951        spin_unlock_irqrestore(&lp->lock, flags);
 952}
 953
 954static void netdev_get_drvinfo(struct net_device *dev,
 955                        struct ethtool_drvinfo *info)
 956{
 957        struct r6040_private *rp = netdev_priv(dev);
 958
 959        strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
 960        strlcpy(info->version, DRV_VERSION, sizeof(info->version));
 961        strlcpy(info->bus_info, pci_name(rp->pdev), sizeof(info->bus_info));
 962}
 963
 964static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 965{
 966        struct r6040_private *rp = netdev_priv(dev);
 967
 968        return  phy_ethtool_gset(rp->phydev, cmd);
 969}
 970
 971static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 972{
 973        struct r6040_private *rp = netdev_priv(dev);
 974
 975        return phy_ethtool_sset(rp->phydev, cmd);
 976}
 977
 978static const struct ethtool_ops netdev_ethtool_ops = {
 979        .get_drvinfo            = netdev_get_drvinfo,
 980        .get_settings           = netdev_get_settings,
 981        .set_settings           = netdev_set_settings,
 982        .get_link               = ethtool_op_get_link,
 983        .get_ts_info            = ethtool_op_get_ts_info,
 984};
 985
 986static const struct net_device_ops r6040_netdev_ops = {
 987        .ndo_open               = r6040_open,
 988        .ndo_stop               = r6040_close,
 989        .ndo_start_xmit         = r6040_start_xmit,
 990        .ndo_get_stats          = r6040_get_stats,
 991        .ndo_set_rx_mode        = r6040_multicast_list,
 992        .ndo_change_mtu         = eth_change_mtu,
 993        .ndo_validate_addr      = eth_validate_addr,
 994        .ndo_set_mac_address    = eth_mac_addr,
 995        .ndo_do_ioctl           = r6040_ioctl,
 996        .ndo_tx_timeout         = r6040_tx_timeout,
 997#ifdef CONFIG_NET_POLL_CONTROLLER
 998        .ndo_poll_controller    = r6040_poll_controller,
 999#endif
1000};

1001
1002static void r6040_adjust_link(struct net_device *dev)
1003{
1004        struct r6040_private *lp = netdev_priv(dev);
1005        struct phy_device *phydev = lp->phydev;
1006        int status_changed = 0;
1007        void __iomem *ioaddr = lp->base;
1008
1009        BUG_ON(!phydev);
1010
1011        if (lp->old_link != phydev->link) {
1012                status_changed = 1;
1013                lp->old_link = phydev->link;
1014        }
1015
1016        /* reflect duplex change */
1017        if (phydev->link && (lp->old_duplex != phydev->duplex)) {
1018                lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0);
1019                iowrite16(lp->mcr0, ioaddr);
1020
1021                status_changed = 1;
1022                lp->old_duplex = phydev->duplex;
1023        }
1024
1025        if (status_changed) {
1026                pr_info("%s: link %s", dev->name, phydev->link ?
1027                        "UP" : "DOWN");
1028                if (phydev->link)
1029                        pr_cont(" - %d/%s", phydev->speed,
1030                        DUPLEX_FULL == phydev->duplex ? "full" : "half");
1031                pr_cont("\n");
1032        }
1033}
1034
1035static int r6040_mii_probe(struct net_device *dev)
1036{
1037        struct r6040_private *lp = netdev_priv(dev);
1038        struct phy_device *phydev = NULL;
1039
1040        phydev = phy_find_first(lp->mii_bus);
1041        if (!phydev) {
1042                dev_err(&lp->pdev->dev, "no PHY found\n");
1043                return -ENODEV;
1044        }
1045
1046        phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link,
1047                             PHY_INTERFACE_MODE_MII);
1048
1049        if (IS_ERR(phydev)) {
1050                dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1051                return PTR_ERR(phydev);
1052        }
1053
1054        /* mask with MAC supported features */
1055        phydev->supported &= (SUPPORTED_10baseT_Half
1056                                | SUPPORTED_10baseT_Full
1057                                | SUPPORTED_100baseT_Half
1058                                | SUPPORTED_100baseT_Full
1059                                | SUPPORTED_Autoneg
1060                                | SUPPORTED_MII
1061                                | SUPPORTED_TP);
1062
1063        phydev->advertising = phydev->supported;
1064        lp->phydev = phydev;
1065        lp->old_link = 0;
1066        lp->old_duplex = -1;
1067
1068        dev_info(&lp->pdev->dev, "attached PHY driver [%s] "
1069                "(mii_bus:phy_addr=%s)\n",
1070                phydev->drv->name, dev_name(&phydev->dev));
1071
1072        return 0;
1073}
1074
1075static int r6040_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1076{
1077        struct net_device *dev;
1078        struct r6040_private *lp;
1079        void __iomem *ioaddr;
1080        int err, io_size = R6040_IO_SIZE;
1081        static int card_idx = -1;
1082        int bar = 0;
1083        u16 *adrp;
1084        int i;
1085
1086        pr_info("%s\n", version);
1087
1088        err = pci_enable_device(pdev);
1089        if (err)
1090                goto err_out;
1091
1092        /* this should always be supported */
1093        err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1094        if (err) {
1095                dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1096                                "not supported by the card\n");
1097                goto err_out_disable_dev;
1098        }
1099        err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1100        if (err) {
1101                dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1102                                "not supported by the card\n");
1103                goto err_out_disable_dev;
1104        }
1105
1106        /* IO Size check */
1107        if (pci_resource_len(pdev, bar) < io_size) {
1108                dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
1109                err = -EIO;
1110                goto err_out_disable_dev;
1111        }
1112
1113        pci_set_master(pdev);
1114
1115        dev = alloc_etherdev(sizeof(struct r6040_private));
1116        if (!dev) {
1117                err = -ENOMEM;
1118                goto err_out_disable_dev;
1119        }
1120        SET_NETDEV_DEV(dev, &pdev->dev);
1121        lp = netdev_priv(dev);
1122
1123        err = pci_request_regions(pdev, DRV_NAME);
1124
1125        if (err) {
1126                dev_err(&pdev->dev, "Failed to request PCI regions\n");
1127                goto err_out_free_dev;
1128        }
1129
1130        ioaddr = pci_iomap(pdev, bar, io_size);
1131        if (!ioaddr) {
1132                dev_err(&pdev->dev, "ioremap failed for device\n");
1133                err = -EIO;
1134                goto err_out_free_res;
1135        }
1136
1137        /* If PHY status change register is still set to zero it means the
1138         * bootloader didn't initialize it, so we set it to:
1139         * - enable phy status change
1140         * - enable all phy addresses
1141         * - set to lowest timer divider */
1142        if (ioread16(ioaddr + PHY_CC) == 0)
1143                iowrite16(SCEN | PHY_MAX_ADDR << PHYAD_SHIFT |
1144                                7 << TMRDIV_SHIFT, ioaddr + PHY_CC);
1145
1146        /* Init system & device */
1147        lp->base = ioaddr;
1148        dev->irq = pdev->irq;
1149
1150        spin_lock_init(&lp->lock);
1151        pci_set_drvdata(pdev, dev);
1152
1153        /* Set MAC address */
1154        card_idx++;
1155
1156        adrp = (u16 *)dev->dev_addr;
1157        adrp[0] = ioread16(ioaddr + MID_0L);
1158        adrp[1] = ioread16(ioaddr + MID_0M);
1159        adrp[2] = ioread16(ioaddr + MID_0H);
1160
1161        /* Some bootloader/BIOSes do not initialize
1162         * MAC address, warn about that */
1163        if (!(adrp[0] || adrp[1] || adrp[2])) {
1164                netdev_warn(dev, "MAC address not initialized, "
1165                                        "generating random\n");
1166                eth_hw_addr_random(dev);
1167        }
1168
1169        /* Link new device into r6040_root_dev */
1170        lp->pdev = pdev;
1171        lp->dev = dev;
1172
1173        /* Init RDC private data */
1174        lp->mcr0 = MCR0_XMTEN | MCR0_RCVEN;
1175
1176        /* The RDC-specific entries in the device structure. */
1177        dev->netdev_ops = &r6040_netdev_ops;
1178        dev->ethtool_ops = &netdev_ethtool_ops;
1179        dev->watchdog_timeo = TX_TIMEOUT;
1180
1181        netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1182
1183        lp->mii_bus = mdiobus_alloc();
1184        if (!lp->mii_bus) {
1185                dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
1186                err = -ENOMEM;
1187                goto err_out_unmap;
1188        }
1189
1190        lp->mii_bus->priv = dev;
1191        lp->mii_bus->read = r6040_mdiobus_read;
1192        lp->mii_bus->write = r6040_mdiobus_write;
1193        lp->mii_bus->reset = r6040_mdiobus_reset;
1194        lp->mii_bus->name = "r6040_eth_mii";
1195        snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1196                dev_name(&pdev->dev), card_idx);
1197        lp->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1198        if (!lp->mii_bus->irq) {
1199                err = -ENOMEM;
1200                goto err_out_mdio;
1201        }
1202
1203        for (i = 0; i < PHY_MAX_ADDR; i++)
1204                lp->mii_bus->irq[i] = PHY_POLL;
1205
1206        err = mdiobus_register(lp->mii_bus);
1207        if (err) {
1208                dev_err(&pdev->dev, "failed to register MII bus\n");
1209                goto err_out_mdio_irq;
1210        }
1211
1212        err = r6040_mii_probe(dev);
1213        if (err) {
1214                dev_err(&pdev->dev, "failed to probe MII bus\n");
1215                goto err_out_mdio_unregister;
1216        }
1217
1218        /* Register net device. After this dev->name assign */
1219        err = register_netdev(dev);
1220        if (err) {
1221                dev_err(&pdev->dev, "Failed to register net device\n");
1222                goto err_out_mdio_unregister;
1223        }
1224        return 0;
1225
1226err_out_mdio_unregister:
1227        mdiobus_unregister(lp->mii_bus);
1228err_out_mdio_irq:
1229        kfree(lp->mii_bus->irq);
1230err_out_mdio:
1231        mdiobus_free(lp->mii_bus);
1232err_out_unmap:
1233        netif_napi_del(&lp->napi);
1234        pci_set_drvdata(pdev, NULL);
1235        pci_iounmap(pdev, ioaddr);
1236err_out_free_res:
1237        pci_release_regions(pdev);
1238err_out_free_dev:
1239        free_netdev(dev);
1240err_out_disable_dev:
1241        pci_disable_device(pdev);
1242err_out:
1243        return err;
1244}
1245
1246static void r6040_remove_one(struct pci_dev *pdev)
1247{
1248        struct net_device *dev = pci_get_drvdata(pdev);
1249        struct r6040_private *lp = netdev_priv(dev);
1250
1251        unregister_netdev(dev);
1252        mdiobus_unregister(lp->mii_bus);
1253        kfree(lp->mii_bus->irq);
1254        mdiobus_free(lp->mii_bus);
1255        netif_napi_del(&lp->napi);
1256        pci_iounmap(pdev, lp->base);
1257        pci_release_regions(pdev);
1258        free_netdev(dev);
1259        pci_disable_device(pdev);
1260        pci_set_drvdata(pdev, NULL);
1261}
1262
1263
1264static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = {
1265        { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1266        { 0 }
1267};
1268MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1269
1270static struct pci_driver r6040_driver = {
1271        .name           = DRV_NAME,
1272        .id_table       = r6040_pci_tbl,
1273        .probe          = r6040_init_one,
1274        .remove         = r6040_remove_one,
1275};
1276
1277module_pci_driver(r6040_driver);
1278