1
2
3
4#include <linux/if_ether.h>
5#include <linux/types.h>
6
7
8struct rx_header {
9 ushort pad;
10 ushort rx_count;
11 ushort rx_status;
12 ushort cur_addr;
13};
14
15#define PAR_DATA 0
16#define PAR_STATUS 1
17#define PAR_CONTROL 2
18
19#define Ctrl_LNibRead 0x08
20#define Ctrl_HNibRead 0
21#define Ctrl_LNibWrite 0x08
22#define Ctrl_HNibWrite 0
23#define Ctrl_SelData 0x04
24#define Ctrl_IRQEN 0x10
25
26#define EOW 0xE0
27#define EOC 0xE0
28#define WrAddr 0x40
29#define RdAddr 0xC0
30#define HNib 0x10
31
32enum page0_regs
33{
34
35 PAR0 = 0, PAR1 = 1, PAR2 = 2, PAR3 = 3, PAR4 = 4, PAR5 = 5,
36 TxCNT0 = 6, TxCNT1 = 7,
37 TxSTAT = 8, RxSTAT = 9,
38 ISR = 10, IMR = 11,
39 CMR1 = 12,
40 CMR2 = 13,
41 MODSEL = 14,
42 MAR = 14,
43 CMR2_h = 0x1d, };
44
45enum eepage_regs
46{ PROM_CMD = 6, PROM_DATA = 7 };
47
48
49#define ISR_TxOK 0x01
50#define ISR_RxOK 0x04
51#define ISR_TxErr 0x02
52#define ISRh_RxErr 0x11
53
54#define CMR1h_MUX 0x08
55#define CMR1h_RESET 0x04
56#define CMR1h_RxENABLE 0x02
57#define CMR1h_TxENABLE 0x01
58#define CMR1h_TxRxOFF 0x00
59#define CMR1_ReXmit 0x08
60#define CMR1_Xmit 0x04
61#define CMR1_IRQ 0x02
62#define CMR1_BufEnb 0x01
63#define CMR1_NextPkt 0x01
64
65#define CMR2_NULL 8
66#define CMR2_IRQOUT 9
67#define CMR2_RAMTEST 10
68#define CMR2_EEPROM 12
69
70#define CMR2h_OFF 0
71#define CMR2h_Physical 1
72#define CMR2h_Normal 2
73#define CMR2h_PROMISC 3
74
75
76
77static inline unsigned char inbyte(unsigned short port)
78{
79 unsigned char _v;
80 __asm__ __volatile__ ("inb %w1,%b0" :"=a" (_v):"d" (port));
81 return _v;
82}
83
84
85
86static inline unsigned char read_nibble(short port, unsigned char offset)
87{
88 unsigned char retval;
89 outb(EOC+offset, port + PAR_DATA);
90 outb(RdAddr+offset, port + PAR_DATA);
91 inbyte(port + PAR_STATUS);
92 retval = inbyte(port + PAR_STATUS);
93 outb(EOC+offset, port + PAR_DATA);
94
95 return retval;
96}
97
98
99
100static inline unsigned char read_byte_mode0(short ioaddr)
101{
102 unsigned char low_nib;
103
104 outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
105 inbyte(ioaddr + PAR_STATUS);
106 low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
107 outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
108 inbyte(ioaddr + PAR_STATUS);
109 inbyte(ioaddr + PAR_STATUS);
110 return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
111}
112
113
114static inline unsigned char read_byte_mode2(short ioaddr)
115{
116 unsigned char low_nib;
117
118 outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
119 inbyte(ioaddr + PAR_STATUS);
120 low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
121 outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
122 inbyte(ioaddr + PAR_STATUS);
123 return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
124}
125
126
127static inline unsigned char read_byte_mode4(short ioaddr)
128{
129 unsigned char low_nib;
130
131 outb(RdAddr | MAR, ioaddr + PAR_DATA);
132 low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
133 outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
134 return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
135}
136
137
138static inline unsigned char read_byte_mode6(short ioaddr)
139{
140 unsigned char low_nib;
141
142 outb(RdAddr | MAR, ioaddr + PAR_DATA);
143 inbyte(ioaddr + PAR_STATUS);
144 low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
145 outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
146 inbyte(ioaddr + PAR_STATUS);
147 return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
148}
149
150static inline void
151write_reg(short port, unsigned char reg, unsigned char value)
152{
153 unsigned char outval;
154 outb(EOC | reg, port + PAR_DATA);
155 outval = WrAddr | reg;
156 outb(outval, port + PAR_DATA);
157 outb(outval, port + PAR_DATA);
158
159 outval &= 0xf0;
160 outval |= value;
161 outb(outval, port + PAR_DATA);
162 outval &= 0x1f;
163 outb(outval, port + PAR_DATA);
164 outb(outval, port + PAR_DATA);
165
166 outb(EOC | outval, port + PAR_DATA);
167}
168
169static inline void
170write_reg_high(short port, unsigned char reg, unsigned char value)
171{
172 unsigned char outval = EOC | HNib | reg;
173
174 outb(outval, port + PAR_DATA);
175 outval &= WrAddr | HNib | 0x0f;
176 outb(outval, port + PAR_DATA);
177 outb(outval, port + PAR_DATA);
178
179 outval = WrAddr | HNib | value;
180 outb(outval, port + PAR_DATA);
181 outval &= HNib | 0x0f;
182 outb(outval, port + PAR_DATA);
183 outb(outval, port + PAR_DATA);
184
185 outb(EOC | HNib | outval, port + PAR_DATA);
186}
187
188
189static inline void
190write_reg_byte(short port, unsigned char reg, unsigned char value)
191{
192 unsigned char outval;
193 outb(EOC | reg, port + PAR_DATA);
194 outval = WrAddr | reg;
195 outb(outval, port + PAR_DATA);
196 outb(outval, port + PAR_DATA);
197
198 outb((outval & 0xf0) | (value & 0x0f), port + PAR_DATA);
199 outb(value & 0x0f, port + PAR_DATA);
200 value >>= 4;
201 outb(value, port + PAR_DATA);
202 outb(0x10 | value, port + PAR_DATA);
203 outb(0x10 | value, port + PAR_DATA);
204
205 outb(EOC | value, port + PAR_DATA);
206}
207
208
209
210
211
212
213
214
215static inline void write_byte_mode0(short ioaddr, unsigned char value)
216{
217 outb(value & 0x0f, ioaddr + PAR_DATA);
218 outb((value>>4) | 0x10, ioaddr + PAR_DATA);
219}
220
221static inline void write_byte_mode1(short ioaddr, unsigned char value)
222{
223 outb(value & 0x0f, ioaddr + PAR_DATA);
224 outb(Ctrl_IRQEN | Ctrl_LNibWrite, ioaddr + PAR_CONTROL);
225 outb((value>>4) | 0x10, ioaddr + PAR_DATA);
226 outb(Ctrl_IRQEN | Ctrl_HNibWrite, ioaddr + PAR_CONTROL);
227}
228
229
230static inline void write_word_mode0(short ioaddr, unsigned short value)
231{
232 outb(value & 0x0f, ioaddr + PAR_DATA);
233 value >>= 4;
234 outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
235 value >>= 4;
236 outb(value & 0x0f, ioaddr + PAR_DATA);
237 value >>= 4;
238 outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
239}
240
241
242#define EE_SHIFT_CLK 0x04
243#define EE_CS 0x02
244#define EE_CLK_HIGH 0x12
245#define EE_CLK_LOW 0x16
246#define EE_DATA_WRITE 0x01
247#define EE_DATA_READ 0x08
248
249
250#define eeprom_delay(ticks) \
251do { int _i = 40; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)
252
253
254#define EE_WRITE_CMD(offset) (((5 << 6) + (offset)) << 17)
255#define EE_READ(offset) (((6 << 6) + (offset)) << 17)
256#define EE_ERASE(offset) (((7 << 6) + (offset)) << 17)
257#define EE_CMD_SIZE 27
258