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68
69#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
70
71#include <linux/module.h>
72#include <linux/kernel.h>
73#include <linux/types.h>
74#include <linux/compiler.h>
75#include <linux/slab.h>
76#include <linux/delay.h>
77#include <linux/init.h>
78#include <linux/interrupt.h>
79#include <linux/vmalloc.h>
80#include <linux/ioport.h>
81#include <linux/pci.h>
82#include <linux/mm.h>
83#include <linux/highmem.h>
84#include <linux/list.h>
85#include <linux/dma-mapping.h>
86
87#include <linux/netdevice.h>
88#include <linux/etherdevice.h>
89#include <linux/skbuff.h>
90#include <linux/ethtool.h>
91#include <linux/crc32.h>
92#include <linux/random.h>
93#include <linux/mii.h>
94#include <linux/ip.h>
95#include <linux/tcp.h>
96#include <linux/mutex.h>
97#include <linux/firmware.h>
98
99#include <net/checksum.h>
100
101#include <linux/atomic.h>
102#include <asm/io.h>
103#include <asm/byteorder.h>
104#include <asm/uaccess.h>
105
106#define cas_page_map(x) kmap_atomic((x))
107#define cas_page_unmap(x) kunmap_atomic((x))
108#define CAS_NCPUS num_online_cpus()
109
110#define cas_skb_release(x) netif_rx(x)
111
112
113#define USE_HP_WORKAROUND
114#define HP_WORKAROUND_DEFAULT
115#define CAS_HP_ALT_FIRMWARE cas_prog_null
116
117#include "cassini.h"
118
119#define USE_TX_COMPWB
120#define USE_CSMA_CD_PROTO
121#define USE_RX_BLANK
122#undef USE_ENTROPY_DEV
123
124
125
126
127#undef USE_PCI_INTB
128#undef USE_PCI_INTC
129#undef USE_PCI_INTD
130#undef USE_QOS
131
132#undef USE_VPD_DEBUG
133
134
135#define USE_PAGE_ORDER
136#define RX_DONT_BATCH 0
137#define RX_COPY_ALWAYS 0
138#define RX_COPY_MIN 64
139#undef RX_COUNT_BUFFERS
140
141#define DRV_MODULE_NAME "cassini"
142#define DRV_MODULE_VERSION "1.6"
143#define DRV_MODULE_RELDATE "21 May 2008"
144
145#define CAS_DEF_MSG_ENABLE \
146 (NETIF_MSG_DRV | \
147 NETIF_MSG_PROBE | \
148 NETIF_MSG_LINK | \
149 NETIF_MSG_TIMER | \
150 NETIF_MSG_IFDOWN | \
151 NETIF_MSG_IFUP | \
152 NETIF_MSG_RX_ERR | \
153 NETIF_MSG_TX_ERR)
154
155
156
157
158#define CAS_TX_TIMEOUT (HZ)
159#define CAS_LINK_TIMEOUT (22*HZ/10)
160#define CAS_LINK_FAST_TIMEOUT (1)
161
162
163
164
165#define STOP_TRIES_PHY 1000
166#define STOP_TRIES 5000
167
168
169
170
171
172#define CAS_MIN_FRAME 97
173#define CAS_1000MB_MIN_FRAME 255
174#define CAS_MIN_MTU 60
175#define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
176
177#if 1
178
179
180
181
182#else
183#define CAS_RESET_MTU 1
184#define CAS_RESET_ALL 2
185#define CAS_RESET_SPARE 3
186#endif
187
188static char version[] =
189 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
190
191static int cassini_debug = -1;
192static int link_mode;
193
194MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
195MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
196MODULE_LICENSE("GPL");
197MODULE_FIRMWARE("sun/cassini.bin");
198module_param(cassini_debug, int, 0);
199MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
200module_param(link_mode, int, 0);
201MODULE_PARM_DESC(link_mode, "default link mode");
202
203
204
205
206
207#define DEFAULT_LINKDOWN_TIMEOUT 5
208
209
210
211static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
212module_param(linkdown_timeout, int, 0);
213MODULE_PARM_DESC(linkdown_timeout,
214"min reset interval in sec. for PCS linkdown issue; disabled if not positive");
215
216
217
218
219
220
221static int link_transition_timeout;
222
223
224
225static u16 link_modes[] = {
226 BMCR_ANENABLE,
227 0,
228 BMCR_SPEED100,
229 BMCR_FULLDPLX,
230 BMCR_SPEED100|BMCR_FULLDPLX,
231 CAS_BMCR_SPEED1000|BMCR_FULLDPLX
232};
233
234static DEFINE_PCI_DEVICE_TABLE(cas_pci_tbl) = {
235 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
237 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
239 { 0, }
240};
241
242MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
243
244static void cas_set_link_modes(struct cas *cp);
245
246static inline void cas_lock_tx(struct cas *cp)
247{
248 int i;
249
250 for (i = 0; i < N_TX_RINGS; i++)
251 spin_lock(&cp->tx_lock[i]);
252}
253
254static inline void cas_lock_all(struct cas *cp)
255{
256 spin_lock_irq(&cp->lock);
257 cas_lock_tx(cp);
258}
259
260
261
262
263
264
265
266
267
268#define cas_lock_all_save(cp, flags) \
269do { \
270 struct cas *xxxcp = (cp); \
271 spin_lock_irqsave(&xxxcp->lock, flags); \
272 cas_lock_tx(xxxcp); \
273} while (0)
274
275static inline void cas_unlock_tx(struct cas *cp)
276{
277 int i;
278
279 for (i = N_TX_RINGS; i > 0; i--)
280 spin_unlock(&cp->tx_lock[i - 1]);
281}
282
283static inline void cas_unlock_all(struct cas *cp)
284{
285 cas_unlock_tx(cp);
286 spin_unlock_irq(&cp->lock);
287}
288
289#define cas_unlock_all_restore(cp, flags) \
290do { \
291 struct cas *xxxcp = (cp); \
292 cas_unlock_tx(xxxcp); \
293 spin_unlock_irqrestore(&xxxcp->lock, flags); \
294} while (0)
295
296static void cas_disable_irq(struct cas *cp, const int ring)
297{
298
299 if (ring == 0) {
300 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
301 return;
302 }
303
304
305 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
306 switch (ring) {
307#if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
308#ifdef USE_PCI_INTB
309 case 1:
310#endif
311#ifdef USE_PCI_INTC
312 case 2:
313#endif
314#ifdef USE_PCI_INTD
315 case 3:
316#endif
317 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
318 cp->regs + REG_PLUS_INTRN_MASK(ring));
319 break;
320#endif
321 default:
322 writel(INTRN_MASK_CLEAR_ALL, cp->regs +
323 REG_PLUS_INTRN_MASK(ring));
324 break;
325 }
326 }
327}
328
329static inline void cas_mask_intr(struct cas *cp)
330{
331 int i;
332
333 for (i = 0; i < N_RX_COMP_RINGS; i++)
334 cas_disable_irq(cp, i);
335}
336
337static void cas_enable_irq(struct cas *cp, const int ring)
338{
339 if (ring == 0) {
340 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
341 return;
342 }
343
344 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
345 switch (ring) {
346#if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
347#ifdef USE_PCI_INTB
348 case 1:
349#endif
350#ifdef USE_PCI_INTC
351 case 2:
352#endif
353#ifdef USE_PCI_INTD
354 case 3:
355#endif
356 writel(INTRN_MASK_RX_EN, cp->regs +
357 REG_PLUS_INTRN_MASK(ring));
358 break;
359#endif
360 default:
361 break;
362 }
363 }
364}
365
366static inline void cas_unmask_intr(struct cas *cp)
367{
368 int i;
369
370 for (i = 0; i < N_RX_COMP_RINGS; i++)
371 cas_enable_irq(cp, i);
372}
373
374static inline void cas_entropy_gather(struct cas *cp)
375{
376#ifdef USE_ENTROPY_DEV
377 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
378 return;
379
380 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
381 readl(cp->regs + REG_ENTROPY_IV),
382 sizeof(uint64_t)*8);
383#endif
384}
385
386static inline void cas_entropy_reset(struct cas *cp)
387{
388#ifdef USE_ENTROPY_DEV
389 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
390 return;
391
392 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
393 cp->regs + REG_BIM_LOCAL_DEV_EN);
394 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
395 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
396
397
398 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
399 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
400#endif
401}
402
403
404
405
406static u16 cas_phy_read(struct cas *cp, int reg)
407{
408 u32 cmd;
409 int limit = STOP_TRIES_PHY;
410
411 cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
412 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
413 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
414 cmd |= MIF_FRAME_TURN_AROUND_MSB;
415 writel(cmd, cp->regs + REG_MIF_FRAME);
416
417
418 while (limit-- > 0) {
419 udelay(10);
420 cmd = readl(cp->regs + REG_MIF_FRAME);
421 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
422 return cmd & MIF_FRAME_DATA_MASK;
423 }
424 return 0xFFFF;
425}
426
427static int cas_phy_write(struct cas *cp, int reg, u16 val)
428{
429 int limit = STOP_TRIES_PHY;
430 u32 cmd;
431
432 cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
433 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
434 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
435 cmd |= MIF_FRAME_TURN_AROUND_MSB;
436 cmd |= val & MIF_FRAME_DATA_MASK;
437 writel(cmd, cp->regs + REG_MIF_FRAME);
438
439
440 while (limit-- > 0) {
441 udelay(10);
442 cmd = readl(cp->regs + REG_MIF_FRAME);
443 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
444 return 0;
445 }
446 return -1;
447}
448
449static void cas_phy_powerup(struct cas *cp)
450{
451 u16 ctl = cas_phy_read(cp, MII_BMCR);
452
453 if ((ctl & BMCR_PDOWN) == 0)
454 return;
455 ctl &= ~BMCR_PDOWN;
456 cas_phy_write(cp, MII_BMCR, ctl);
457}
458
459static void cas_phy_powerdown(struct cas *cp)
460{
461 u16 ctl = cas_phy_read(cp, MII_BMCR);
462
463 if (ctl & BMCR_PDOWN)
464 return;
465 ctl |= BMCR_PDOWN;
466 cas_phy_write(cp, MII_BMCR, ctl);
467}
468
469
470static int cas_page_free(struct cas *cp, cas_page_t *page)
471{
472 pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
473 PCI_DMA_FROMDEVICE);
474 __free_pages(page->buffer, cp->page_order);
475 kfree(page);
476 return 0;
477}
478
479#ifdef RX_COUNT_BUFFERS
480#define RX_USED_ADD(x, y) ((x)->used += (y))
481#define RX_USED_SET(x, y) ((x)->used = (y))
482#else
483#define RX_USED_ADD(x, y)
484#define RX_USED_SET(x, y)
485#endif
486
487
488
489
490static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
491{
492 cas_page_t *page;
493
494 page = kmalloc(sizeof(cas_page_t), flags);
495 if (!page)
496 return NULL;
497
498 INIT_LIST_HEAD(&page->list);
499 RX_USED_SET(page, 0);
500 page->buffer = alloc_pages(flags, cp->page_order);
501 if (!page->buffer)
502 goto page_err;
503 page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
504 cp->page_size, PCI_DMA_FROMDEVICE);
505 return page;
506
507page_err:
508 kfree(page);
509 return NULL;
510}
511
512
513static void cas_spare_init(struct cas *cp)
514{
515 spin_lock(&cp->rx_inuse_lock);
516 INIT_LIST_HEAD(&cp->rx_inuse_list);
517 spin_unlock(&cp->rx_inuse_lock);
518
519 spin_lock(&cp->rx_spare_lock);
520 INIT_LIST_HEAD(&cp->rx_spare_list);
521 cp->rx_spares_needed = RX_SPARE_COUNT;
522 spin_unlock(&cp->rx_spare_lock);
523}
524
525
526static void cas_spare_free(struct cas *cp)
527{
528 struct list_head list, *elem, *tmp;
529
530
531 INIT_LIST_HEAD(&list);
532 spin_lock(&cp->rx_spare_lock);
533 list_splice_init(&cp->rx_spare_list, &list);
534 spin_unlock(&cp->rx_spare_lock);
535 list_for_each_safe(elem, tmp, &list) {
536 cas_page_free(cp, list_entry(elem, cas_page_t, list));
537 }
538
539 INIT_LIST_HEAD(&list);
540#if 1
541
542
543
544
545 spin_lock(&cp->rx_inuse_lock);
546 list_splice_init(&cp->rx_inuse_list, &list);
547 spin_unlock(&cp->rx_inuse_lock);
548#else
549 spin_lock(&cp->rx_spare_lock);
550 list_splice_init(&cp->rx_inuse_list, &list);
551 spin_unlock(&cp->rx_spare_lock);
552#endif
553 list_for_each_safe(elem, tmp, &list) {
554 cas_page_free(cp, list_entry(elem, cas_page_t, list));
555 }
556}
557
558
559static void cas_spare_recover(struct cas *cp, const gfp_t flags)
560{
561 struct list_head list, *elem, *tmp;
562 int needed, i;
563
564
565
566
567
568
569 INIT_LIST_HEAD(&list);
570 spin_lock(&cp->rx_inuse_lock);
571 list_splice_init(&cp->rx_inuse_list, &list);
572 spin_unlock(&cp->rx_inuse_lock);
573
574 list_for_each_safe(elem, tmp, &list) {
575 cas_page_t *page = list_entry(elem, cas_page_t, list);
576
577
578
579
580
581
582
583
584
585
586
587
588
589 if (page_count(page->buffer) > 1)
590 continue;
591
592 list_del(elem);
593 spin_lock(&cp->rx_spare_lock);
594 if (cp->rx_spares_needed > 0) {
595 list_add(elem, &cp->rx_spare_list);
596 cp->rx_spares_needed--;
597 spin_unlock(&cp->rx_spare_lock);
598 } else {
599 spin_unlock(&cp->rx_spare_lock);
600 cas_page_free(cp, page);
601 }
602 }
603
604
605 if (!list_empty(&list)) {
606 spin_lock(&cp->rx_inuse_lock);
607 list_splice(&list, &cp->rx_inuse_list);
608 spin_unlock(&cp->rx_inuse_lock);
609 }
610
611 spin_lock(&cp->rx_spare_lock);
612 needed = cp->rx_spares_needed;
613 spin_unlock(&cp->rx_spare_lock);
614 if (!needed)
615 return;
616
617
618 INIT_LIST_HEAD(&list);
619 i = 0;
620 while (i < needed) {
621 cas_page_t *spare = cas_page_alloc(cp, flags);
622 if (!spare)
623 break;
624 list_add(&spare->list, &list);
625 i++;
626 }
627
628 spin_lock(&cp->rx_spare_lock);
629 list_splice(&list, &cp->rx_spare_list);
630 cp->rx_spares_needed -= i;
631 spin_unlock(&cp->rx_spare_lock);
632}
633
634
635static cas_page_t *cas_page_dequeue(struct cas *cp)
636{
637 struct list_head *entry;
638 int recover;
639
640 spin_lock(&cp->rx_spare_lock);
641 if (list_empty(&cp->rx_spare_list)) {
642
643 spin_unlock(&cp->rx_spare_lock);
644 cas_spare_recover(cp, GFP_ATOMIC);
645 spin_lock(&cp->rx_spare_lock);
646 if (list_empty(&cp->rx_spare_list)) {
647 netif_err(cp, rx_err, cp->dev,
648 "no spare buffers available\n");
649 spin_unlock(&cp->rx_spare_lock);
650 return NULL;
651 }
652 }
653
654 entry = cp->rx_spare_list.next;
655 list_del(entry);
656 recover = ++cp->rx_spares_needed;
657 spin_unlock(&cp->rx_spare_lock);
658
659
660 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
661#if 1
662 atomic_inc(&cp->reset_task_pending);
663 atomic_inc(&cp->reset_task_pending_spare);
664 schedule_work(&cp->reset_task);
665#else
666 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
667 schedule_work(&cp->reset_task);
668#endif
669 }
670 return list_entry(entry, cas_page_t, list);
671}
672
673
674static void cas_mif_poll(struct cas *cp, const int enable)
675{
676 u32 cfg;
677
678 cfg = readl(cp->regs + REG_MIF_CFG);
679 cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
680
681 if (cp->phy_type & CAS_PHY_MII_MDIO1)
682 cfg |= MIF_CFG_PHY_SELECT;
683
684
685 if (enable) {
686 cfg |= MIF_CFG_POLL_EN;
687 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
688 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
689 }
690 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
691 cp->regs + REG_MIF_MASK);
692 writel(cfg, cp->regs + REG_MIF_CFG);
693}
694
695
696static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
697{
698 u16 ctl;
699#if 1
700 int lcntl;
701 int changed = 0;
702 int oldstate = cp->lstate;
703 int link_was_not_down = !(oldstate == link_down);
704#endif
705
706 if (!ep)
707 goto start_aneg;
708 lcntl = cp->link_cntl;
709 if (ep->autoneg == AUTONEG_ENABLE)
710 cp->link_cntl = BMCR_ANENABLE;
711 else {
712 u32 speed = ethtool_cmd_speed(ep);
713 cp->link_cntl = 0;
714 if (speed == SPEED_100)
715 cp->link_cntl |= BMCR_SPEED100;
716 else if (speed == SPEED_1000)
717 cp->link_cntl |= CAS_BMCR_SPEED1000;
718 if (ep->duplex == DUPLEX_FULL)
719 cp->link_cntl |= BMCR_FULLDPLX;
720 }
721#if 1
722 changed = (lcntl != cp->link_cntl);
723#endif
724start_aneg:
725 if (cp->lstate == link_up) {
726 netdev_info(cp->dev, "PCS link down\n");
727 } else {
728 if (changed) {
729 netdev_info(cp->dev, "link configuration changed\n");
730 }
731 }
732 cp->lstate = link_down;
733 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
734 if (!cp->hw_running)
735 return;
736#if 1
737
738
739
740
741
742 if (oldstate == link_up)
743 netif_carrier_off(cp->dev);
744 if (changed && link_was_not_down) {
745
746
747
748
749
750 atomic_inc(&cp->reset_task_pending);
751 atomic_inc(&cp->reset_task_pending_all);
752 schedule_work(&cp->reset_task);
753 cp->timer_ticks = 0;
754 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
755 return;
756 }
757#endif
758 if (cp->phy_type & CAS_PHY_SERDES) {
759 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
760
761 if (cp->link_cntl & BMCR_ANENABLE) {
762 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
763 cp->lstate = link_aneg;
764 } else {
765 if (cp->link_cntl & BMCR_FULLDPLX)
766 val |= PCS_MII_CTRL_DUPLEX;
767 val &= ~PCS_MII_AUTONEG_EN;
768 cp->lstate = link_force_ok;
769 }
770 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
771 writel(val, cp->regs + REG_PCS_MII_CTRL);
772
773 } else {
774 cas_mif_poll(cp, 0);
775 ctl = cas_phy_read(cp, MII_BMCR);
776 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
777 CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
778 ctl |= cp->link_cntl;
779 if (ctl & BMCR_ANENABLE) {
780 ctl |= BMCR_ANRESTART;
781 cp->lstate = link_aneg;
782 } else {
783 cp->lstate = link_force_ok;
784 }
785 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
786 cas_phy_write(cp, MII_BMCR, ctl);
787 cas_mif_poll(cp, 1);
788 }
789
790 cp->timer_ticks = 0;
791 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
792}
793
794
795static int cas_reset_mii_phy(struct cas *cp)
796{
797 int limit = STOP_TRIES_PHY;
798 u16 val;
799
800 cas_phy_write(cp, MII_BMCR, BMCR_RESET);
801 udelay(100);
802 while (--limit) {
803 val = cas_phy_read(cp, MII_BMCR);
804 if ((val & BMCR_RESET) == 0)
805 break;
806 udelay(10);
807 }
808 return limit <= 0;
809}
810
811static int cas_saturn_firmware_init(struct cas *cp)
812{
813 const struct firmware *fw;
814 const char fw_name[] = "sun/cassini.bin";
815 int err;
816
817 if (PHY_NS_DP83065 != cp->phy_id)
818 return 0;
819
820 err = request_firmware(&fw, fw_name, &cp->pdev->dev);
821 if (err) {
822 pr_err("Failed to load firmware \"%s\"\n",
823 fw_name);
824 return err;
825 }
826 if (fw->size < 2) {
827 pr_err("bogus length %zu in \"%s\"\n",
828 fw->size, fw_name);
829 err = -EINVAL;
830 goto out;
831 }
832 cp->fw_load_addr= fw->data[1] << 8 | fw->data[0];
833 cp->fw_size = fw->size - 2;
834 cp->fw_data = vmalloc(cp->fw_size);
835 if (!cp->fw_data) {
836 err = -ENOMEM;
837 goto out;
838 }
839 memcpy(cp->fw_data, &fw->data[2], cp->fw_size);
840out:
841 release_firmware(fw);
842 return err;
843}
844
845static void cas_saturn_firmware_load(struct cas *cp)
846{
847 int i;
848
849 cas_phy_powerdown(cp);
850
851
852 cas_phy_write(cp, DP83065_MII_MEM, 0x0);
853
854
855 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
856 cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
857 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
858 cas_phy_write(cp, DP83065_MII_REGD, 0x82);
859 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
860 cas_phy_write(cp, DP83065_MII_REGD, 0x0);
861 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
862 cas_phy_write(cp, DP83065_MII_REGD, 0x39);
863
864
865 cas_phy_write(cp, DP83065_MII_MEM, 0x1);
866 cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr);
867 for (i = 0; i < cp->fw_size; i++)
868 cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]);
869
870
871 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
872 cas_phy_write(cp, DP83065_MII_REGD, 0x1);
873}
874
875
876
877static void cas_phy_init(struct cas *cp)
878{
879 u16 val;
880
881
882 if (CAS_PHY_MII(cp->phy_type)) {
883 writel(PCS_DATAPATH_MODE_MII,
884 cp->regs + REG_PCS_DATAPATH_MODE);
885
886 cas_mif_poll(cp, 0);
887 cas_reset_mii_phy(cp);
888
889 if (PHY_LUCENT_B0 == cp->phy_id) {
890
891 cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
892 cas_phy_write(cp, MII_BMCR, 0x00f1);
893 cas_phy_write(cp, LUCENT_MII_REG, 0x0);
894
895 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
896
897 cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
898 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
899 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
900 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
901 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
902 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
903 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
904 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
905 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
906 cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
907 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
908
909 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
910 val = cas_phy_read(cp, BROADCOM_MII_REG4);
911 val = cas_phy_read(cp, BROADCOM_MII_REG4);
912 if (val & 0x0080) {
913
914 cas_phy_write(cp, BROADCOM_MII_REG4,
915 val & ~0x0080);
916 }
917
918 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
919 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
920 SATURN_PCFG_FSI : 0x0,
921 cp->regs + REG_SATURN_PCFG);
922
923
924
925
926
927 if (PHY_NS_DP83065 == cp->phy_id) {
928 cas_saturn_firmware_load(cp);
929 }
930 cas_phy_powerup(cp);
931 }
932
933
934 val = cas_phy_read(cp, MII_BMCR);
935 val &= ~BMCR_ANENABLE;
936 cas_phy_write(cp, MII_BMCR, val);
937 udelay(10);
938
939 cas_phy_write(cp, MII_ADVERTISE,
940 cas_phy_read(cp, MII_ADVERTISE) |
941 (ADVERTISE_10HALF | ADVERTISE_10FULL |
942 ADVERTISE_100HALF | ADVERTISE_100FULL |
943 CAS_ADVERTISE_PAUSE |
944 CAS_ADVERTISE_ASYM_PAUSE));
945
946 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
947
948
949
950 val = cas_phy_read(cp, CAS_MII_1000_CTRL);
951 val &= ~CAS_ADVERTISE_1000HALF;
952 val |= CAS_ADVERTISE_1000FULL;
953 cas_phy_write(cp, CAS_MII_1000_CTRL, val);
954 }
955
956 } else {
957
958 u32 val;
959 int limit;
960
961 writel(PCS_DATAPATH_MODE_SERDES,
962 cp->regs + REG_PCS_DATAPATH_MODE);
963
964
965 if (cp->cas_flags & CAS_FLAG_SATURN)
966 writel(0, cp->regs + REG_SATURN_PCFG);
967
968
969 val = readl(cp->regs + REG_PCS_MII_CTRL);
970 val |= PCS_MII_RESET;
971 writel(val, cp->regs + REG_PCS_MII_CTRL);
972
973 limit = STOP_TRIES;
974 while (--limit > 0) {
975 udelay(10);
976 if ((readl(cp->regs + REG_PCS_MII_CTRL) &
977 PCS_MII_RESET) == 0)
978 break;
979 }
980 if (limit <= 0)
981 netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n",
982 readl(cp->regs + REG_PCS_STATE_MACHINE));
983
984
985
986
987 writel(0x0, cp->regs + REG_PCS_CFG);
988
989
990 val = readl(cp->regs + REG_PCS_MII_ADVERT);
991 val &= ~PCS_MII_ADVERT_HD;
992 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
993 PCS_MII_ADVERT_ASYM_PAUSE);
994 writel(val, cp->regs + REG_PCS_MII_ADVERT);
995
996
997 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
998
999
1000 writel(PCS_SERDES_CTRL_SYNCD_EN,
1001 cp->regs + REG_PCS_SERDES_CTRL);
1002 }
1003}
1004
1005
1006static int cas_pcs_link_check(struct cas *cp)
1007{
1008 u32 stat, state_machine;
1009 int retval = 0;
1010
1011
1012
1013
1014
1015 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1016 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
1017 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1018
1019
1020
1021
1022 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
1023 PCS_MII_STATUS_REMOTE_FAULT)) ==
1024 (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT))
1025 netif_info(cp, link, cp->dev, "PCS RemoteFault\n");
1026
1027
1028
1029
1030 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1031 if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1032 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1033 } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1034 stat |= PCS_MII_STATUS_LINK_STATUS;
1035 }
1036
1037 if (stat & PCS_MII_STATUS_LINK_STATUS) {
1038 if (cp->lstate != link_up) {
1039 if (cp->opened) {
1040 cp->lstate = link_up;
1041 cp->link_transition = LINK_TRANSITION_LINK_UP;
1042
1043 cas_set_link_modes(cp);
1044 netif_carrier_on(cp->dev);
1045 }
1046 }
1047 } else if (cp->lstate == link_up) {
1048 cp->lstate = link_down;
1049 if (link_transition_timeout != 0 &&
1050 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1051 !cp->link_transition_jiffies_valid) {
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064 retval = 1;
1065 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1066 cp->link_transition_jiffies = jiffies;
1067 cp->link_transition_jiffies_valid = 1;
1068 } else {
1069 cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1070 }
1071 netif_carrier_off(cp->dev);
1072 if (cp->opened)
1073 netif_info(cp, link, cp->dev, "PCS link down\n");
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1084
1085 stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1086 if (stat == 0x03)
1087 return 1;
1088 }
1089 } else if (cp->lstate == link_down) {
1090 if (link_transition_timeout != 0 &&
1091 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1092 !cp->link_transition_jiffies_valid) {
1093
1094
1095
1096
1097
1098 retval = 1;
1099 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1100 cp->link_transition_jiffies = jiffies;
1101 cp->link_transition_jiffies_valid = 1;
1102 } else {
1103 cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1104 }
1105 }
1106
1107 return retval;
1108}
1109
1110static int cas_pcs_interrupt(struct net_device *dev,
1111 struct cas *cp, u32 status)
1112{
1113 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1114
1115 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1116 return 0;
1117 return cas_pcs_link_check(cp);
1118}
1119
1120static int cas_txmac_interrupt(struct net_device *dev,
1121 struct cas *cp, u32 status)
1122{
1123 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1124
1125 if (!txmac_stat)
1126 return 0;
1127
1128 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1129 "txmac interrupt, txmac_stat: 0x%x\n", txmac_stat);
1130
1131
1132
1133
1134 if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1135 !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1136 return 0;
1137
1138 spin_lock(&cp->stat_lock[0]);
1139 if (txmac_stat & MAC_TX_UNDERRUN) {
1140 netdev_err(dev, "TX MAC xmit underrun\n");
1141 cp->net_stats[0].tx_fifo_errors++;
1142 }
1143
1144 if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1145 netdev_err(dev, "TX MAC max packet size error\n");
1146 cp->net_stats[0].tx_errors++;
1147 }
1148
1149
1150
1151
1152 if (txmac_stat & MAC_TX_COLL_NORMAL)
1153 cp->net_stats[0].collisions += 0x10000;
1154
1155 if (txmac_stat & MAC_TX_COLL_EXCESS) {
1156 cp->net_stats[0].tx_aborted_errors += 0x10000;
1157 cp->net_stats[0].collisions += 0x10000;
1158 }
1159
1160 if (txmac_stat & MAC_TX_COLL_LATE) {
1161 cp->net_stats[0].tx_aborted_errors += 0x10000;
1162 cp->net_stats[0].collisions += 0x10000;
1163 }
1164 spin_unlock(&cp->stat_lock[0]);
1165
1166
1167
1168
1169 return 0;
1170}
1171
1172static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1173{
1174 cas_hp_inst_t *inst;
1175 u32 val;
1176 int i;
1177
1178 i = 0;
1179 while ((inst = firmware) && inst->note) {
1180 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1181
1182 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1183 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1184 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1185
1186 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1187 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1188 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1189 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1190 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1191 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1192 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1193 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1194
1195 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1196 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1197 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1198 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1199 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1200 ++firmware;
1201 ++i;
1202 }
1203}
1204
1205static void cas_init_rx_dma(struct cas *cp)
1206{
1207 u64 desc_dma = cp->block_dvma;
1208 u32 val;
1209 int i, size;
1210
1211
1212 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1213 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1214 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1215 if ((N_RX_DESC_RINGS > 1) &&
1216 (cp->cas_flags & CAS_FLAG_REG_PLUS))
1217 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1218 writel(val, cp->regs + REG_RX_CFG);
1219
1220 val = (unsigned long) cp->init_rxds[0] -
1221 (unsigned long) cp->init_block;
1222 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1223 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1224 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1225
1226 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1227
1228
1229
1230 val = (unsigned long) cp->init_rxds[1] -
1231 (unsigned long) cp->init_block;
1232 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1233 writel((desc_dma + val) & 0xffffffff, cp->regs +
1234 REG_PLUS_RX_DB1_LOW);
1235 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1236 REG_PLUS_RX_KICK1);
1237 }
1238
1239
1240 val = (unsigned long) cp->init_rxcs[0] -
1241 (unsigned long) cp->init_block;
1242 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1243 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1244
1245 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1246
1247 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1248 val = (unsigned long) cp->init_rxcs[i] -
1249 (unsigned long) cp->init_block;
1250 writel((desc_dma + val) >> 32, cp->regs +
1251 REG_PLUS_RX_CBN_HI(i));
1252 writel((desc_dma + val) & 0xffffffff, cp->regs +
1253 REG_PLUS_RX_CBN_LOW(i));
1254 }
1255 }
1256
1257
1258
1259
1260
1261 readl(cp->regs + REG_INTR_STATUS_ALIAS);
1262 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1263 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1264 for (i = 1; i < N_RX_COMP_RINGS; i++)
1265 readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1266
1267
1268 if (N_RX_COMP_RINGS > 1)
1269 writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1270 cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1271
1272 for (i = 2; i < N_RX_COMP_RINGS; i++)
1273 writel(INTR_RX_DONE_ALT,
1274 cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1275 }
1276
1277
1278 val = CAS_BASE(RX_PAUSE_THRESH_OFF,
1279 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1280 val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1281 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1282 writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1283
1284
1285 for (i = 0; i < 64; i++) {
1286 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1287 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1288 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1289 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1290 }
1291
1292
1293 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1294 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1295
1296
1297#ifdef USE_RX_BLANK
1298 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1299 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1300 writel(val, cp->regs + REG_RX_BLANK);
1301#else
1302 writel(0x0, cp->regs + REG_RX_BLANK);
1303#endif
1304
1305
1306
1307
1308
1309
1310
1311 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1312 writel(val, cp->regs + REG_RX_AE_THRESH);
1313 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1314 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1315 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1316 }
1317
1318
1319
1320
1321 writel(0x0, cp->regs + REG_RX_RED);
1322
1323
1324 val = 0;
1325 if (cp->page_size == 0x1000)
1326 val = 0x1;
1327 else if (cp->page_size == 0x2000)
1328 val = 0x2;
1329 else if (cp->page_size == 0x4000)
1330 val = 0x3;
1331
1332
1333 size = cp->dev->mtu + 64;
1334 if (size > cp->page_size)
1335 size = cp->page_size;
1336
1337 if (size <= 0x400)
1338 i = 0x0;
1339 else if (size <= 0x800)
1340 i = 0x1;
1341 else if (size <= 0x1000)
1342 i = 0x2;
1343 else
1344 i = 0x3;
1345
1346 cp->mtu_stride = 1 << (i + 10);
1347 val = CAS_BASE(RX_PAGE_SIZE, val);
1348 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1349 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1350 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1351 writel(val, cp->regs + REG_RX_PAGE_SIZE);
1352
1353
1354 if (CAS_HP_FIRMWARE == cas_prog_null)
1355 return;
1356
1357 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1358 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1359 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1360 writel(val, cp->regs + REG_HP_CFG);
1361}
1362
1363static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1364{
1365 memset(rxc, 0, sizeof(*rxc));
1366 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1367}
1368
1369
1370
1371
1372
1373static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1374{
1375 cas_page_t *page = cp->rx_pages[1][index];
1376 cas_page_t *new;
1377
1378 if (page_count(page->buffer) == 1)
1379 return page;
1380
1381 new = cas_page_dequeue(cp);
1382 if (new) {
1383 spin_lock(&cp->rx_inuse_lock);
1384 list_add(&page->list, &cp->rx_inuse_list);
1385 spin_unlock(&cp->rx_inuse_lock);
1386 }
1387 return new;
1388}
1389
1390
1391static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1392 const int index)
1393{
1394 cas_page_t **page0 = cp->rx_pages[0];
1395 cas_page_t **page1 = cp->rx_pages[1];
1396
1397
1398 if (page_count(page0[index]->buffer) > 1) {
1399 cas_page_t *new = cas_page_spare(cp, index);
1400 if (new) {
1401 page1[index] = page0[index];
1402 page0[index] = new;
1403 }
1404 }
1405 RX_USED_SET(page0[index], 0);
1406 return page0[index];
1407}
1408
1409static void cas_clean_rxds(struct cas *cp)
1410{
1411
1412 struct cas_rx_desc *rxd = cp->init_rxds[0];
1413 int i, size;
1414
1415
1416 for (i = 0; i < N_RX_FLOWS; i++) {
1417 struct sk_buff *skb;
1418 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1419 cas_skb_release(skb);
1420 }
1421 }
1422
1423
1424 size = RX_DESC_RINGN_SIZE(0);
1425 for (i = 0; i < size; i++) {
1426 cas_page_t *page = cas_page_swap(cp, 0, i);
1427 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1428 rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1429 CAS_BASE(RX_INDEX_RING, 0));
1430 }
1431
1432 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4;
1433 cp->rx_last[0] = 0;
1434 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1435}
1436
1437static void cas_clean_rxcs(struct cas *cp)
1438{
1439 int i, j;
1440
1441
1442 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1443 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1444 for (i = 0; i < N_RX_COMP_RINGS; i++) {
1445 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1446 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1447 cas_rxc_init(rxc + j);
1448 }
1449 }
1450}
1451
1452#if 0
1453
1454
1455
1456
1457
1458
1459static int cas_rxmac_reset(struct cas *cp)
1460{
1461 struct net_device *dev = cp->dev;
1462 int limit;
1463 u32 val;
1464
1465
1466 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1467 for (limit = 0; limit < STOP_TRIES; limit++) {
1468 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1469 break;
1470 udelay(10);
1471 }
1472 if (limit == STOP_TRIES) {
1473 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
1474 return 1;
1475 }
1476
1477
1478 writel(0, cp->regs + REG_RX_CFG);
1479 for (limit = 0; limit < STOP_TRIES; limit++) {
1480 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1481 break;
1482 udelay(10);
1483 }
1484 if (limit == STOP_TRIES) {
1485 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
1486 return 1;
1487 }
1488
1489 mdelay(5);
1490
1491
1492 writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1493 for (limit = 0; limit < STOP_TRIES; limit++) {
1494 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1495 break;
1496 udelay(10);
1497 }
1498 if (limit == STOP_TRIES) {
1499 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
1500 return 1;
1501 }
1502
1503
1504 cas_clean_rxds(cp);
1505 cas_clean_rxcs(cp);
1506
1507
1508 cas_init_rx_dma(cp);
1509
1510
1511 val = readl(cp->regs + REG_RX_CFG);
1512 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1513 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1514 val = readl(cp->regs + REG_MAC_RX_CFG);
1515 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1516 return 0;
1517}
1518#endif
1519
1520static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1521 u32 status)
1522{
1523 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1524
1525 if (!stat)
1526 return 0;
1527
1528 netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat);
1529
1530
1531 spin_lock(&cp->stat_lock[0]);
1532 if (stat & MAC_RX_ALIGN_ERR)
1533 cp->net_stats[0].rx_frame_errors += 0x10000;
1534
1535 if (stat & MAC_RX_CRC_ERR)
1536 cp->net_stats[0].rx_crc_errors += 0x10000;
1537
1538 if (stat & MAC_RX_LEN_ERR)
1539 cp->net_stats[0].rx_length_errors += 0x10000;
1540
1541 if (stat & MAC_RX_OVERFLOW) {
1542 cp->net_stats[0].rx_over_errors++;
1543 cp->net_stats[0].rx_fifo_errors++;
1544 }
1545
1546
1547
1548
1549 spin_unlock(&cp->stat_lock[0]);
1550 return 0;
1551}
1552
1553static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1554 u32 status)
1555{
1556 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1557
1558 if (!stat)
1559 return 0;
1560
1561 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1562 "mac interrupt, stat: 0x%x\n", stat);
1563
1564
1565
1566
1567
1568 if (stat & MAC_CTRL_PAUSE_STATE)
1569 cp->pause_entered++;
1570
1571 if (stat & MAC_CTRL_PAUSE_RECEIVED)
1572 cp->pause_last_time_recvd = (stat >> 16);
1573
1574 return 0;
1575}
1576
1577
1578
1579static inline int cas_mdio_link_not_up(struct cas *cp)
1580{
1581 u16 val;
1582
1583 switch (cp->lstate) {
1584 case link_force_ret:
1585 netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n");
1586 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1587 cp->timer_ticks = 5;
1588 cp->lstate = link_force_ok;
1589 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1590 break;
1591
1592 case link_aneg:
1593 val = cas_phy_read(cp, MII_BMCR);
1594
1595
1596
1597
1598 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1599 val |= BMCR_FULLDPLX;
1600 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1601 CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1602 cas_phy_write(cp, MII_BMCR, val);
1603 cp->timer_ticks = 5;
1604 cp->lstate = link_force_try;
1605 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1606 break;
1607
1608 case link_force_try:
1609
1610 val = cas_phy_read(cp, MII_BMCR);
1611 cp->timer_ticks = 5;
1612 if (val & CAS_BMCR_SPEED1000) {
1613 val &= ~CAS_BMCR_SPEED1000;
1614 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1615 cas_phy_write(cp, MII_BMCR, val);
1616 break;
1617 }
1618
1619 if (val & BMCR_SPEED100) {
1620 if (val & BMCR_FULLDPLX)
1621 val &= ~BMCR_FULLDPLX;
1622 else {
1623 val &= ~BMCR_SPEED100;
1624 }
1625 cas_phy_write(cp, MII_BMCR, val);
1626 break;
1627 }
1628 default:
1629 break;
1630 }
1631 return 0;
1632}
1633
1634
1635
1636static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1637{
1638 int restart;
1639
1640 if (bmsr & BMSR_LSTATUS) {
1641
1642
1643
1644
1645
1646 if ((cp->lstate == link_force_try) &&
1647 (cp->link_cntl & BMCR_ANENABLE)) {
1648 cp->lstate = link_force_ret;
1649 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1650 cas_mif_poll(cp, 0);
1651 cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1652 cp->timer_ticks = 5;
1653 if (cp->opened)
1654 netif_info(cp, link, cp->dev,
1655 "Got link after fallback, retrying autoneg once...\n");
1656 cas_phy_write(cp, MII_BMCR,
1657 cp->link_fcntl | BMCR_ANENABLE |
1658 BMCR_ANRESTART);
1659 cas_mif_poll(cp, 1);
1660
1661 } else if (cp->lstate != link_up) {
1662 cp->lstate = link_up;
1663 cp->link_transition = LINK_TRANSITION_LINK_UP;
1664
1665 if (cp->opened) {
1666 cas_set_link_modes(cp);
1667 netif_carrier_on(cp->dev);
1668 }
1669 }
1670 return 0;
1671 }
1672
1673
1674
1675
1676 restart = 0;
1677 if (cp->lstate == link_up) {
1678 cp->lstate = link_down;
1679 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1680
1681 netif_carrier_off(cp->dev);
1682 if (cp->opened)
1683 netif_info(cp, link, cp->dev, "Link down\n");
1684 restart = 1;
1685
1686 } else if (++cp->timer_ticks > 10)
1687 cas_mdio_link_not_up(cp);
1688
1689 return restart;
1690}
1691
1692static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1693 u32 status)
1694{
1695 u32 stat = readl(cp->regs + REG_MIF_STATUS);
1696 u16 bmsr;
1697
1698
1699 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1700 return 0;
1701
1702 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1703 return cas_mii_link_check(cp, bmsr);
1704}
1705
1706static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1707 u32 status)
1708{
1709 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1710
1711 if (!stat)
1712 return 0;
1713
1714 netdev_err(dev, "PCI error [%04x:%04x]",
1715 stat, readl(cp->regs + REG_BIM_DIAG));
1716
1717
1718 if ((stat & PCI_ERR_BADACK) &&
1719 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1720 pr_cont(" <No ACK64# during ABS64 cycle>");
1721
1722 if (stat & PCI_ERR_DTRTO)
1723 pr_cont(" <Delayed transaction timeout>");
1724 if (stat & PCI_ERR_OTHER)
1725 pr_cont(" <other>");
1726 if (stat & PCI_ERR_BIM_DMA_WRITE)
1727 pr_cont(" <BIM DMA 0 write req>");
1728 if (stat & PCI_ERR_BIM_DMA_READ)
1729 pr_cont(" <BIM DMA 0 read req>");
1730 pr_cont("\n");
1731
1732 if (stat & PCI_ERR_OTHER) {
1733 u16 cfg;
1734
1735
1736
1737
1738 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1739 netdev_err(dev, "Read PCI cfg space status [%04x]\n", cfg);
1740 if (cfg & PCI_STATUS_PARITY)
1741 netdev_err(dev, "PCI parity error detected\n");
1742 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1743 netdev_err(dev, "PCI target abort\n");
1744 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1745 netdev_err(dev, "PCI master acks target abort\n");
1746 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1747 netdev_err(dev, "PCI master abort\n");
1748 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1749 netdev_err(dev, "PCI system error SERR#\n");
1750 if (cfg & PCI_STATUS_DETECTED_PARITY)
1751 netdev_err(dev, "PCI parity error\n");
1752
1753
1754 cfg &= (PCI_STATUS_PARITY |
1755 PCI_STATUS_SIG_TARGET_ABORT |
1756 PCI_STATUS_REC_TARGET_ABORT |
1757 PCI_STATUS_REC_MASTER_ABORT |
1758 PCI_STATUS_SIG_SYSTEM_ERROR |
1759 PCI_STATUS_DETECTED_PARITY);
1760 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1761 }
1762
1763
1764 return 1;
1765}
1766
1767
1768
1769
1770
1771
1772static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1773 u32 status)
1774{
1775 if (status & INTR_RX_TAG_ERROR) {
1776
1777 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1778 "corrupt rx tag framing\n");
1779 spin_lock(&cp->stat_lock[0]);
1780 cp->net_stats[0].rx_errors++;
1781 spin_unlock(&cp->stat_lock[0]);
1782 goto do_reset;
1783 }
1784
1785 if (status & INTR_RX_LEN_MISMATCH) {
1786
1787 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1788 "length mismatch for rx frame\n");
1789 spin_lock(&cp->stat_lock[0]);
1790 cp->net_stats[0].rx_errors++;
1791 spin_unlock(&cp->stat_lock[0]);
1792 goto do_reset;
1793 }
1794
1795 if (status & INTR_PCS_STATUS) {
1796 if (cas_pcs_interrupt(dev, cp, status))
1797 goto do_reset;
1798 }
1799
1800 if (status & INTR_TX_MAC_STATUS) {
1801 if (cas_txmac_interrupt(dev, cp, status))
1802 goto do_reset;
1803 }
1804
1805 if (status & INTR_RX_MAC_STATUS) {
1806 if (cas_rxmac_interrupt(dev, cp, status))
1807 goto do_reset;
1808 }
1809
1810 if (status & INTR_MAC_CTRL_STATUS) {
1811 if (cas_mac_interrupt(dev, cp, status))
1812 goto do_reset;
1813 }
1814
1815 if (status & INTR_MIF_STATUS) {
1816 if (cas_mif_interrupt(dev, cp, status))
1817 goto do_reset;
1818 }
1819
1820 if (status & INTR_PCI_ERROR_STATUS) {
1821 if (cas_pci_interrupt(dev, cp, status))
1822 goto do_reset;
1823 }
1824 return 0;
1825
1826do_reset:
1827#if 1
1828 atomic_inc(&cp->reset_task_pending);
1829 atomic_inc(&cp->reset_task_pending_all);
1830 netdev_err(dev, "reset called in cas_abnormal_irq [0x%x]\n", status);
1831 schedule_work(&cp->reset_task);
1832#else
1833 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1834 netdev_err(dev, "reset called in cas_abnormal_irq\n");
1835 schedule_work(&cp->reset_task);
1836#endif
1837 return 1;
1838}
1839
1840
1841
1842
1843#define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1844#define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1845static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1846 const int len)
1847{
1848 unsigned long off = addr + len;
1849
1850 if (CAS_TABORT(cp) == 1)
1851 return 0;
1852 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1853 return 0;
1854 return TX_TARGET_ABORT_LEN;
1855}
1856
1857static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1858{
1859 struct cas_tx_desc *txds;
1860 struct sk_buff **skbs;
1861 struct net_device *dev = cp->dev;
1862 int entry, count;
1863
1864 spin_lock(&cp->tx_lock[ring]);
1865 txds = cp->init_txds[ring];
1866 skbs = cp->tx_skbs[ring];
1867 entry = cp->tx_old[ring];
1868
1869 count = TX_BUFF_COUNT(ring, entry, limit);
1870 while (entry != limit) {
1871 struct sk_buff *skb = skbs[entry];
1872 dma_addr_t daddr;
1873 u32 dlen;
1874 int frag;
1875
1876 if (!skb) {
1877
1878 entry = TX_DESC_NEXT(ring, entry);
1879 continue;
1880 }
1881
1882
1883 count -= skb_shinfo(skb)->nr_frags +
1884 + cp->tx_tiny_use[ring][entry].nbufs + 1;
1885 if (count < 0)
1886 break;
1887
1888 netif_printk(cp, tx_done, KERN_DEBUG, cp->dev,
1889 "tx[%d] done, slot %d\n", ring, entry);
1890
1891 skbs[entry] = NULL;
1892 cp->tx_tiny_use[ring][entry].nbufs = 0;
1893
1894 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1895 struct cas_tx_desc *txd = txds + entry;
1896
1897 daddr = le64_to_cpu(txd->buffer);
1898 dlen = CAS_VAL(TX_DESC_BUFLEN,
1899 le64_to_cpu(txd->control));
1900 pci_unmap_page(cp->pdev, daddr, dlen,
1901 PCI_DMA_TODEVICE);
1902 entry = TX_DESC_NEXT(ring, entry);
1903
1904
1905 if (cp->tx_tiny_use[ring][entry].used) {
1906 cp->tx_tiny_use[ring][entry].used = 0;
1907 entry = TX_DESC_NEXT(ring, entry);
1908 }
1909 }
1910
1911 spin_lock(&cp->stat_lock[ring]);
1912 cp->net_stats[ring].tx_packets++;
1913 cp->net_stats[ring].tx_bytes += skb->len;
1914 spin_unlock(&cp->stat_lock[ring]);
1915 dev_kfree_skb_irq(skb);
1916 }
1917 cp->tx_old[ring] = entry;
1918
1919
1920
1921
1922
1923 if (netif_queue_stopped(dev) &&
1924 (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1925 netif_wake_queue(dev);
1926 spin_unlock(&cp->tx_lock[ring]);
1927}
1928
1929static void cas_tx(struct net_device *dev, struct cas *cp,
1930 u32 status)
1931{
1932 int limit, ring;
1933#ifdef USE_TX_COMPWB
1934 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1935#endif
1936 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1937 "tx interrupt, status: 0x%x, %llx\n",
1938 status, (unsigned long long)compwb);
1939
1940 for (ring = 0; ring < N_TX_RINGS; ring++) {
1941#ifdef USE_TX_COMPWB
1942
1943 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1944 CAS_VAL(TX_COMPWB_LSB, compwb);
1945 compwb = TX_COMPWB_NEXT(compwb);
1946#else
1947 limit = readl(cp->regs + REG_TX_COMPN(ring));
1948#endif
1949 if (cp->tx_old[ring] != limit)
1950 cas_tx_ringN(cp, ring, limit);
1951 }
1952}
1953
1954
1955static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1956 int entry, const u64 *words,
1957 struct sk_buff **skbref)
1958{
1959 int dlen, hlen, len, i, alloclen;
1960 int off, swivel = RX_SWIVEL_OFF_VAL;
1961 struct cas_page *page;
1962 struct sk_buff *skb;
1963 void *addr, *crcaddr;
1964 __sum16 csum;
1965 char *p;
1966
1967 hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1968 dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1969 len = hlen + dlen;
1970
1971 if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1972 alloclen = len;
1973 else
1974 alloclen = max(hlen, RX_COPY_MIN);
1975
1976 skb = netdev_alloc_skb(cp->dev, alloclen + swivel + cp->crc_size);
1977 if (skb == NULL)
1978 return -1;
1979
1980 *skbref = skb;
1981 skb_reserve(skb, swivel);
1982
1983 p = skb->data;
1984 addr = crcaddr = NULL;
1985 if (hlen) {
1986 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1987 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1988 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1989 swivel;
1990
1991 i = hlen;
1992 if (!dlen)
1993 i += cp->crc_size;
1994 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
1995 PCI_DMA_FROMDEVICE);
1996 addr = cas_page_map(page->buffer);
1997 memcpy(p, addr + off, i);
1998 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
1999 PCI_DMA_FROMDEVICE);
2000 cas_page_unmap(addr);
2001 RX_USED_ADD(page, 0x100);
2002 p += hlen;
2003 swivel = 0;
2004 }
2005
2006
2007 if (alloclen < (hlen + dlen)) {
2008 skb_frag_t *frag = skb_shinfo(skb)->frags;
2009
2010
2011 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2012 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2013 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2014
2015 hlen = min(cp->page_size - off, dlen);
2016 if (hlen < 0) {
2017 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2018 "rx page overflow: %d\n", hlen);
2019 dev_kfree_skb_irq(skb);
2020 return -1;
2021 }
2022 i = hlen;
2023 if (i == dlen)
2024 i += cp->crc_size;
2025 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2026 PCI_DMA_FROMDEVICE);
2027
2028
2029 swivel = 0;
2030 if (p == (char *) skb->data) {
2031 addr = cas_page_map(page->buffer);
2032 memcpy(p, addr + off, RX_COPY_MIN);
2033 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2034 PCI_DMA_FROMDEVICE);
2035 cas_page_unmap(addr);
2036 off += RX_COPY_MIN;
2037 swivel = RX_COPY_MIN;
2038 RX_USED_ADD(page, cp->mtu_stride);
2039 } else {
2040 RX_USED_ADD(page, hlen);
2041 }
2042 skb_put(skb, alloclen);
2043
2044 skb_shinfo(skb)->nr_frags++;
2045 skb->data_len += hlen - swivel;
2046 skb->truesize += hlen - swivel;
2047 skb->len += hlen - swivel;
2048
2049 __skb_frag_set_page(frag, page->buffer);
2050 __skb_frag_ref(frag);
2051 frag->page_offset = off;
2052 skb_frag_size_set(frag, hlen - swivel);
2053
2054
2055 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2056 hlen = dlen;
2057 off = 0;
2058
2059 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2060 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2061 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2062 hlen + cp->crc_size,
2063 PCI_DMA_FROMDEVICE);
2064 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2065 hlen + cp->crc_size,
2066 PCI_DMA_FROMDEVICE);
2067
2068 skb_shinfo(skb)->nr_frags++;
2069 skb->data_len += hlen;
2070 skb->len += hlen;
2071 frag++;
2072
2073 __skb_frag_set_page(frag, page->buffer);
2074 __skb_frag_ref(frag);
2075 frag->page_offset = 0;
2076 skb_frag_size_set(frag, hlen);
2077 RX_USED_ADD(page, hlen + cp->crc_size);
2078 }
2079
2080 if (cp->crc_size) {
2081 addr = cas_page_map(page->buffer);
2082 crcaddr = addr + off + hlen;
2083 }
2084
2085 } else {
2086
2087 if (!dlen)
2088 goto end_copy_pkt;
2089
2090 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2091 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2092 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2093 hlen = min(cp->page_size - off, dlen);
2094 if (hlen < 0) {
2095 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2096 "rx page overflow: %d\n", hlen);
2097 dev_kfree_skb_irq(skb);
2098 return -1;
2099 }
2100 i = hlen;
2101 if (i == dlen)
2102 i += cp->crc_size;
2103 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2104 PCI_DMA_FROMDEVICE);
2105 addr = cas_page_map(page->buffer);
2106 memcpy(p, addr + off, i);
2107 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2108 PCI_DMA_FROMDEVICE);
2109 cas_page_unmap(addr);
2110 if (p == (char *) skb->data)
2111 RX_USED_ADD(page, cp->mtu_stride);
2112 else
2113 RX_USED_ADD(page, i);
2114
2115
2116 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2117 p += hlen;
2118 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2119 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2120 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2121 dlen + cp->crc_size,
2122 PCI_DMA_FROMDEVICE);
2123 addr = cas_page_map(page->buffer);
2124 memcpy(p, addr, dlen + cp->crc_size);
2125 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2126 dlen + cp->crc_size,
2127 PCI_DMA_FROMDEVICE);
2128 cas_page_unmap(addr);
2129 RX_USED_ADD(page, dlen + cp->crc_size);
2130 }
2131end_copy_pkt:
2132 if (cp->crc_size) {
2133 addr = NULL;
2134 crcaddr = skb->data + alloclen;
2135 }
2136 skb_put(skb, alloclen);
2137 }
2138
2139 csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
2140 if (cp->crc_size) {
2141
2142 csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
2143 csum_unfold(csum)));
2144 if (addr)
2145 cas_page_unmap(addr);
2146 }
2147 skb->protocol = eth_type_trans(skb, cp->dev);
2148 if (skb->protocol == htons(ETH_P_IP)) {
2149 skb->csum = csum_unfold(~csum);
2150 skb->ip_summed = CHECKSUM_COMPLETE;
2151 } else
2152 skb_checksum_none_assert(skb);
2153 return len;
2154}
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2172 struct sk_buff *skb)
2173{
2174 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2175 struct sk_buff_head *flow = &cp->rx_flows[flowid];
2176
2177
2178
2179
2180
2181 __skb_queue_tail(flow, skb);
2182 if (words[0] & RX_COMP1_RELEASE_FLOW) {
2183 while ((skb = __skb_dequeue(flow))) {
2184 cas_skb_release(skb);
2185 }
2186 }
2187}
2188
2189
2190
2191
2192static void cas_post_page(struct cas *cp, const int ring, const int index)
2193{
2194 cas_page_t *new;
2195 int entry;
2196
2197 entry = cp->rx_old[ring];
2198
2199 new = cas_page_swap(cp, ring, index);
2200 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2201 cp->init_rxds[ring][entry].index =
2202 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2203 CAS_BASE(RX_INDEX_RING, ring));
2204
2205 entry = RX_DESC_ENTRY(ring, entry + 1);
2206 cp->rx_old[ring] = entry;
2207
2208 if (entry % 4)
2209 return;
2210
2211 if (ring == 0)
2212 writel(entry, cp->regs + REG_RX_KICK);
2213 else if ((N_RX_DESC_RINGS > 1) &&
2214 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2215 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2216}
2217
2218
2219
2220static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2221{
2222 unsigned int entry, last, count, released;
2223 int cluster;
2224 cas_page_t **page = cp->rx_pages[ring];
2225
2226 entry = cp->rx_old[ring];
2227
2228 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2229 "rxd[%d] interrupt, done: %d\n", ring, entry);
2230
2231 cluster = -1;
2232 count = entry & 0x3;
2233 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2234 released = 0;
2235 while (entry != last) {
2236
2237 if (page_count(page[entry]->buffer) > 1) {
2238 cas_page_t *new = cas_page_dequeue(cp);
2239 if (!new) {
2240
2241
2242
2243 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2244 if (!timer_pending(&cp->link_timer))
2245 mod_timer(&cp->link_timer, jiffies +
2246 CAS_LINK_FAST_TIMEOUT);
2247 cp->rx_old[ring] = entry;
2248 cp->rx_last[ring] = num ? num - released : 0;
2249 return -ENOMEM;
2250 }
2251 spin_lock(&cp->rx_inuse_lock);
2252 list_add(&page[entry]->list, &cp->rx_inuse_list);
2253 spin_unlock(&cp->rx_inuse_lock);
2254 cp->init_rxds[ring][entry].buffer =
2255 cpu_to_le64(new->dma_addr);
2256 page[entry] = new;
2257
2258 }
2259
2260 if (++count == 4) {
2261 cluster = entry;
2262 count = 0;
2263 }
2264 released++;
2265 entry = RX_DESC_ENTRY(ring, entry + 1);
2266 }
2267 cp->rx_old[ring] = entry;
2268
2269 if (cluster < 0)
2270 return 0;
2271
2272 if (ring == 0)
2273 writel(cluster, cp->regs + REG_RX_KICK);
2274 else if ((N_RX_DESC_RINGS > 1) &&
2275 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2276 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2277 return 0;
2278}
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2294{
2295 struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2296 int entry, drops;
2297 int npackets = 0;
2298
2299 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2300 "rx[%d] interrupt, done: %d/%d\n",
2301 ring,
2302 readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]);
2303
2304 entry = cp->rx_new[ring];
2305 drops = 0;
2306 while (1) {
2307 struct cas_rx_comp *rxc = rxcs + entry;
2308 struct sk_buff *uninitialized_var(skb);
2309 int type, len;
2310 u64 words[4];
2311 int i, dring;
2312
2313 words[0] = le64_to_cpu(rxc->word1);
2314 words[1] = le64_to_cpu(rxc->word2);
2315 words[2] = le64_to_cpu(rxc->word3);
2316 words[3] = le64_to_cpu(rxc->word4);
2317
2318
2319 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2320 if (type == 0)
2321 break;
2322
2323
2324 if (words[3] & RX_COMP4_ZERO) {
2325 break;
2326 }
2327
2328
2329 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2330 spin_lock(&cp->stat_lock[ring]);
2331 cp->net_stats[ring].rx_errors++;
2332 if (words[3] & RX_COMP4_LEN_MISMATCH)
2333 cp->net_stats[ring].rx_length_errors++;
2334 if (words[3] & RX_COMP4_BAD)
2335 cp->net_stats[ring].rx_crc_errors++;
2336 spin_unlock(&cp->stat_lock[ring]);
2337
2338
2339 drop_it:
2340 spin_lock(&cp->stat_lock[ring]);
2341 ++cp->net_stats[ring].rx_dropped;
2342 spin_unlock(&cp->stat_lock[ring]);
2343 goto next;
2344 }
2345
2346 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2347 if (len < 0) {
2348 ++drops;
2349 goto drop_it;
2350 }
2351
2352
2353
2354
2355 if (RX_DONT_BATCH || (type == 0x2)) {
2356
2357 cas_skb_release(skb);
2358 } else {
2359 cas_rx_flow_pkt(cp, words, skb);
2360 }
2361
2362 spin_lock(&cp->stat_lock[ring]);
2363 cp->net_stats[ring].rx_packets++;
2364 cp->net_stats[ring].rx_bytes += len;
2365 spin_unlock(&cp->stat_lock[ring]);
2366
2367 next:
2368 npackets++;
2369
2370
2371 if (words[0] & RX_COMP1_RELEASE_HDR) {
2372 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2373 dring = CAS_VAL(RX_INDEX_RING, i);
2374 i = CAS_VAL(RX_INDEX_NUM, i);
2375 cas_post_page(cp, dring, i);
2376 }
2377
2378 if (words[0] & RX_COMP1_RELEASE_DATA) {
2379 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2380 dring = CAS_VAL(RX_INDEX_RING, i);
2381 i = CAS_VAL(RX_INDEX_NUM, i);
2382 cas_post_page(cp, dring, i);
2383 }
2384
2385 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2386 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2387 dring = CAS_VAL(RX_INDEX_RING, i);
2388 i = CAS_VAL(RX_INDEX_NUM, i);
2389 cas_post_page(cp, dring, i);
2390 }
2391
2392
2393 entry = RX_COMP_ENTRY(ring, entry + 1 +
2394 CAS_VAL(RX_COMP1_SKIP, words[0]));
2395#ifdef USE_NAPI
2396 if (budget && (npackets >= budget))
2397 break;
2398#endif
2399 }
2400 cp->rx_new[ring] = entry;
2401
2402 if (drops)
2403 netdev_info(cp->dev, "Memory squeeze, deferring packet\n");
2404 return npackets;
2405}
2406
2407
2408
2409static void cas_post_rxcs_ringN(struct net_device *dev,
2410 struct cas *cp, int ring)
2411{
2412 struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2413 int last, entry;
2414
2415 last = cp->rx_cur[ring];
2416 entry = cp->rx_new[ring];
2417 netif_printk(cp, intr, KERN_DEBUG, dev,
2418 "rxc[%d] interrupt, done: %d/%d\n",
2419 ring, readl(cp->regs + REG_RX_COMP_HEAD), entry);
2420
2421
2422 while (last != entry) {
2423 cas_rxc_init(rxc + last);
2424 last = RX_COMP_ENTRY(ring, last + 1);
2425 }
2426 cp->rx_cur[ring] = last;
2427
2428 if (ring == 0)
2429 writel(last, cp->regs + REG_RX_COMP_TAIL);
2430 else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2431 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2432}
2433
2434
2435
2436
2437
2438
2439#if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2440static inline void cas_handle_irqN(struct net_device *dev,
2441 struct cas *cp, const u32 status,
2442 const int ring)
2443{
2444 if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2445 cas_post_rxcs_ringN(dev, cp, ring);
2446}
2447
2448static irqreturn_t cas_interruptN(int irq, void *dev_id)
2449{
2450 struct net_device *dev = dev_id;
2451 struct cas *cp = netdev_priv(dev);
2452 unsigned long flags;
2453 int ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2454 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2455
2456
2457 if (status == 0)
2458 return IRQ_NONE;
2459
2460 spin_lock_irqsave(&cp->lock, flags);
2461 if (status & INTR_RX_DONE_ALT) {
2462#ifdef USE_NAPI
2463 cas_mask_intr(cp);
2464 napi_schedule(&cp->napi);
2465#else
2466 cas_rx_ringN(cp, ring, 0);
2467#endif
2468 status &= ~INTR_RX_DONE_ALT;
2469 }
2470
2471 if (status)
2472 cas_handle_irqN(dev, cp, status, ring);
2473 spin_unlock_irqrestore(&cp->lock, flags);
2474 return IRQ_HANDLED;
2475}
2476#endif
2477
2478#ifdef USE_PCI_INTB
2479
2480static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2481{
2482 if (status & INTR_RX_BUF_UNAVAIL_1) {
2483
2484
2485 cas_post_rxds_ringN(cp, 1, 0);
2486 spin_lock(&cp->stat_lock[1]);
2487 cp->net_stats[1].rx_dropped++;
2488 spin_unlock(&cp->stat_lock[1]);
2489 }
2490
2491 if (status & INTR_RX_BUF_AE_1)
2492 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2493 RX_AE_FREEN_VAL(1));
2494
2495 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2496 cas_post_rxcs_ringN(cp, 1);
2497}
2498
2499
2500static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2501{
2502 struct net_device *dev = dev_id;
2503 struct cas *cp = netdev_priv(dev);
2504 unsigned long flags;
2505 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2506
2507
2508 if (status == 0)
2509 return IRQ_NONE;
2510
2511 spin_lock_irqsave(&cp->lock, flags);
2512 if (status & INTR_RX_DONE_ALT) {
2513#ifdef USE_NAPI
2514 cas_mask_intr(cp);
2515 napi_schedule(&cp->napi);
2516#else
2517 cas_rx_ringN(cp, 1, 0);
2518#endif
2519 status &= ~INTR_RX_DONE_ALT;
2520 }
2521 if (status)
2522 cas_handle_irq1(cp, status);
2523 spin_unlock_irqrestore(&cp->lock, flags);
2524 return IRQ_HANDLED;
2525}
2526#endif
2527
2528static inline void cas_handle_irq(struct net_device *dev,
2529 struct cas *cp, const u32 status)
2530{
2531
2532 if (status & INTR_ERROR_MASK)
2533 cas_abnormal_irq(dev, cp, status);
2534
2535 if (status & INTR_RX_BUF_UNAVAIL) {
2536
2537
2538
2539 cas_post_rxds_ringN(cp, 0, 0);
2540 spin_lock(&cp->stat_lock[0]);
2541 cp->net_stats[0].rx_dropped++;
2542 spin_unlock(&cp->stat_lock[0]);
2543 } else if (status & INTR_RX_BUF_AE) {
2544 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2545 RX_AE_FREEN_VAL(0));
2546 }
2547
2548 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2549 cas_post_rxcs_ringN(dev, cp, 0);
2550}
2551
2552static irqreturn_t cas_interrupt(int irq, void *dev_id)
2553{
2554 struct net_device *dev = dev_id;
2555 struct cas *cp = netdev_priv(dev);
2556 unsigned long flags;
2557 u32 status = readl(cp->regs + REG_INTR_STATUS);
2558
2559 if (status == 0)
2560 return IRQ_NONE;
2561
2562 spin_lock_irqsave(&cp->lock, flags);
2563 if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2564 cas_tx(dev, cp, status);
2565 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2566 }
2567
2568 if (status & INTR_RX_DONE) {
2569#ifdef USE_NAPI
2570 cas_mask_intr(cp);
2571 napi_schedule(&cp->napi);
2572#else
2573 cas_rx_ringN(cp, 0, 0);
2574#endif
2575 status &= ~INTR_RX_DONE;
2576 }
2577
2578 if (status)
2579 cas_handle_irq(dev, cp, status);
2580 spin_unlock_irqrestore(&cp->lock, flags);
2581 return IRQ_HANDLED;
2582}
2583
2584
2585#ifdef USE_NAPI
2586static int cas_poll(struct napi_struct *napi, int budget)
2587{
2588 struct cas *cp = container_of(napi, struct cas, napi);
2589 struct net_device *dev = cp->dev;
2590 int i, enable_intr, credits;
2591 u32 status = readl(cp->regs + REG_INTR_STATUS);
2592 unsigned long flags;
2593
2594 spin_lock_irqsave(&cp->lock, flags);
2595 cas_tx(dev, cp, status);
2596 spin_unlock_irqrestore(&cp->lock, flags);
2597
2598
2599
2600
2601
2602
2603
2604
2605 enable_intr = 1;
2606 credits = 0;
2607 for (i = 0; i < N_RX_COMP_RINGS; i++) {
2608 int j;
2609 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2610 credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2611 if (credits >= budget) {
2612 enable_intr = 0;
2613 goto rx_comp;
2614 }
2615 }
2616 }
2617
2618rx_comp:
2619
2620 spin_lock_irqsave(&cp->lock, flags);
2621 if (status)
2622 cas_handle_irq(dev, cp, status);
2623
2624#ifdef USE_PCI_INTB
2625 if (N_RX_COMP_RINGS > 1) {
2626 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2627 if (status)
2628 cas_handle_irq1(dev, cp, status);
2629 }
2630#endif
2631
2632#ifdef USE_PCI_INTC
2633 if (N_RX_COMP_RINGS > 2) {
2634 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2635 if (status)
2636 cas_handle_irqN(dev, cp, status, 2);
2637 }
2638#endif
2639
2640#ifdef USE_PCI_INTD
2641 if (N_RX_COMP_RINGS > 3) {
2642 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2643 if (status)
2644 cas_handle_irqN(dev, cp, status, 3);
2645 }
2646#endif
2647 spin_unlock_irqrestore(&cp->lock, flags);
2648 if (enable_intr) {
2649 napi_complete(napi);
2650 cas_unmask_intr(cp);
2651 }
2652 return credits;
2653}
2654#endif
2655
2656#ifdef CONFIG_NET_POLL_CONTROLLER
2657static void cas_netpoll(struct net_device *dev)
2658{
2659 struct cas *cp = netdev_priv(dev);
2660
2661 cas_disable_irq(cp, 0);
2662 cas_interrupt(cp->pdev->irq, dev);
2663 cas_enable_irq(cp, 0);
2664
2665#ifdef USE_PCI_INTB
2666 if (N_RX_COMP_RINGS > 1) {
2667
2668 }
2669#endif
2670#ifdef USE_PCI_INTC
2671 if (N_RX_COMP_RINGS > 2) {
2672
2673 }
2674#endif
2675#ifdef USE_PCI_INTD
2676 if (N_RX_COMP_RINGS > 3) {
2677
2678 }
2679#endif
2680}
2681#endif
2682
2683static void cas_tx_timeout(struct net_device *dev)
2684{
2685 struct cas *cp = netdev_priv(dev);
2686
2687 netdev_err(dev, "transmit timed out, resetting\n");
2688 if (!cp->hw_running) {
2689 netdev_err(dev, "hrm.. hw not running!\n");
2690 return;
2691 }
2692
2693 netdev_err(dev, "MIF_STATE[%08x]\n",
2694 readl(cp->regs + REG_MIF_STATE_MACHINE));
2695
2696 netdev_err(dev, "MAC_STATE[%08x]\n",
2697 readl(cp->regs + REG_MAC_STATE_MACHINE));
2698
2699 netdev_err(dev, "TX_STATE[%08x:%08x:%08x] FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2700 readl(cp->regs + REG_TX_CFG),
2701 readl(cp->regs + REG_MAC_TX_STATUS),
2702 readl(cp->regs + REG_MAC_TX_CFG),
2703 readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2704 readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2705 readl(cp->regs + REG_TX_FIFO_READ_PTR),
2706 readl(cp->regs + REG_TX_SM_1),
2707 readl(cp->regs + REG_TX_SM_2));
2708
2709 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
2710 readl(cp->regs + REG_RX_CFG),
2711 readl(cp->regs + REG_MAC_RX_STATUS),
2712 readl(cp->regs + REG_MAC_RX_CFG));
2713
2714 netdev_err(dev, "HP_STATE[%08x:%08x:%08x:%08x]\n",
2715 readl(cp->regs + REG_HP_STATE_MACHINE),
2716 readl(cp->regs + REG_HP_STATUS0),
2717 readl(cp->regs + REG_HP_STATUS1),
2718 readl(cp->regs + REG_HP_STATUS2));
2719
2720#if 1
2721 atomic_inc(&cp->reset_task_pending);
2722 atomic_inc(&cp->reset_task_pending_all);
2723 schedule_work(&cp->reset_task);
2724#else
2725 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2726 schedule_work(&cp->reset_task);
2727#endif
2728}
2729
2730static inline int cas_intme(int ring, int entry)
2731{
2732
2733 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2734 return 1;
2735 return 0;
2736}
2737
2738
2739static void cas_write_txd(struct cas *cp, int ring, int entry,
2740 dma_addr_t mapping, int len, u64 ctrl, int last)
2741{
2742 struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2743
2744 ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2745 if (cas_intme(ring, entry))
2746 ctrl |= TX_DESC_INTME;
2747 if (last)
2748 ctrl |= TX_DESC_EOF;
2749 txd->control = cpu_to_le64(ctrl);
2750 txd->buffer = cpu_to_le64(mapping);
2751}
2752
2753static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2754 const int entry)
2755{
2756 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2757}
2758
2759static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2760 const int entry, const int tentry)
2761{
2762 cp->tx_tiny_use[ring][tentry].nbufs++;
2763 cp->tx_tiny_use[ring][entry].used = 1;
2764 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2765}
2766
2767static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2768 struct sk_buff *skb)
2769{
2770 struct net_device *dev = cp->dev;
2771 int entry, nr_frags, frag, tabort, tentry;
2772 dma_addr_t mapping;
2773 unsigned long flags;
2774 u64 ctrl;
2775 u32 len;
2776
2777 spin_lock_irqsave(&cp->tx_lock[ring], flags);
2778
2779
2780 if (TX_BUFFS_AVAIL(cp, ring) <=
2781 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2782 netif_stop_queue(dev);
2783 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2784 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
2785 return 1;
2786 }
2787
2788 ctrl = 0;
2789 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2790 const u64 csum_start_off = skb_checksum_start_offset(skb);
2791 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2792
2793 ctrl = TX_DESC_CSUM_EN |
2794 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2795 CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2796 }
2797
2798 entry = cp->tx_new[ring];
2799 cp->tx_skbs[ring][entry] = skb;
2800
2801 nr_frags = skb_shinfo(skb)->nr_frags;
2802 len = skb_headlen(skb);
2803 mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2804 offset_in_page(skb->data), len,
2805 PCI_DMA_TODEVICE);
2806
2807 tentry = entry;
2808 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2809 if (unlikely(tabort)) {
2810
2811 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2812 ctrl | TX_DESC_SOF, 0);
2813 entry = TX_DESC_NEXT(ring, entry);
2814
2815 skb_copy_from_linear_data_offset(skb, len - tabort,
2816 tx_tiny_buf(cp, ring, entry), tabort);
2817 mapping = tx_tiny_map(cp, ring, entry, tentry);
2818 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2819 (nr_frags == 0));
2820 } else {
2821 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2822 TX_DESC_SOF, (nr_frags == 0));
2823 }
2824 entry = TX_DESC_NEXT(ring, entry);
2825
2826 for (frag = 0; frag < nr_frags; frag++) {
2827 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2828
2829 len = skb_frag_size(fragp);
2830 mapping = skb_frag_dma_map(&cp->pdev->dev, fragp, 0, len,
2831 DMA_TO_DEVICE);
2832
2833 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2834 if (unlikely(tabort)) {
2835 void *addr;
2836
2837
2838 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2839 ctrl, 0);
2840 entry = TX_DESC_NEXT(ring, entry);
2841
2842 addr = cas_page_map(skb_frag_page(fragp));
2843 memcpy(tx_tiny_buf(cp, ring, entry),
2844 addr + fragp->page_offset + len - tabort,
2845 tabort);
2846 cas_page_unmap(addr);
2847 mapping = tx_tiny_map(cp, ring, entry, tentry);
2848 len = tabort;
2849 }
2850
2851 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2852 (frag + 1 == nr_frags));
2853 entry = TX_DESC_NEXT(ring, entry);
2854 }
2855
2856 cp->tx_new[ring] = entry;
2857 if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2858 netif_stop_queue(dev);
2859
2860 netif_printk(cp, tx_queued, KERN_DEBUG, dev,
2861 "tx[%d] queued, slot %d, skblen %d, avail %d\n",
2862 ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring));
2863 writel(entry, cp->regs + REG_TX_KICKN(ring));
2864 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2865 return 0;
2866}
2867
2868static netdev_tx_t cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2869{
2870 struct cas *cp = netdev_priv(dev);
2871
2872
2873
2874
2875 static int ring;
2876
2877 if (skb_padto(skb, cp->min_frame_size))
2878 return NETDEV_TX_OK;
2879
2880
2881
2882
2883 if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2884 return NETDEV_TX_BUSY;
2885 return NETDEV_TX_OK;
2886}
2887
2888static void cas_init_tx_dma(struct cas *cp)
2889{
2890 u64 desc_dma = cp->block_dvma;
2891 unsigned long off;
2892 u32 val;
2893 int i;
2894
2895
2896#ifdef USE_TX_COMPWB
2897 off = offsetof(struct cas_init_block, tx_compwb);
2898 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2899 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2900#endif
2901
2902
2903
2904
2905 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2906 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2907 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2908 TX_CFG_INTR_COMPWB_DIS;
2909
2910
2911 for (i = 0; i < MAX_TX_RINGS; i++) {
2912 off = (unsigned long) cp->init_txds[i] -
2913 (unsigned long) cp->init_block;
2914
2915 val |= CAS_TX_RINGN_BASE(i);
2916 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2917 writel((desc_dma + off) & 0xffffffff, cp->regs +
2918 REG_TX_DBN_LOW(i));
2919
2920
2921
2922 }
2923 writel(val, cp->regs + REG_TX_CFG);
2924
2925
2926
2927
2928#ifdef USE_QOS
2929 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2930 writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2931 writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2932 writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2933#else
2934 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2935 writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2936 writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2937 writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2938#endif
2939}
2940
2941
2942static inline void cas_init_dma(struct cas *cp)
2943{
2944 cas_init_tx_dma(cp);
2945 cas_init_rx_dma(cp);
2946}
2947
2948static void cas_process_mc_list(struct cas *cp)
2949{
2950 u16 hash_table[16];
2951 u32 crc;
2952 struct netdev_hw_addr *ha;
2953 int i = 1;
2954
2955 memset(hash_table, 0, sizeof(hash_table));
2956 netdev_for_each_mc_addr(ha, cp->dev) {
2957 if (i <= CAS_MC_EXACT_MATCH_SIZE) {
2958
2959
2960
2961 writel((ha->addr[4] << 8) | ha->addr[5],
2962 cp->regs + REG_MAC_ADDRN(i*3 + 0));
2963 writel((ha->addr[2] << 8) | ha->addr[3],
2964 cp->regs + REG_MAC_ADDRN(i*3 + 1));
2965 writel((ha->addr[0] << 8) | ha->addr[1],
2966 cp->regs + REG_MAC_ADDRN(i*3 + 2));
2967 i++;
2968 }
2969 else {
2970
2971
2972
2973 crc = ether_crc_le(ETH_ALEN, ha->addr);
2974 crc >>= 24;
2975 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
2976 }
2977 }
2978 for (i = 0; i < 16; i++)
2979 writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i));
2980}
2981
2982
2983static u32 cas_setup_multicast(struct cas *cp)
2984{
2985 u32 rxcfg = 0;
2986 int i;
2987
2988 if (cp->dev->flags & IFF_PROMISC) {
2989 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2990
2991 } else if (cp->dev->flags & IFF_ALLMULTI) {
2992 for (i=0; i < 16; i++)
2993 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2994 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2995
2996 } else {
2997 cas_process_mc_list(cp);
2998 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2999 }
3000
3001 return rxcfg;
3002}
3003
3004
3005static void cas_clear_mac_err(struct cas *cp)
3006{
3007 writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3008 writel(0, cp->regs + REG_MAC_COLL_FIRST);
3009 writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3010 writel(0, cp->regs + REG_MAC_COLL_LATE);
3011 writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3012 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3013 writel(0, cp->regs + REG_MAC_RECV_FRAME);
3014 writel(0, cp->regs + REG_MAC_LEN_ERR);
3015 writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3016 writel(0, cp->regs + REG_MAC_FCS_ERR);
3017 writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3018}
3019
3020
3021static void cas_mac_reset(struct cas *cp)
3022{
3023 int i;
3024
3025
3026 writel(0x1, cp->regs + REG_MAC_TX_RESET);
3027 writel(0x1, cp->regs + REG_MAC_RX_RESET);
3028
3029
3030 i = STOP_TRIES;
3031 while (i-- > 0) {
3032 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3033 break;
3034 udelay(10);
3035 }
3036
3037
3038 i = STOP_TRIES;
3039 while (i-- > 0) {
3040 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3041 break;
3042 udelay(10);
3043 }
3044
3045 if (readl(cp->regs + REG_MAC_TX_RESET) |
3046 readl(cp->regs + REG_MAC_RX_RESET))
3047 netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n",
3048 readl(cp->regs + REG_MAC_TX_RESET),
3049 readl(cp->regs + REG_MAC_RX_RESET),
3050 readl(cp->regs + REG_MAC_STATE_MACHINE));
3051}
3052
3053
3054
3055static void cas_init_mac(struct cas *cp)
3056{
3057 unsigned char *e = &cp->dev->dev_addr[0];
3058 int i;
3059 cas_mac_reset(cp);
3060
3061
3062 writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3063
3064
3065#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3066
3067
3068
3069 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3070 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3071#endif
3072
3073 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3074
3075 writel(0x00, cp->regs + REG_MAC_IPG0);
3076 writel(0x08, cp->regs + REG_MAC_IPG1);
3077 writel(0x04, cp->regs + REG_MAC_IPG2);
3078
3079
3080 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3081
3082
3083 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3084
3085
3086
3087
3088
3089 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3090 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3091 (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3092 cp->regs + REG_MAC_FRAMESIZE_MAX);
3093
3094
3095
3096
3097
3098 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3099 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3100 else
3101 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3102 writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3103 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3104 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3105
3106 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3107
3108 writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3109 writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3110 writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3111 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3112 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3113
3114
3115 for (i = 0; i < 45; i++)
3116 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3117
3118 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3119 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3120 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3121
3122 writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3123 writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3124 writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3125
3126 cp->mac_rx_cfg = cas_setup_multicast(cp);
3127
3128 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3129 cas_clear_mac_err(cp);
3130 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3131
3132
3133
3134
3135
3136 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3137 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3138
3139
3140
3141
3142 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3143}
3144
3145
3146static void cas_init_pause_thresholds(struct cas *cp)
3147{
3148
3149
3150
3151 if (cp->rx_fifo_size <= (2 * 1024)) {
3152 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3153 } else {
3154 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3155 if (max_frame * 3 > cp->rx_fifo_size) {
3156 cp->rx_pause_off = 7104;
3157 cp->rx_pause_on = 960;
3158 } else {
3159 int off = (cp->rx_fifo_size - (max_frame * 2));
3160 int on = off - max_frame;
3161 cp->rx_pause_off = off;
3162 cp->rx_pause_on = on;
3163 }
3164 }
3165}
3166
3167static int cas_vpd_match(const void __iomem *p, const char *str)
3168{
3169 int len = strlen(str) + 1;
3170 int i;
3171
3172 for (i = 0; i < len; i++) {
3173 if (readb(p + i) != str[i])
3174 return 0;
3175 }
3176 return 1;
3177}
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3192 const int offset)
3193{
3194 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3195 void __iomem *base, *kstart;
3196 int i, len;
3197 int found = 0;
3198#define VPD_FOUND_MAC 0x01
3199#define VPD_FOUND_PHY 0x02
3200
3201 int phy_type = CAS_PHY_MII_MDIO0;
3202 int mac_off = 0;
3203
3204#if defined(CONFIG_SPARC)
3205 const unsigned char *addr;
3206#endif
3207
3208
3209 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3210 cp->regs + REG_BIM_LOCAL_DEV_EN);
3211
3212
3213 if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3214 goto use_random_mac_addr;
3215
3216
3217 base = NULL;
3218 for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3219
3220 if ((readb(p + i + 0) == 0x50) &&
3221 (readb(p + i + 1) == 0x43) &&
3222 (readb(p + i + 2) == 0x49) &&
3223 (readb(p + i + 3) == 0x52)) {
3224 base = p + (readb(p + i + 8) |
3225 (readb(p + i + 9) << 8));
3226 break;
3227 }
3228 }
3229
3230 if (!base || (readb(base) != 0x82))
3231 goto use_random_mac_addr;
3232
3233 i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3234 while (i < EXPANSION_ROM_SIZE) {
3235 if (readb(base + i) != 0x90)
3236 goto use_random_mac_addr;
3237
3238
3239 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3240
3241
3242 kstart = base + i + 3;
3243 p = kstart;
3244 while ((p - kstart) < len) {
3245 int klen = readb(p + 2);
3246 int j;
3247 char type;
3248
3249 p += 3;
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288 if (readb(p) != 'I')
3289 goto next;
3290
3291
3292 type = readb(p + 3);
3293 if (type == 'B') {
3294 if ((klen == 29) && readb(p + 4) == 6 &&
3295 cas_vpd_match(p + 5,
3296 "local-mac-address")) {
3297 if (mac_off++ > offset)
3298 goto next;
3299
3300
3301 for (j = 0; j < 6; j++)
3302 dev_addr[j] =
3303 readb(p + 23 + j);
3304 goto found_mac;
3305 }
3306 }
3307
3308 if (type != 'S')
3309 goto next;
3310
3311#ifdef USE_ENTROPY_DEV
3312 if ((klen == 24) &&
3313 cas_vpd_match(p + 5, "entropy-dev") &&
3314 cas_vpd_match(p + 17, "vms110")) {
3315 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3316 goto next;
3317 }
3318#endif
3319
3320 if (found & VPD_FOUND_PHY)
3321 goto next;
3322
3323 if ((klen == 18) && readb(p + 4) == 4 &&
3324 cas_vpd_match(p + 5, "phy-type")) {
3325 if (cas_vpd_match(p + 14, "pcs")) {
3326 phy_type = CAS_PHY_SERDES;
3327 goto found_phy;
3328 }
3329 }
3330
3331 if ((klen == 23) && readb(p + 4) == 4 &&
3332 cas_vpd_match(p + 5, "phy-interface")) {
3333 if (cas_vpd_match(p + 19, "pcs")) {
3334 phy_type = CAS_PHY_SERDES;
3335 goto found_phy;
3336 }
3337 }
3338found_mac:
3339 found |= VPD_FOUND_MAC;
3340 goto next;
3341
3342found_phy:
3343 found |= VPD_FOUND_PHY;
3344
3345next:
3346 p += klen;
3347 }
3348 i += len + 3;
3349 }
3350
3351use_random_mac_addr:
3352 if (found & VPD_FOUND_MAC)
3353 goto done;
3354
3355#if defined(CONFIG_SPARC)
3356 addr = of_get_property(cp->of_node, "local-mac-address", NULL);
3357 if (addr != NULL) {
3358 memcpy(dev_addr, addr, 6);
3359 goto done;
3360 }
3361#endif
3362
3363
3364 pr_info("MAC address not found in ROM VPD\n");
3365 dev_addr[0] = 0x08;
3366 dev_addr[1] = 0x00;
3367 dev_addr[2] = 0x20;
3368 get_random_bytes(dev_addr + 3, 3);
3369
3370done:
3371 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3372 return phy_type;
3373}
3374
3375
3376static void cas_check_pci_invariants(struct cas *cp)
3377{
3378 struct pci_dev *pdev = cp->pdev;
3379
3380 cp->cas_flags = 0;
3381 if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3382 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3383 if (pdev->revision >= CAS_ID_REVPLUS)
3384 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3385 if (pdev->revision < CAS_ID_REVPLUS02u)
3386 cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3387
3388
3389
3390
3391 if (pdev->revision < CAS_ID_REV2)
3392 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3393 } else {
3394
3395 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3396
3397
3398
3399
3400 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3401 (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3402 cp->cas_flags |= CAS_FLAG_SATURN;
3403 }
3404}
3405
3406
3407static int cas_check_invariants(struct cas *cp)
3408{
3409 struct pci_dev *pdev = cp->pdev;
3410 u32 cfg;
3411 int i;
3412
3413
3414 cp->page_order = 0;
3415#ifdef USE_PAGE_ORDER
3416 if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3417
3418 struct page *page = alloc_pages(GFP_ATOMIC,
3419 CAS_JUMBO_PAGE_SHIFT -
3420 PAGE_SHIFT);
3421 if (page) {
3422 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3423 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3424 } else {
3425 printk("MTU limited to %d bytes\n", CAS_MAX_MTU);
3426 }
3427 }
3428#endif
3429 cp->page_size = (PAGE_SIZE << cp->page_order);
3430
3431
3432 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3433 cp->rx_fifo_size = RX_FIFO_SIZE;
3434
3435
3436
3437
3438 cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3439 PCI_SLOT(pdev->devfn));
3440 if (cp->phy_type & CAS_PHY_SERDES) {
3441 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3442 return 0;
3443 }
3444
3445
3446 cfg = readl(cp->regs + REG_MIF_CFG);
3447 if (cfg & MIF_CFG_MDIO_1) {
3448 cp->phy_type = CAS_PHY_MII_MDIO1;
3449 } else if (cfg & MIF_CFG_MDIO_0) {
3450 cp->phy_type = CAS_PHY_MII_MDIO0;
3451 }
3452
3453 cas_mif_poll(cp, 0);
3454 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3455
3456 for (i = 0; i < 32; i++) {
3457 u32 phy_id;
3458 int j;
3459
3460 for (j = 0; j < 3; j++) {
3461 cp->phy_addr = i;
3462 phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3463 phy_id |= cas_phy_read(cp, MII_PHYSID2);
3464 if (phy_id && (phy_id != 0xFFFFFFFF)) {
3465 cp->phy_id = phy_id;
3466 goto done;
3467 }
3468 }
3469 }
3470 pr_err("MII phy did not respond [%08x]\n",
3471 readl(cp->regs + REG_MIF_STATE_MACHINE));
3472 return -1;
3473
3474done:
3475
3476 cfg = cas_phy_read(cp, MII_BMSR);
3477 if ((cfg & CAS_BMSR_1000_EXTEND) &&
3478 cas_phy_read(cp, CAS_MII_1000_EXTEND))
3479 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3480 return 0;
3481}
3482
3483
3484static inline void cas_start_dma(struct cas *cp)
3485{
3486 int i;
3487 u32 val;
3488 int txfailed = 0;
3489
3490
3491 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3492 writel(val, cp->regs + REG_TX_CFG);
3493 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3494 writel(val, cp->regs + REG_RX_CFG);
3495
3496
3497 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3498 writel(val, cp->regs + REG_MAC_TX_CFG);
3499 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3500 writel(val, cp->regs + REG_MAC_RX_CFG);
3501
3502 i = STOP_TRIES;
3503 while (i-- > 0) {
3504 val = readl(cp->regs + REG_MAC_TX_CFG);
3505 if ((val & MAC_TX_CFG_EN))
3506 break;
3507 udelay(10);
3508 }
3509 if (i < 0) txfailed = 1;
3510 i = STOP_TRIES;
3511 while (i-- > 0) {
3512 val = readl(cp->regs + REG_MAC_RX_CFG);
3513 if ((val & MAC_RX_CFG_EN)) {
3514 if (txfailed) {
3515 netdev_err(cp->dev,
3516 "enabling mac failed [tx:%08x:%08x]\n",
3517 readl(cp->regs + REG_MIF_STATE_MACHINE),
3518 readl(cp->regs + REG_MAC_STATE_MACHINE));
3519 }
3520 goto enable_rx_done;
3521 }
3522 udelay(10);
3523 }
3524 netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n",
3525 (txfailed ? "tx,rx" : "rx"),
3526 readl(cp->regs + REG_MIF_STATE_MACHINE),
3527 readl(cp->regs + REG_MAC_STATE_MACHINE));
3528
3529enable_rx_done:
3530 cas_unmask_intr(cp);
3531 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3532 writel(0, cp->regs + REG_RX_COMP_TAIL);
3533
3534 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3535 if (N_RX_DESC_RINGS > 1)
3536 writel(RX_DESC_RINGN_SIZE(1) - 4,
3537 cp->regs + REG_PLUS_RX_KICK1);
3538
3539 for (i = 1; i < N_RX_COMP_RINGS; i++)
3540 writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3541 }
3542}
3543
3544
3545static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3546 int *pause)
3547{
3548 u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3549 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0;
3550 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3551 if (val & PCS_MII_LPA_ASYM_PAUSE)
3552 *pause |= 0x10;
3553 *spd = 1000;
3554}
3555
3556
3557static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3558 int *pause)
3559{
3560 u32 val;
3561
3562 *fd = 0;
3563 *spd = 10;
3564 *pause = 0;
3565
3566
3567 val = cas_phy_read(cp, MII_LPA);
3568 if (val & CAS_LPA_PAUSE)
3569 *pause = 0x01;
3570
3571 if (val & CAS_LPA_ASYM_PAUSE)
3572 *pause |= 0x10;
3573
3574 if (val & LPA_DUPLEX)
3575 *fd = 1;
3576 if (val & LPA_100)
3577 *spd = 100;
3578
3579 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3580 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3581 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3582 *spd = 1000;
3583 if (val & CAS_LPA_1000FULL)
3584 *fd = 1;
3585 }
3586}
3587
3588
3589
3590
3591
3592
3593static void cas_set_link_modes(struct cas *cp)
3594{
3595 u32 val;
3596 int full_duplex, speed, pause;
3597
3598 full_duplex = 0;
3599 speed = 10;
3600 pause = 0;
3601
3602 if (CAS_PHY_MII(cp->phy_type)) {
3603 cas_mif_poll(cp, 0);
3604 val = cas_phy_read(cp, MII_BMCR);
3605 if (val & BMCR_ANENABLE) {
3606 cas_read_mii_link_mode(cp, &full_duplex, &speed,
3607 &pause);
3608 } else {
3609 if (val & BMCR_FULLDPLX)
3610 full_duplex = 1;
3611
3612 if (val & BMCR_SPEED100)
3613 speed = 100;
3614 else if (val & CAS_BMCR_SPEED1000)
3615 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3616 1000 : 100;
3617 }
3618 cas_mif_poll(cp, 1);
3619
3620 } else {
3621 val = readl(cp->regs + REG_PCS_MII_CTRL);
3622 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3623 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3624 if (val & PCS_MII_CTRL_DUPLEX)
3625 full_duplex = 1;
3626 }
3627 }
3628
3629 netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n",
3630 speed, full_duplex ? "full" : "half");
3631
3632 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3633 if (CAS_PHY_MII(cp->phy_type)) {
3634 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3635 if (!full_duplex)
3636 val |= MAC_XIF_DISABLE_ECHO;
3637 }
3638 if (full_duplex)
3639 val |= MAC_XIF_FDPLX_LED;
3640 if (speed == 1000)
3641 val |= MAC_XIF_GMII_MODE;
3642 writel(val, cp->regs + REG_MAC_XIF_CFG);
3643
3644
3645 val = MAC_TX_CFG_IPG_EN;
3646 if (full_duplex) {
3647 val |= MAC_TX_CFG_IGNORE_CARRIER;
3648 val |= MAC_TX_CFG_IGNORE_COLL;
3649 } else {
3650#ifndef USE_CSMA_CD_PROTO
3651 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3652 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3653#endif
3654 }
3655
3656
3657
3658
3659
3660
3661
3662 if ((speed == 1000) && !full_duplex) {
3663 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3664 cp->regs + REG_MAC_TX_CFG);
3665
3666 val = readl(cp->regs + REG_MAC_RX_CFG);
3667 val &= ~MAC_RX_CFG_STRIP_FCS;
3668 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3669 cp->regs + REG_MAC_RX_CFG);
3670
3671 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3672
3673 cp->crc_size = 4;
3674
3675 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3676
3677 } else {
3678 writel(val, cp->regs + REG_MAC_TX_CFG);
3679
3680
3681
3682
3683 val = readl(cp->regs + REG_MAC_RX_CFG);
3684 if (full_duplex) {
3685 val |= MAC_RX_CFG_STRIP_FCS;
3686 cp->crc_size = 0;
3687 cp->min_frame_size = CAS_MIN_MTU;
3688 } else {
3689 val &= ~MAC_RX_CFG_STRIP_FCS;
3690 cp->crc_size = 4;
3691 cp->min_frame_size = CAS_MIN_FRAME;
3692 }
3693 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3694 cp->regs + REG_MAC_RX_CFG);
3695 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3696 }
3697
3698 if (netif_msg_link(cp)) {
3699 if (pause & 0x01) {
3700 netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
3701 cp->rx_fifo_size,
3702 cp->rx_pause_off,
3703 cp->rx_pause_on);
3704 } else if (pause & 0x10) {
3705 netdev_info(cp->dev, "TX pause enabled\n");
3706 } else {
3707 netdev_info(cp->dev, "Pause is disabled\n");
3708 }
3709 }
3710
3711 val = readl(cp->regs + REG_MAC_CTRL_CFG);
3712 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3713 if (pause) {
3714 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3715 if (pause & 0x01) {
3716 val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3717 }
3718 }
3719 writel(val, cp->regs + REG_MAC_CTRL_CFG);
3720 cas_start_dma(cp);
3721}
3722
3723
3724static void cas_init_hw(struct cas *cp, int restart_link)
3725{
3726 if (restart_link)
3727 cas_phy_init(cp);
3728
3729 cas_init_pause_thresholds(cp);
3730 cas_init_mac(cp);
3731 cas_init_dma(cp);
3732
3733 if (restart_link) {
3734
3735 cp->timer_ticks = 0;
3736 cas_begin_auto_negotiation(cp, NULL);
3737 } else if (cp->lstate == link_up) {
3738 cas_set_link_modes(cp);
3739 netif_carrier_on(cp->dev);
3740 }
3741}
3742
3743
3744
3745
3746
3747static void cas_hard_reset(struct cas *cp)
3748{
3749 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3750 udelay(20);
3751 pci_restore_state(cp->pdev);
3752}
3753
3754
3755static void cas_global_reset(struct cas *cp, int blkflag)
3756{
3757 int limit;
3758
3759
3760 if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3761
3762
3763
3764
3765
3766
3767 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3768 cp->regs + REG_SW_RESET);
3769 } else {
3770 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3771 }
3772
3773
3774 mdelay(3);
3775
3776 limit = STOP_TRIES;
3777 while (limit-- > 0) {
3778 u32 val = readl(cp->regs + REG_SW_RESET);
3779 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3780 goto done;
3781 udelay(10);
3782 }
3783 netdev_err(cp->dev, "sw reset failed\n");
3784
3785done:
3786
3787 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3788 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3789
3790
3791
3792
3793
3794 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3795 PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3796 PCI_ERR_BIM_DMA_READ), cp->regs +
3797 REG_PCI_ERR_STATUS_MASK);
3798
3799
3800
3801
3802 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3803}
3804
3805static void cas_reset(struct cas *cp, int blkflag)
3806{
3807 u32 val;
3808
3809 cas_mask_intr(cp);
3810 cas_global_reset(cp, blkflag);
3811 cas_mac_reset(cp);
3812 cas_entropy_reset(cp);
3813
3814
3815 val = readl(cp->regs + REG_TX_CFG);
3816 val &= ~TX_CFG_DMA_EN;
3817 writel(val, cp->regs + REG_TX_CFG);
3818
3819 val = readl(cp->regs + REG_RX_CFG);
3820 val &= ~RX_CFG_DMA_EN;
3821 writel(val, cp->regs + REG_RX_CFG);
3822
3823
3824 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3825 (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3826 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3827 } else {
3828 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3829 }
3830
3831
3832 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3833 cas_clear_mac_err(cp);
3834 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3835}
3836
3837
3838static void cas_shutdown(struct cas *cp)
3839{
3840 unsigned long flags;
3841
3842
3843 cp->hw_running = 0;
3844
3845 del_timer_sync(&cp->link_timer);
3846
3847
3848#if 0
3849 while (atomic_read(&cp->reset_task_pending_mtu) ||
3850 atomic_read(&cp->reset_task_pending_spare) ||
3851 atomic_read(&cp->reset_task_pending_all))
3852 schedule();
3853
3854#else
3855 while (atomic_read(&cp->reset_task_pending))
3856 schedule();
3857#endif
3858
3859 cas_lock_all_save(cp, flags);
3860 cas_reset(cp, 0);
3861 if (cp->cas_flags & CAS_FLAG_SATURN)
3862 cas_phy_powerdown(cp);
3863 cas_unlock_all_restore(cp, flags);
3864}
3865
3866static int cas_change_mtu(struct net_device *dev, int new_mtu)
3867{
3868 struct cas *cp = netdev_priv(dev);
3869
3870 if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
3871 return -EINVAL;
3872
3873 dev->mtu = new_mtu;
3874 if (!netif_running(dev) || !netif_device_present(dev))
3875 return 0;
3876
3877
3878#if 1
3879 atomic_inc(&cp->reset_task_pending);
3880 if ((cp->phy_type & CAS_PHY_SERDES)) {
3881 atomic_inc(&cp->reset_task_pending_all);
3882 } else {
3883 atomic_inc(&cp->reset_task_pending_mtu);
3884 }
3885 schedule_work(&cp->reset_task);
3886#else
3887 atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3888 CAS_RESET_ALL : CAS_RESET_MTU);
3889 pr_err("reset called in cas_change_mtu\n");
3890 schedule_work(&cp->reset_task);
3891#endif
3892
3893 flush_work(&cp->reset_task);
3894 return 0;
3895}
3896
3897static void cas_clean_txd(struct cas *cp, int ring)
3898{
3899 struct cas_tx_desc *txd = cp->init_txds[ring];
3900 struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3901 u64 daddr, dlen;
3902 int i, size;
3903
3904 size = TX_DESC_RINGN_SIZE(ring);
3905 for (i = 0; i < size; i++) {
3906 int frag;
3907
3908 if (skbs[i] == NULL)
3909 continue;
3910
3911 skb = skbs[i];
3912 skbs[i] = NULL;
3913
3914 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
3915 int ent = i & (size - 1);
3916
3917
3918
3919
3920 daddr = le64_to_cpu(txd[ent].buffer);
3921 dlen = CAS_VAL(TX_DESC_BUFLEN,
3922 le64_to_cpu(txd[ent].control));
3923 pci_unmap_page(cp->pdev, daddr, dlen,
3924 PCI_DMA_TODEVICE);
3925
3926 if (frag != skb_shinfo(skb)->nr_frags) {
3927 i++;
3928
3929
3930
3931
3932 ent = i & (size - 1);
3933 if (cp->tx_tiny_use[ring][ent].used)
3934 i++;
3935 }
3936 }
3937 dev_kfree_skb_any(skb);
3938 }
3939
3940
3941 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3942}
3943
3944
3945static inline void cas_free_rx_desc(struct cas *cp, int ring)
3946{
3947 cas_page_t **page = cp->rx_pages[ring];
3948 int i, size;
3949
3950 size = RX_DESC_RINGN_SIZE(ring);
3951 for (i = 0; i < size; i++) {
3952 if (page[i]) {
3953 cas_page_free(cp, page[i]);
3954 page[i] = NULL;
3955 }
3956 }
3957}
3958
3959static void cas_free_rxds(struct cas *cp)
3960{
3961 int i;
3962
3963 for (i = 0; i < N_RX_DESC_RINGS; i++)
3964 cas_free_rx_desc(cp, i);
3965}
3966
3967
3968static void cas_clean_rings(struct cas *cp)
3969{
3970 int i;
3971
3972
3973 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
3974 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
3975 for (i = 0; i < N_TX_RINGS; i++)
3976 cas_clean_txd(cp, i);
3977
3978
3979 memset(cp->init_block, 0, sizeof(struct cas_init_block));
3980 cas_clean_rxds(cp);
3981 cas_clean_rxcs(cp);
3982}
3983
3984
3985static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
3986{
3987 cas_page_t **page = cp->rx_pages[ring];
3988 int size, i = 0;
3989
3990 size = RX_DESC_RINGN_SIZE(ring);
3991 for (i = 0; i < size; i++) {
3992 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
3993 return -1;
3994 }
3995 return 0;
3996}
3997
3998static int cas_alloc_rxds(struct cas *cp)
3999{
4000 int i;
4001
4002 for (i = 0; i < N_RX_DESC_RINGS; i++) {
4003 if (cas_alloc_rx_desc(cp, i) < 0) {
4004 cas_free_rxds(cp);
4005 return -1;
4006 }
4007 }
4008 return 0;
4009}
4010
4011static void cas_reset_task(struct work_struct *work)
4012{
4013 struct cas *cp = container_of(work, struct cas, reset_task);
4014#if 0
4015 int pending = atomic_read(&cp->reset_task_pending);
4016#else
4017 int pending_all = atomic_read(&cp->reset_task_pending_all);
4018 int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4019 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4020
4021 if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4022
4023
4024
4025 atomic_dec(&cp->reset_task_pending);
4026 return;
4027 }
4028#endif
4029
4030
4031
4032
4033 if (cp->hw_running) {
4034 unsigned long flags;
4035
4036
4037 netif_device_detach(cp->dev);
4038 cas_lock_all_save(cp, flags);
4039
4040 if (cp->opened) {
4041
4042
4043
4044
4045 cas_spare_recover(cp, GFP_ATOMIC);
4046 }
4047#if 1
4048
4049 if (!pending_all && !pending_mtu)
4050 goto done;
4051#else
4052 if (pending == CAS_RESET_SPARE)
4053 goto done;
4054#endif
4055
4056
4057
4058
4059
4060
4061
4062#if 1
4063 cas_reset(cp, !(pending_all > 0));
4064 if (cp->opened)
4065 cas_clean_rings(cp);
4066 cas_init_hw(cp, (pending_all > 0));
4067#else
4068 cas_reset(cp, !(pending == CAS_RESET_ALL));
4069 if (cp->opened)
4070 cas_clean_rings(cp);
4071 cas_init_hw(cp, pending == CAS_RESET_ALL);
4072#endif
4073
4074done:
4075 cas_unlock_all_restore(cp, flags);
4076 netif_device_attach(cp->dev);
4077 }
4078#if 1
4079 atomic_sub(pending_all, &cp->reset_task_pending_all);
4080 atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4081 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4082 atomic_dec(&cp->reset_task_pending);
4083#else
4084 atomic_set(&cp->reset_task_pending, 0);
4085#endif
4086}
4087
4088static void cas_link_timer(unsigned long data)
4089{
4090 struct cas *cp = (struct cas *) data;
4091 int mask, pending = 0, reset = 0;
4092 unsigned long flags;
4093
4094 if (link_transition_timeout != 0 &&
4095 cp->link_transition_jiffies_valid &&
4096 ((jiffies - cp->link_transition_jiffies) >
4097 (link_transition_timeout))) {
4098
4099
4100
4101
4102 cp->link_transition_jiffies_valid = 0;
4103 }
4104
4105 if (!cp->hw_running)
4106 return;
4107
4108 spin_lock_irqsave(&cp->lock, flags);
4109 cas_lock_tx(cp);
4110 cas_entropy_gather(cp);
4111
4112
4113
4114
4115#if 1
4116 if (atomic_read(&cp->reset_task_pending_all) ||
4117 atomic_read(&cp->reset_task_pending_spare) ||
4118 atomic_read(&cp->reset_task_pending_mtu))
4119 goto done;
4120#else
4121 if (atomic_read(&cp->reset_task_pending))
4122 goto done;
4123#endif
4124
4125
4126 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4127 int i, rmask;
4128
4129 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4130 rmask = CAS_FLAG_RXD_POST(i);
4131 if ((mask & rmask) == 0)
4132 continue;
4133
4134
4135 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4136 pending = 1;
4137 continue;
4138 }
4139 cp->cas_flags &= ~rmask;
4140 }
4141 }
4142
4143 if (CAS_PHY_MII(cp->phy_type)) {
4144 u16 bmsr;
4145 cas_mif_poll(cp, 0);
4146 bmsr = cas_phy_read(cp, MII_BMSR);
4147
4148
4149
4150
4151
4152 bmsr = cas_phy_read(cp, MII_BMSR);
4153 cas_mif_poll(cp, 1);
4154 readl(cp->regs + REG_MIF_STATUS);
4155 reset = cas_mii_link_check(cp, bmsr);
4156 } else {
4157 reset = cas_pcs_link_check(cp);
4158 }
4159
4160 if (reset)
4161 goto done;
4162
4163
4164 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4165 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4166 u32 wptr, rptr;
4167 int tlm = CAS_VAL(MAC_SM_TLM, val);
4168
4169 if (((tlm == 0x5) || (tlm == 0x3)) &&
4170 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4171 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4172 "tx err: MAC_STATE[%08x]\n", val);
4173 reset = 1;
4174 goto done;
4175 }
4176
4177 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4178 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4179 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4180 if ((val == 0) && (wptr != rptr)) {
4181 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4182 "tx err: TX_FIFO[%08x:%08x:%08x]\n",
4183 val, wptr, rptr);
4184 reset = 1;
4185 }
4186
4187 if (reset)
4188 cas_hard_reset(cp);
4189 }
4190
4191done:
4192 if (reset) {
4193#if 1
4194 atomic_inc(&cp->reset_task_pending);
4195 atomic_inc(&cp->reset_task_pending_all);
4196 schedule_work(&cp->reset_task);
4197#else
4198 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4199 pr_err("reset called in cas_link_timer\n");
4200 schedule_work(&cp->reset_task);
4201#endif
4202 }
4203
4204 if (!pending)
4205 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4206 cas_unlock_tx(cp);
4207 spin_unlock_irqrestore(&cp->lock, flags);
4208}
4209
4210
4211
4212
4213static void cas_tx_tiny_free(struct cas *cp)
4214{
4215 struct pci_dev *pdev = cp->pdev;
4216 int i;
4217
4218 for (i = 0; i < N_TX_RINGS; i++) {
4219 if (!cp->tx_tiny_bufs[i])
4220 continue;
4221
4222 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4223 cp->tx_tiny_bufs[i],
4224 cp->tx_tiny_dvma[i]);
4225 cp->tx_tiny_bufs[i] = NULL;
4226 }
4227}
4228
4229static int cas_tx_tiny_alloc(struct cas *cp)
4230{
4231 struct pci_dev *pdev = cp->pdev;
4232 int i;
4233
4234 for (i = 0; i < N_TX_RINGS; i++) {
4235 cp->tx_tiny_bufs[i] =
4236 pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4237 &cp->tx_tiny_dvma[i]);
4238 if (!cp->tx_tiny_bufs[i]) {
4239 cas_tx_tiny_free(cp);
4240 return -1;
4241 }
4242 }
4243 return 0;
4244}
4245
4246
4247static int cas_open(struct net_device *dev)
4248{
4249 struct cas *cp = netdev_priv(dev);
4250 int hw_was_up, err;
4251 unsigned long flags;
4252
4253 mutex_lock(&cp->pm_mutex);
4254
4255 hw_was_up = cp->hw_running;
4256
4257
4258
4259
4260 if (!cp->hw_running) {
4261
4262 cas_lock_all_save(cp, flags);
4263
4264
4265
4266
4267
4268 cas_reset(cp, 0);
4269 cp->hw_running = 1;
4270 cas_unlock_all_restore(cp, flags);
4271 }
4272
4273 err = -ENOMEM;
4274 if (cas_tx_tiny_alloc(cp) < 0)
4275 goto err_unlock;
4276
4277
4278 if (cas_alloc_rxds(cp) < 0)
4279 goto err_tx_tiny;
4280
4281
4282 cas_spare_init(cp);
4283 cas_spare_recover(cp, GFP_KERNEL);
4284
4285
4286
4287
4288
4289
4290 if (request_irq(cp->pdev->irq, cas_interrupt,
4291 IRQF_SHARED, dev->name, (void *) dev)) {
4292 netdev_err(cp->dev, "failed to request irq !\n");
4293 err = -EAGAIN;
4294 goto err_spare;
4295 }
4296
4297#ifdef USE_NAPI
4298 napi_enable(&cp->napi);
4299#endif
4300
4301 cas_lock_all_save(cp, flags);
4302 cas_clean_rings(cp);
4303 cas_init_hw(cp, !hw_was_up);
4304 cp->opened = 1;
4305 cas_unlock_all_restore(cp, flags);
4306
4307 netif_start_queue(dev);
4308 mutex_unlock(&cp->pm_mutex);
4309 return 0;
4310
4311err_spare:
4312 cas_spare_free(cp);
4313 cas_free_rxds(cp);
4314err_tx_tiny:
4315 cas_tx_tiny_free(cp);
4316err_unlock:
4317 mutex_unlock(&cp->pm_mutex);
4318 return err;
4319}
4320
4321static int cas_close(struct net_device *dev)
4322{
4323 unsigned long flags;
4324 struct cas *cp = netdev_priv(dev);
4325
4326#ifdef USE_NAPI
4327 napi_disable(&cp->napi);
4328#endif
4329
4330 mutex_lock(&cp->pm_mutex);
4331
4332 netif_stop_queue(dev);
4333
4334
4335 cas_lock_all_save(cp, flags);
4336 cp->opened = 0;
4337 cas_reset(cp, 0);
4338 cas_phy_init(cp);
4339 cas_begin_auto_negotiation(cp, NULL);
4340 cas_clean_rings(cp);
4341 cas_unlock_all_restore(cp, flags);
4342
4343 free_irq(cp->pdev->irq, (void *) dev);
4344 cas_spare_free(cp);
4345 cas_free_rxds(cp);
4346 cas_tx_tiny_free(cp);
4347 mutex_unlock(&cp->pm_mutex);
4348 return 0;
4349}
4350
4351static struct {
4352 const char name[ETH_GSTRING_LEN];
4353} ethtool_cassini_statnames[] = {
4354 {"collisions"},
4355 {"rx_bytes"},
4356 {"rx_crc_errors"},
4357 {"rx_dropped"},
4358 {"rx_errors"},
4359 {"rx_fifo_errors"},
4360 {"rx_frame_errors"},
4361 {"rx_length_errors"},
4362 {"rx_over_errors"},
4363 {"rx_packets"},
4364 {"tx_aborted_errors"},
4365 {"tx_bytes"},
4366 {"tx_dropped"},
4367 {"tx_errors"},
4368 {"tx_fifo_errors"},
4369 {"tx_packets"}
4370};
4371#define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
4372
4373static struct {
4374 const int offsets;
4375} ethtool_register_table[] = {
4376 {-MII_BMSR},
4377 {-MII_BMCR},
4378 {REG_CAWR},
4379 {REG_INF_BURST},
4380 {REG_BIM_CFG},
4381 {REG_RX_CFG},
4382 {REG_HP_CFG},
4383 {REG_MAC_TX_CFG},
4384 {REG_MAC_RX_CFG},
4385 {REG_MAC_CTRL_CFG},
4386 {REG_MAC_XIF_CFG},
4387 {REG_MIF_CFG},
4388 {REG_PCS_CFG},
4389 {REG_SATURN_PCFG},
4390 {REG_PCS_MII_STATUS},
4391 {REG_PCS_STATE_MACHINE},
4392 {REG_MAC_COLL_EXCESS},
4393 {REG_MAC_COLL_LATE}
4394};
4395#define CAS_REG_LEN ARRAY_SIZE(ethtool_register_table)
4396#define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN)
4397
4398static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4399{
4400 u8 *p;
4401 int i;
4402 unsigned long flags;
4403
4404 spin_lock_irqsave(&cp->lock, flags);
4405 for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4406 u16 hval;
4407 u32 val;
4408 if (ethtool_register_table[i].offsets < 0) {
4409 hval = cas_phy_read(cp,
4410 -ethtool_register_table[i].offsets);
4411 val = hval;
4412 } else {
4413 val= readl(cp->regs+ethtool_register_table[i].offsets);
4414 }
4415 memcpy(p, (u8 *)&val, sizeof(u32));
4416 }
4417 spin_unlock_irqrestore(&cp->lock, flags);
4418}
4419
4420static struct net_device_stats *cas_get_stats(struct net_device *dev)
4421{
4422 struct cas *cp = netdev_priv(dev);
4423 struct net_device_stats *stats = cp->net_stats;
4424 unsigned long flags;
4425 int i;
4426 unsigned long tmp;
4427
4428
4429 if (!cp->hw_running)
4430 return stats + N_TX_RINGS;
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4441 stats[N_TX_RINGS].rx_crc_errors +=
4442 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4443 stats[N_TX_RINGS].rx_frame_errors +=
4444 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4445 stats[N_TX_RINGS].rx_length_errors +=
4446 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4447#if 1
4448 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4449 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4450 stats[N_TX_RINGS].tx_aborted_errors += tmp;
4451 stats[N_TX_RINGS].collisions +=
4452 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4453#else
4454 stats[N_TX_RINGS].tx_aborted_errors +=
4455 readl(cp->regs + REG_MAC_COLL_EXCESS);
4456 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4457 readl(cp->regs + REG_MAC_COLL_LATE);
4458#endif
4459 cas_clear_mac_err(cp);
4460
4461
4462 spin_lock(&cp->stat_lock[0]);
4463 stats[N_TX_RINGS].collisions += stats[0].collisions;
4464 stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors;
4465 stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors;
4466 stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors;
4467 stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4468 stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors;
4469 spin_unlock(&cp->stat_lock[0]);
4470
4471 for (i = 0; i < N_TX_RINGS; i++) {
4472 spin_lock(&cp->stat_lock[i]);
4473 stats[N_TX_RINGS].rx_length_errors +=
4474 stats[i].rx_length_errors;
4475 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4476 stats[N_TX_RINGS].rx_packets += stats[i].rx_packets;
4477 stats[N_TX_RINGS].tx_packets += stats[i].tx_packets;
4478 stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes;
4479 stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes;
4480 stats[N_TX_RINGS].rx_errors += stats[i].rx_errors;
4481 stats[N_TX_RINGS].tx_errors += stats[i].tx_errors;
4482 stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped;
4483 stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped;
4484 memset(stats + i, 0, sizeof(struct net_device_stats));
4485 spin_unlock(&cp->stat_lock[i]);
4486 }
4487 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4488 return stats + N_TX_RINGS;
4489}
4490
4491
4492static void cas_set_multicast(struct net_device *dev)
4493{
4494 struct cas *cp = netdev_priv(dev);
4495 u32 rxcfg, rxcfg_new;
4496 unsigned long flags;
4497 int limit = STOP_TRIES;
4498
4499 if (!cp->hw_running)
4500 return;
4501
4502 spin_lock_irqsave(&cp->lock, flags);
4503 rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4504
4505
4506 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4507 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4508 if (!limit--)
4509 break;
4510 udelay(10);
4511 }
4512
4513
4514 limit = STOP_TRIES;
4515 rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4516 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4517 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4518 if (!limit--)
4519 break;
4520 udelay(10);
4521 }
4522
4523
4524 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4525 rxcfg |= rxcfg_new;
4526 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4527 spin_unlock_irqrestore(&cp->lock, flags);
4528}
4529
4530static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4531{
4532 struct cas *cp = netdev_priv(dev);
4533 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
4534 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
4535 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
4536 info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
4537 cp->casreg_len : CAS_MAX_REGS;
4538 info->n_stats = CAS_NUM_STAT_KEYS;
4539}
4540
4541static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4542{
4543 struct cas *cp = netdev_priv(dev);
4544 u16 bmcr;
4545 int full_duplex, speed, pause;
4546 unsigned long flags;
4547 enum link_state linkstate = link_up;
4548
4549 cmd->advertising = 0;
4550 cmd->supported = SUPPORTED_Autoneg;
4551 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4552 cmd->supported |= SUPPORTED_1000baseT_Full;
4553 cmd->advertising |= ADVERTISED_1000baseT_Full;
4554 }
4555
4556
4557 spin_lock_irqsave(&cp->lock, flags);
4558 bmcr = 0;
4559 linkstate = cp->lstate;
4560 if (CAS_PHY_MII(cp->phy_type)) {
4561 cmd->port = PORT_MII;
4562 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
4563 XCVR_INTERNAL : XCVR_EXTERNAL;
4564 cmd->phy_address = cp->phy_addr;
4565 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
4566 ADVERTISED_10baseT_Half |
4567 ADVERTISED_10baseT_Full |
4568 ADVERTISED_100baseT_Half |
4569 ADVERTISED_100baseT_Full;
4570
4571 cmd->supported |=
4572 (SUPPORTED_10baseT_Half |
4573 SUPPORTED_10baseT_Full |
4574 SUPPORTED_100baseT_Half |
4575 SUPPORTED_100baseT_Full |
4576 SUPPORTED_TP | SUPPORTED_MII);
4577
4578 if (cp->hw_running) {
4579 cas_mif_poll(cp, 0);
4580 bmcr = cas_phy_read(cp, MII_BMCR);
4581 cas_read_mii_link_mode(cp, &full_duplex,
4582 &speed, &pause);
4583 cas_mif_poll(cp, 1);
4584 }
4585
4586 } else {
4587 cmd->port = PORT_FIBRE;
4588 cmd->transceiver = XCVR_INTERNAL;
4589 cmd->phy_address = 0;
4590 cmd->supported |= SUPPORTED_FIBRE;
4591 cmd->advertising |= ADVERTISED_FIBRE;
4592
4593 if (cp->hw_running) {
4594
4595 bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4596 cas_read_pcs_link_mode(cp, &full_duplex,
4597 &speed, &pause);
4598 }
4599 }
4600 spin_unlock_irqrestore(&cp->lock, flags);
4601
4602 if (bmcr & BMCR_ANENABLE) {
4603 cmd->advertising |= ADVERTISED_Autoneg;
4604 cmd->autoneg = AUTONEG_ENABLE;
4605 ethtool_cmd_speed_set(cmd, ((speed == 10) ?
4606 SPEED_10 :
4607 ((speed == 1000) ?
4608 SPEED_1000 : SPEED_100)));
4609 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4610 } else {
4611 cmd->autoneg = AUTONEG_DISABLE;
4612 ethtool_cmd_speed_set(cmd, ((bmcr & CAS_BMCR_SPEED1000) ?
4613 SPEED_1000 :
4614 ((bmcr & BMCR_SPEED100) ?
4615 SPEED_100 : SPEED_10)));
4616 cmd->duplex =
4617 (bmcr & BMCR_FULLDPLX) ?
4618 DUPLEX_FULL : DUPLEX_HALF;
4619 }
4620 if (linkstate != link_up) {
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631 if (cp->link_cntl & BMCR_ANENABLE) {
4632 ethtool_cmd_speed_set(cmd, 0);
4633 cmd->duplex = 0xff;
4634 } else {
4635 ethtool_cmd_speed_set(cmd, SPEED_10);
4636 if (cp->link_cntl & BMCR_SPEED100) {
4637 ethtool_cmd_speed_set(cmd, SPEED_100);
4638 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4639 ethtool_cmd_speed_set(cmd, SPEED_1000);
4640 }
4641 cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
4642 DUPLEX_FULL : DUPLEX_HALF;
4643 }
4644 }
4645 return 0;
4646}
4647
4648static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4649{
4650 struct cas *cp = netdev_priv(dev);
4651 unsigned long flags;
4652 u32 speed = ethtool_cmd_speed(cmd);
4653
4654
4655 if (cmd->autoneg != AUTONEG_ENABLE &&
4656 cmd->autoneg != AUTONEG_DISABLE)
4657 return -EINVAL;
4658
4659 if (cmd->autoneg == AUTONEG_DISABLE &&
4660 ((speed != SPEED_1000 &&
4661 speed != SPEED_100 &&
4662 speed != SPEED_10) ||
4663 (cmd->duplex != DUPLEX_HALF &&
4664 cmd->duplex != DUPLEX_FULL)))
4665 return -EINVAL;
4666
4667
4668 spin_lock_irqsave(&cp->lock, flags);
4669 cas_begin_auto_negotiation(cp, cmd);
4670 spin_unlock_irqrestore(&cp->lock, flags);
4671 return 0;
4672}
4673
4674static int cas_nway_reset(struct net_device *dev)
4675{
4676 struct cas *cp = netdev_priv(dev);
4677 unsigned long flags;
4678
4679 if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4680 return -EINVAL;
4681
4682
4683 spin_lock_irqsave(&cp->lock, flags);
4684 cas_begin_auto_negotiation(cp, NULL);
4685 spin_unlock_irqrestore(&cp->lock, flags);
4686
4687 return 0;
4688}
4689
4690static u32 cas_get_link(struct net_device *dev)
4691{
4692 struct cas *cp = netdev_priv(dev);
4693 return cp->lstate == link_up;
4694}
4695
4696static u32 cas_get_msglevel(struct net_device *dev)
4697{
4698 struct cas *cp = netdev_priv(dev);
4699 return cp->msg_enable;
4700}
4701
4702static void cas_set_msglevel(struct net_device *dev, u32 value)
4703{
4704 struct cas *cp = netdev_priv(dev);
4705 cp->msg_enable = value;
4706}
4707
4708static int cas_get_regs_len(struct net_device *dev)
4709{
4710 struct cas *cp = netdev_priv(dev);
4711 return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4712}
4713
4714static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4715 void *p)
4716{
4717 struct cas *cp = netdev_priv(dev);
4718 regs->version = 0;
4719
4720 cas_read_regs(cp, p, regs->len / sizeof(u32));
4721}
4722
4723static int cas_get_sset_count(struct net_device *dev, int sset)
4724{
4725 switch (sset) {
4726 case ETH_SS_STATS:
4727 return CAS_NUM_STAT_KEYS;
4728 default:
4729 return -EOPNOTSUPP;
4730 }
4731}
4732
4733static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4734{
4735 memcpy(data, ðtool_cassini_statnames,
4736 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4737}
4738
4739static void cas_get_ethtool_stats(struct net_device *dev,
4740 struct ethtool_stats *estats, u64 *data)
4741{
4742 struct cas *cp = netdev_priv(dev);
4743 struct net_device_stats *stats = cas_get_stats(cp->dev);
4744 int i = 0;
4745 data[i++] = stats->collisions;
4746 data[i++] = stats->rx_bytes;
4747 data[i++] = stats->rx_crc_errors;
4748 data[i++] = stats->rx_dropped;
4749 data[i++] = stats->rx_errors;
4750 data[i++] = stats->rx_fifo_errors;
4751 data[i++] = stats->rx_frame_errors;
4752 data[i++] = stats->rx_length_errors;
4753 data[i++] = stats->rx_over_errors;
4754 data[i++] = stats->rx_packets;
4755 data[i++] = stats->tx_aborted_errors;
4756 data[i++] = stats->tx_bytes;
4757 data[i++] = stats->tx_dropped;
4758 data[i++] = stats->tx_errors;
4759 data[i++] = stats->tx_fifo_errors;
4760 data[i++] = stats->tx_packets;
4761 BUG_ON(i != CAS_NUM_STAT_KEYS);
4762}
4763
4764static const struct ethtool_ops cas_ethtool_ops = {
4765 .get_drvinfo = cas_get_drvinfo,
4766 .get_settings = cas_get_settings,
4767 .set_settings = cas_set_settings,
4768 .nway_reset = cas_nway_reset,
4769 .get_link = cas_get_link,
4770 .get_msglevel = cas_get_msglevel,
4771 .set_msglevel = cas_set_msglevel,
4772 .get_regs_len = cas_get_regs_len,
4773 .get_regs = cas_get_regs,
4774 .get_sset_count = cas_get_sset_count,
4775 .get_strings = cas_get_strings,
4776 .get_ethtool_stats = cas_get_ethtool_stats,
4777};
4778
4779static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4780{
4781 struct cas *cp = netdev_priv(dev);
4782 struct mii_ioctl_data *data = if_mii(ifr);
4783 unsigned long flags;
4784 int rc = -EOPNOTSUPP;
4785
4786
4787
4788
4789 mutex_lock(&cp->pm_mutex);
4790 switch (cmd) {
4791 case SIOCGMIIPHY:
4792 data->phy_id = cp->phy_addr;
4793
4794
4795 case SIOCGMIIREG:
4796 spin_lock_irqsave(&cp->lock, flags);
4797 cas_mif_poll(cp, 0);
4798 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4799 cas_mif_poll(cp, 1);
4800 spin_unlock_irqrestore(&cp->lock, flags);
4801 rc = 0;
4802 break;
4803
4804 case SIOCSMIIREG:
4805 spin_lock_irqsave(&cp->lock, flags);
4806 cas_mif_poll(cp, 0);
4807 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4808 cas_mif_poll(cp, 1);
4809 spin_unlock_irqrestore(&cp->lock, flags);
4810 break;
4811 default:
4812 break;
4813 }
4814
4815 mutex_unlock(&cp->pm_mutex);
4816 return rc;
4817}
4818
4819
4820
4821
4822
4823static void cas_program_bridge(struct pci_dev *cas_pdev)
4824{
4825 struct pci_dev *pdev = cas_pdev->bus->self;
4826 u32 val;
4827
4828 if (!pdev)
4829 return;
4830
4831 if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4832 return;
4833
4834
4835
4836
4837
4838
4839 pci_read_config_dword(pdev, 0x40, &val);
4840 val &= ~0x00040000;
4841 pci_write_config_dword(pdev, 0x40, val);
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865 pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887 pci_write_config_word(pdev, 0x52,
4888 (0x7 << 13) |
4889 (0x7 << 10) |
4890 (0x7 << 7) |
4891 (0x7 << 4) |
4892 (0xf << 0));
4893
4894
4895 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4896
4897
4898
4899
4900 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4901}
4902
4903static const struct net_device_ops cas_netdev_ops = {
4904 .ndo_open = cas_open,
4905 .ndo_stop = cas_close,
4906 .ndo_start_xmit = cas_start_xmit,
4907 .ndo_get_stats = cas_get_stats,
4908 .ndo_set_rx_mode = cas_set_multicast,
4909 .ndo_do_ioctl = cas_ioctl,
4910 .ndo_tx_timeout = cas_tx_timeout,
4911 .ndo_change_mtu = cas_change_mtu,
4912 .ndo_set_mac_address = eth_mac_addr,
4913 .ndo_validate_addr = eth_validate_addr,
4914#ifdef CONFIG_NET_POLL_CONTROLLER
4915 .ndo_poll_controller = cas_netpoll,
4916#endif
4917};
4918
4919static int cas_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4920{
4921 static int cas_version_printed = 0;
4922 unsigned long casreg_len;
4923 struct net_device *dev;
4924 struct cas *cp;
4925 int i, err, pci_using_dac;
4926 u16 pci_cmd;
4927 u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4928
4929 if (cas_version_printed++ == 0)
4930 pr_info("%s", version);
4931
4932 err = pci_enable_device(pdev);
4933 if (err) {
4934 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
4935 return err;
4936 }
4937
4938 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4939 dev_err(&pdev->dev, "Cannot find proper PCI device "
4940 "base address, aborting\n");
4941 err = -ENODEV;
4942 goto err_out_disable_pdev;
4943 }
4944
4945 dev = alloc_etherdev(sizeof(*cp));
4946 if (!dev) {
4947 err = -ENOMEM;
4948 goto err_out_disable_pdev;
4949 }
4950 SET_NETDEV_DEV(dev, &pdev->dev);
4951
4952 err = pci_request_regions(pdev, dev->name);
4953 if (err) {
4954 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
4955 goto err_out_free_netdev;
4956 }
4957 pci_set_master(pdev);
4958
4959
4960
4961
4962
4963 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4964 pci_cmd &= ~PCI_COMMAND_SERR;
4965 pci_cmd |= PCI_COMMAND_PARITY;
4966 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4967 if (pci_try_set_mwi(pdev))
4968 pr_warning("Could not enable MWI for %s\n", pci_name(pdev));
4969
4970 cas_program_bridge(pdev);
4971
4972
4973
4974
4975
4976
4977
4978#if 1
4979 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4980 &orig_cacheline_size);
4981 if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4982 cas_cacheline_size =
4983 (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
4984 CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
4985 if (pci_write_config_byte(pdev,
4986 PCI_CACHE_LINE_SIZE,
4987 cas_cacheline_size)) {
4988 dev_err(&pdev->dev, "Could not set PCI cache "
4989 "line size\n");
4990 goto err_write_cacheline;
4991 }
4992 }
4993#endif
4994
4995
4996
4997 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4998 pci_using_dac = 1;
4999 err = pci_set_consistent_dma_mask(pdev,
5000 DMA_BIT_MASK(64));
5001 if (err < 0) {
5002 dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
5003 "for consistent allocations\n");
5004 goto err_out_free_res;
5005 }
5006
5007 } else {
5008 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5009 if (err) {
5010 dev_err(&pdev->dev, "No usable DMA configuration, "
5011 "aborting\n");
5012 goto err_out_free_res;
5013 }
5014 pci_using_dac = 0;
5015 }
5016
5017 casreg_len = pci_resource_len(pdev, 0);
5018
5019 cp = netdev_priv(dev);
5020 cp->pdev = pdev;
5021#if 1
5022
5023 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
5024#endif
5025 cp->dev = dev;
5026 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
5027 cassini_debug;
5028
5029#if defined(CONFIG_SPARC)
5030 cp->of_node = pci_device_to_OF_node(pdev);
5031#endif
5032
5033 cp->link_transition = LINK_TRANSITION_UNKNOWN;
5034 cp->link_transition_jiffies_valid = 0;
5035
5036 spin_lock_init(&cp->lock);
5037 spin_lock_init(&cp->rx_inuse_lock);
5038 spin_lock_init(&cp->rx_spare_lock);
5039 for (i = 0; i < N_TX_RINGS; i++) {
5040 spin_lock_init(&cp->stat_lock[i]);
5041 spin_lock_init(&cp->tx_lock[i]);
5042 }
5043 spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
5044 mutex_init(&cp->pm_mutex);
5045
5046 init_timer(&cp->link_timer);
5047 cp->link_timer.function = cas_link_timer;
5048 cp->link_timer.data = (unsigned long) cp;
5049
5050#if 1
5051
5052
5053
5054 atomic_set(&cp->reset_task_pending, 0);
5055 atomic_set(&cp->reset_task_pending_all, 0);
5056 atomic_set(&cp->reset_task_pending_spare, 0);
5057 atomic_set(&cp->reset_task_pending_mtu, 0);
5058#endif
5059 INIT_WORK(&cp->reset_task, cas_reset_task);
5060
5061
5062 if (link_mode >= 0 && link_mode < 6)
5063 cp->link_cntl = link_modes[link_mode];
5064 else
5065 cp->link_cntl = BMCR_ANENABLE;
5066 cp->lstate = link_down;
5067 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5068 netif_carrier_off(cp->dev);
5069 cp->timer_ticks = 0;
5070
5071
5072 cp->regs = pci_iomap(pdev, 0, casreg_len);
5073 if (!cp->regs) {
5074 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5075 goto err_out_free_res;
5076 }
5077 cp->casreg_len = casreg_len;
5078
5079 pci_save_state(pdev);
5080 cas_check_pci_invariants(cp);
5081 cas_hard_reset(cp);
5082 cas_reset(cp, 0);
5083 if (cas_check_invariants(cp))
5084 goto err_out_iounmap;
5085 if (cp->cas_flags & CAS_FLAG_SATURN)
5086 if (cas_saturn_firmware_init(cp))
5087 goto err_out_iounmap;
5088
5089 cp->init_block = (struct cas_init_block *)
5090 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5091 &cp->block_dvma);
5092 if (!cp->init_block) {
5093 dev_err(&pdev->dev, "Cannot allocate init block, aborting\n");
5094 goto err_out_iounmap;
5095 }
5096
5097 for (i = 0; i < N_TX_RINGS; i++)
5098 cp->init_txds[i] = cp->init_block->txds[i];
5099
5100 for (i = 0; i < N_RX_DESC_RINGS; i++)
5101 cp->init_rxds[i] = cp->init_block->rxds[i];
5102
5103 for (i = 0; i < N_RX_COMP_RINGS; i++)
5104 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5105
5106 for (i = 0; i < N_RX_FLOWS; i++)
5107 skb_queue_head_init(&cp->rx_flows[i]);
5108
5109 dev->netdev_ops = &cas_netdev_ops;
5110 dev->ethtool_ops = &cas_ethtool_ops;
5111 dev->watchdog_timeo = CAS_TX_TIMEOUT;
5112
5113#ifdef USE_NAPI
5114 netif_napi_add(dev, &cp->napi, cas_poll, 64);
5115#endif
5116 dev->irq = pdev->irq;
5117 dev->dma = 0;
5118
5119
5120 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5121 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5122
5123 if (pci_using_dac)
5124 dev->features |= NETIF_F_HIGHDMA;
5125
5126 if (register_netdev(dev)) {
5127 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
5128 goto err_out_free_consistent;
5129 }
5130
5131 i = readl(cp->regs + REG_BIM_CFG);
5132 netdev_info(dev, "Sun Cassini%s (%sbit/%sMHz PCI/%s) Ethernet[%d] %pM\n",
5133 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5134 (i & BIM_CFG_32BIT) ? "32" : "64",
5135 (i & BIM_CFG_66MHZ) ? "66" : "33",
5136 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
5137 dev->dev_addr);
5138
5139 pci_set_drvdata(pdev, dev);
5140 cp->hw_running = 1;
5141 cas_entropy_reset(cp);
5142 cas_phy_init(cp);
5143 cas_begin_auto_negotiation(cp, NULL);
5144 return 0;
5145
5146err_out_free_consistent:
5147 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5148 cp->init_block, cp->block_dvma);
5149
5150err_out_iounmap:
5151 mutex_lock(&cp->pm_mutex);
5152 if (cp->hw_running)
5153 cas_shutdown(cp);
5154 mutex_unlock(&cp->pm_mutex);
5155
5156 pci_iounmap(pdev, cp->regs);
5157
5158
5159err_out_free_res:
5160 pci_release_regions(pdev);
5161
5162err_write_cacheline:
5163
5164
5165
5166 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5167
5168err_out_free_netdev:
5169 free_netdev(dev);
5170
5171err_out_disable_pdev:
5172 pci_disable_device(pdev);
5173 pci_set_drvdata(pdev, NULL);
5174 return -ENODEV;
5175}
5176
5177static void cas_remove_one(struct pci_dev *pdev)
5178{
5179 struct net_device *dev = pci_get_drvdata(pdev);
5180 struct cas *cp;
5181 if (!dev)
5182 return;
5183
5184 cp = netdev_priv(dev);
5185 unregister_netdev(dev);
5186
5187 if (cp->fw_data)
5188 vfree(cp->fw_data);
5189
5190 mutex_lock(&cp->pm_mutex);
5191 cancel_work_sync(&cp->reset_task);
5192 if (cp->hw_running)
5193 cas_shutdown(cp);
5194 mutex_unlock(&cp->pm_mutex);
5195
5196#if 1
5197 if (cp->orig_cacheline_size) {
5198
5199
5200
5201 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5202 cp->orig_cacheline_size);
5203 }
5204#endif
5205 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5206 cp->init_block, cp->block_dvma);
5207 pci_iounmap(pdev, cp->regs);
5208 free_netdev(dev);
5209 pci_release_regions(pdev);
5210 pci_disable_device(pdev);
5211 pci_set_drvdata(pdev, NULL);
5212}
5213
5214#ifdef CONFIG_PM
5215static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5216{
5217 struct net_device *dev = pci_get_drvdata(pdev);
5218 struct cas *cp = netdev_priv(dev);
5219 unsigned long flags;
5220
5221 mutex_lock(&cp->pm_mutex);
5222
5223
5224 if (cp->opened) {
5225 netif_device_detach(dev);
5226
5227 cas_lock_all_save(cp, flags);
5228
5229
5230
5231
5232
5233
5234 cas_reset(cp, 0);
5235 cas_clean_rings(cp);
5236 cas_unlock_all_restore(cp, flags);
5237 }
5238
5239 if (cp->hw_running)
5240 cas_shutdown(cp);
5241 mutex_unlock(&cp->pm_mutex);
5242
5243 return 0;
5244}
5245
5246static int cas_resume(struct pci_dev *pdev)
5247{
5248 struct net_device *dev = pci_get_drvdata(pdev);
5249 struct cas *cp = netdev_priv(dev);
5250
5251 netdev_info(dev, "resuming\n");
5252
5253 mutex_lock(&cp->pm_mutex);
5254 cas_hard_reset(cp);
5255 if (cp->opened) {
5256 unsigned long flags;
5257 cas_lock_all_save(cp, flags);
5258 cas_reset(cp, 0);
5259 cp->hw_running = 1;
5260 cas_clean_rings(cp);
5261 cas_init_hw(cp, 1);
5262 cas_unlock_all_restore(cp, flags);
5263
5264 netif_device_attach(dev);
5265 }
5266 mutex_unlock(&cp->pm_mutex);
5267 return 0;
5268}
5269#endif
5270
5271static struct pci_driver cas_driver = {
5272 .name = DRV_MODULE_NAME,
5273 .id_table = cas_pci_tbl,
5274 .probe = cas_init_one,
5275 .remove = cas_remove_one,
5276#ifdef CONFIG_PM
5277 .suspend = cas_suspend,
5278 .resume = cas_resume
5279#endif
5280};
5281
5282static int __init cas_init(void)
5283{
5284 if (linkdown_timeout > 0)
5285 link_transition_timeout = linkdown_timeout * HZ;
5286 else
5287 link_transition_timeout = 0;
5288
5289 return pci_register_driver(&cas_driver);
5290}
5291
5292static void __exit cas_cleanup(void)
5293{
5294 pci_unregister_driver(&cas_driver);
5295}
5296
5297module_init(cas_init);
5298module_exit(cas_cleanup);
5299