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7#ifndef _SUNBMAC_H
8#define _SUNBMAC_H
9
10
11#define GLOB_CTRL 0x00UL
12#define GLOB_STAT 0x04UL
13#define GLOB_PSIZE 0x08UL
14#define GLOB_MSIZE 0x0cUL
15#define GLOB_RSIZE 0x10UL
16#define GLOB_TSIZE 0x14UL
17#define GLOB_REG_SIZE 0x18UL
18
19#define GLOB_CTRL_MMODE 0x40000000
20#define GLOB_CTRL_BMODE 0x10000000
21#define GLOB_CTRL_EPAR 0x00000020
22#define GLOB_CTRL_ACNTRL 0x00000018
23#define GLOB_CTRL_B64 0x00000004
24#define GLOB_CTRL_B32 0x00000002
25#define GLOB_CTRL_B16 0x00000000
26#define GLOB_CTRL_RESET 0x00000001
27
28#define GLOB_STAT_TX 0x00000008
29#define GLOB_STAT_RX 0x00000004
30#define GLOB_STAT_BM 0x00000002
31#define GLOB_STAT_ER 0x00000001
32
33#define GLOB_PSIZE_2048 0x00
34#define GLOB_PSIZE_4096 0x01
35#define GLOB_PSIZE_6144 0x10
36#define GLOB_PSIZE_8192 0x11
37
38
39#define CREG_CTRL 0x00UL
40#define CREG_STAT 0x04UL
41#define CREG_RXDS 0x08UL
42#define CREG_TXDS 0x0cUL
43#define CREG_RIMASK 0x10UL
44#define CREG_TIMASK 0x14UL
45#define CREG_QMASK 0x18UL
46#define CREG_BMASK 0x1cUL
47#define CREG_RXWBUFPTR 0x20UL
48#define CREG_RXRBUFPTR 0x24UL
49#define CREG_TXWBUFPTR 0x28UL
50#define CREG_TXRBUFPTR 0x2cUL
51#define CREG_CCNT 0x30UL
52#define CREG_REG_SIZE 0x34UL
53
54#define CREG_CTRL_TWAKEUP 0x00000001
55
56#define CREG_STAT_BERROR 0x80000000
57#define CREG_STAT_TXIRQ 0x00200000
58#define CREG_STAT_TXDERROR 0x00080000
59#define CREG_STAT_TXLERR 0x00040000
60#define CREG_STAT_TXPERR 0x00020000
61#define CREG_STAT_TXSERR 0x00010000
62#define CREG_STAT_RXIRQ 0x00000020
63#define CREG_STAT_RXDROP 0x00000010
64#define CREG_STAT_RXSMALL 0x00000008
65#define CREG_STAT_RXLERR 0x00000004
66#define CREG_STAT_RXPERR 0x00000002
67#define CREG_STAT_RXSERR 0x00000001
68
69#define CREG_STAT_ERRORS (CREG_STAT_BERROR|CREG_STAT_TXDERROR|CREG_STAT_TXLERR| \
70 CREG_STAT_TXPERR|CREG_STAT_TXSERR|CREG_STAT_RXDROP| \
71 CREG_STAT_RXSMALL|CREG_STAT_RXLERR|CREG_STAT_RXPERR| \
72 CREG_STAT_RXSERR)
73
74#define CREG_QMASK_TXDERROR 0x00080000
75#define CREG_QMASK_TXLERR 0x00040000
76#define CREG_QMASK_TXPERR 0x00020000
77#define CREG_QMASK_TXSERR 0x00010000
78#define CREG_QMASK_RXDROP 0x00000010
79#define CREG_QMASK_RXBERROR 0x00000008
80#define CREG_QMASK_RXLEERR 0x00000004
81#define CREG_QMASK_RXPERR 0x00000002
82#define CREG_QMASK_RXSERR 0x00000001
83
84
85#define BMAC_XIFCFG 0x000UL
86
87#define BMAC_STATUS 0x100UL
88#define BMAC_IMASK 0x104UL
89
90#define BMAC_TXSWRESET 0x208UL
91#define BMAC_TXCFG 0x20cUL
92#define BMAC_IGAP1 0x210UL
93#define BMAC_IGAP2 0x214UL
94#define BMAC_ALIMIT 0x218UL
95#define BMAC_STIME 0x21cUL
96#define BMAC_PLEN 0x220UL
97#define BMAC_PPAT 0x224UL
98#define BMAC_TXDELIM 0x228UL
99#define BMAC_JSIZE 0x22cUL
100#define BMAC_TXPMAX 0x230UL
101#define BMAC_TXPMIN 0x234UL
102#define BMAC_PATTEMPT 0x238UL
103#define BMAC_DTCTR 0x23cUL
104#define BMAC_NCCTR 0x240UL
105#define BMAC_FCCTR 0x244UL
106#define BMAC_EXCTR 0x248UL
107#define BMAC_LTCTR 0x24cUL
108#define BMAC_RSEED 0x250UL
109#define BMAC_TXSMACHINE 0x254UL
110
111#define BMAC_RXSWRESET 0x308UL
112#define BMAC_RXCFG 0x30cUL
113#define BMAC_RXPMAX 0x310UL
114#define BMAC_RXPMIN 0x314UL
115#define BMAC_MACADDR2 0x318UL
116#define BMAC_MACADDR1 0x31cUL
117#define BMAC_MACADDR0 0x320UL
118#define BMAC_FRCTR 0x324UL
119#define BMAC_GLECTR 0x328UL
120#define BMAC_UNALECTR 0x32cUL
121#define BMAC_RCRCECTR 0x330UL
122#define BMAC_RXSMACHINE 0x334UL
123#define BMAC_RXCVALID 0x338UL
124
125#define BMAC_HTABLE3 0x340UL
126#define BMAC_HTABLE2 0x344UL
127#define BMAC_HTABLE1 0x348UL
128#define BMAC_HTABLE0 0x34cUL
129#define BMAC_AFILTER2 0x350UL
130#define BMAC_AFILTER1 0x354UL
131#define BMAC_AFILTER0 0x358UL
132#define BMAC_AFMASK 0x35cUL
133#define BMAC_REG_SIZE 0x360UL
134
135
136#define BIGMAC_XCFG_ODENABLE 0x00000001
137#define BIGMAC_XCFG_RESV 0x00000002
138#define BIGMAC_XCFG_MLBACK 0x00000004
139#define BIGMAC_XCFG_SMODE 0x00000008
140
141
142#define BIGMAC_STAT_GOTFRAME 0x00000001
143#define BIGMAC_STAT_RCNTEXP 0x00000002
144#define BIGMAC_STAT_ACNTEXP 0x00000004
145#define BIGMAC_STAT_CCNTEXP 0x00000008
146#define BIGMAC_STAT_LCNTEXP 0x00000010
147#define BIGMAC_STAT_RFIFOVF 0x00000020
148#define BIGMAC_STAT_CVCNTEXP 0x00000040
149#define BIGMAC_STAT_SENTFRAME 0x00000100
150#define BIGMAC_STAT_TFIFO_UND 0x00000200
151#define BIGMAC_STAT_MAXPKTERR 0x00000400
152#define BIGMAC_STAT_NCNTEXP 0x00000800
153#define BIGMAC_STAT_ECNTEXP 0x00001000
154#define BIGMAC_STAT_LCCNTEXP 0x00002000
155#define BIGMAC_STAT_FCNTEXP 0x00004000
156#define BIGMAC_STAT_DTIMEXP 0x00008000
157
158
159#define BIGMAC_IMASK_GOTFRAME 0x00000001
160#define BIGMAC_IMASK_RCNTEXP 0x00000002
161#define BIGMAC_IMASK_ACNTEXP 0x00000004
162#define BIGMAC_IMASK_CCNTEXP 0x00000008
163#define BIGMAC_IMASK_LCNTEXP 0x00000010
164#define BIGMAC_IMASK_RFIFOVF 0x00000020
165#define BIGMAC_IMASK_CVCNTEXP 0x00000040
166#define BIGMAC_IMASK_SENTFRAME 0x00000100
167#define BIGMAC_IMASK_TFIFO_UND 0x00000200
168#define BIGMAC_IMASK_MAXPKTERR 0x00000400
169#define BIGMAC_IMASK_NCNTEXP 0x00000800
170#define BIGMAC_IMASK_ECNTEXP 0x00001000
171#define BIGMAC_IMASK_LCCNTEXP 0x00002000
172#define BIGMAC_IMASK_FCNTEXP 0x00004000
173#define BIGMAC_IMASK_DTIMEXP 0x00008000
174
175
176#define BIGMAC_TXCFG_ENABLE 0x00000001
177#define BIGMAC_TXCFG_FIFO 0x00000010
178#define BIGMAC_TXCFG_SMODE 0x00000020
179#define BIGMAC_TXCFG_CIGN 0x00000040
180#define BIGMAC_TXCFG_FCSOFF 0x00000080
181#define BIGMAC_TXCFG_DBACKOFF 0x00000100
182#define BIGMAC_TXCFG_FULLDPLX 0x00000200
183
184
185#define BIGMAC_RXCFG_ENABLE 0x00000001
186#define BIGMAC_RXCFG_FIFO 0x0000000e
187#define BIGMAC_RXCFG_PSTRIP 0x00000020
188#define BIGMAC_RXCFG_PMISC 0x00000040
189#define BIGMAC_RXCFG_DERR 0x00000080
190#define BIGMAC_RXCFG_DCRCS 0x00000100
191#define BIGMAC_RXCFG_ME 0x00000200
192#define BIGMAC_RXCFG_PGRP 0x00000400
193#define BIGMAC_RXCFG_HENABLE 0x00000800
194#define BIGMAC_RXCFG_AENABLE 0x00001000
195
196
197
198
199#define TCVR_TPAL 0x00UL
200#define TCVR_MPAL 0x04UL
201#define TCVR_REG_SIZE 0x08UL
202
203
204#define FRAME_WRITE 0x50020000
205#define FRAME_READ 0x60020000
206
207
208#define TCVR_PAL_SERIAL 0x00000001
209#define TCVR_PAL_EXTLBACK 0x00000002
210#define TCVR_PAL_MSENSE 0x00000004
211#define TCVR_PAL_LTENABLE 0x00000008
212#define TCVR_PAL_LTSTATUS 0x00000010
213
214
215#define MGMT_PAL_DCLOCK 0x00000001
216#define MGMT_PAL_OENAB 0x00000002
217#define MGMT_PAL_MDIO 0x00000004
218#define MGMT_PAL_TIMEO 0x00000008
219#define MGMT_PAL_EXT_MDIO MGMT_PAL_MDIO
220#define MGMT_PAL_INT_MDIO MGMT_PAL_TIMEO
221
222
223#define BIGMAC_PHY_EXTERNAL 0
224#define BIGMAC_PHY_INTERNAL 1
225
226
227struct be_rxd {
228 u32 rx_flags;
229 u32 rx_addr;
230};
231
232#define RXD_OWN 0x80000000
233#define RXD_UPDATE 0x10000000
234#define RXD_LENGTH 0x000007ff
235
236struct be_txd {
237 u32 tx_flags;
238 u32 tx_addr;
239};
240
241#define TXD_OWN 0x80000000
242#define TXD_SOP 0x40000000
243#define TXD_EOP 0x20000000
244#define TXD_UPDATE 0x10000000
245#define TXD_LENGTH 0x000007ff
246
247#define TX_RING_MAXSIZE 256
248#define RX_RING_MAXSIZE 256
249
250#define TX_RING_SIZE 256
251#define RX_RING_SIZE 256
252
253#define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1))
254#define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
255#define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1))
256#define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
257
258#define TX_BUFFS_AVAIL(bp) \
259 (((bp)->tx_old <= (bp)->tx_new) ? \
260 (bp)->tx_old + (TX_RING_SIZE - 1) - (bp)->tx_new : \
261 (bp)->tx_old - (bp)->tx_new - 1)
262
263
264#define RX_COPY_THRESHOLD 256
265#define RX_BUF_ALLOC_SIZE (ETH_FRAME_LEN + (64 * 3))
266
267struct bmac_init_block {
268 struct be_rxd be_rxd[RX_RING_MAXSIZE];
269 struct be_txd be_txd[TX_RING_MAXSIZE];
270};
271
272#define bib_offset(mem, elem) \
273((__u32)((unsigned long)(&(((struct bmac_init_block *)0)->mem[elem]))))
274
275
276enum bigmac_transceiver {
277 external = 0,
278 internal = 1,
279 none = 2,
280};
281
282
283enum bigmac_timer_state {
284 ltrywait = 1,
285 asleep = 2,
286};
287
288struct bigmac {
289 void __iomem *gregs;
290 void __iomem *creg;
291 void __iomem *bregs;
292 void __iomem *tregs;
293 struct bmac_init_block *bmac_block;
294 __u32 bblock_dvma;
295
296 spinlock_t lock;
297
298 struct sk_buff *rx_skbs[RX_RING_SIZE];
299 struct sk_buff *tx_skbs[TX_RING_SIZE];
300
301 int rx_new, tx_new, rx_old, tx_old;
302
303 int board_rev;
304
305 enum bigmac_transceiver tcvr_type;
306 unsigned int bigmac_bursts;
307 unsigned int paddr;
308 unsigned short sw_bmsr;
309 unsigned short sw_bmcr;
310 struct timer_list bigmac_timer;
311 enum bigmac_timer_state timer_state;
312 unsigned int timer_ticks;
313
314 struct net_device_stats enet_stats;
315 struct platform_device *qec_op;
316 struct platform_device *bigmac_op;
317 struct net_device *dev;
318};
319
320
321#define ALIGNED_RX_SKB_ADDR(addr) \
322 ((((unsigned long)(addr) + (64 - 1)) & ~(64 - 1)) - (unsigned long)(addr))
323
324static inline struct sk_buff *big_mac_alloc_skb(unsigned int length, gfp_t gfp_flags)
325{
326 struct sk_buff *skb;
327
328 skb = alloc_skb(length + 64, gfp_flags);
329 if(skb) {
330 int offset = ALIGNED_RX_SKB_ADDR(skb->data);
331
332 if(offset)
333 skb_reserve(skb, offset);
334 }
335 return skb;
336}
337
338#endif
339